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Get rid of legacy pad macros by replacing them with their newer
equivalents.
TEST: TIMELESS-built board images match
Change-Id: I078f9bb3c78f642afc6dcfd64d77be823a4485c2
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46567
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Stefan thinks they don't add value.
Command used:
sed -i -e '/file is part of /d' $(git grep "file is part of " |egrep ":( */\*.*\*/\$|#|;#|-- | *\* )" | cut -d: -f1 |grep -v crossgcc |grep -v gcov | grep -v /elf.h |grep -v nvramtool)
The exceptions are for:
- crossgcc (patch file)
- gcov (imported from gcc)
- elf.h (imported from GNU's libc)
- nvramtool (more complicated header)
The removed lines are:
- fmt.Fprintln(f, "/* This file is part of the coreboot project. */")
-# This file is part of a set of unofficial pre-commit hooks available
-/* This file is part of coreboot */
-# This file is part of msrtool.
-/* This file is part of msrtool. */
- * This file is part of ncurses, designed to be appended after curses.h.in
-/* This file is part of pgtblgen. */
- * This file is part of the coreboot project.
- /* This file is part of the coreboot project. */
-# This file is part of the coreboot project.
-# This file is part of the coreboot project.
-## This file is part of the coreboot project.
--- This file is part of the coreboot project.
-/* This file is part of the coreboot project */
-/* This file is part of the coreboot project. */
-;## This file is part of the coreboot project.
-# This file is part of the coreboot project. It originated in the
- * This file is part of the coreinfo project.
-## This file is part of the coreinfo project.
- * This file is part of the depthcharge project.
-/* This file is part of the depthcharge project. */
-/* This file is part of the ectool project. */
- * This file is part of the GNU C Library.
- * This file is part of the libpayload project.
-## This file is part of the libpayload project.
-/* This file is part of the Linux kernel. */
-## This file is part of the superiotool project.
-/* This file is part of the superiotool project */
-/* This file is part of uio_usbdebug */
Change-Id: I82d872b3b337388c93d5f5bf704e9ee9e53ab3a9
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41194
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Done with sed and God Lines. Only done for C-like code for now.
Change-Id: Idfc7a5713e231c4756b5faca8984c6598fe1e65a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40190
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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They're listed in AUTHORS and often incorrect anyway, for example:
- What's a "Copyright $year-present"?
- Which incarnation of Google (Inc, LLC, ...) is the current
copyright holder?
- People sometimes have their editor auto-add themselves to files even
though they only deleted stuff
- Or they let the editor automatically update the copyright year,
because why not?
- Who is the copyright holder "The coreboot project Authors"?
- Or "Generated Code"?
Sidestep all these issues by simply not putting these notices in
individual files, let's list all copyright holders in AUTHORS instead
and use the git history to deal with the rest.
Change-Id: I09cc279b1f75952bb397de2c3f2b299255163685
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39607
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
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If GPP_E22(CABC_EN) remained floating GPI(SoC default) at V3.3_DX_EDP on,
it may cause damage on the GPIO pad.
To prevent, we would set this pad to GPO on romstage before EDP power on.
Since we need to cover all systems in market, I put it into romstage
instead of early_gpio_table.
BUG=b:111860510
BRANCH=poppy
TEST=Verified CABC_EN is set to GPO high 5ms before EDP power on
Change-Id: I34e2fe86329a88eb05e0ea3c6beac6a64754b41e
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com>
Reviewed-on: https://review.coreboot.org/27773
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Currently, default GPP_D21(LTE3_BODY_SAR) output level is low, it means
LTE tx power is backoff mode as default.
We would set GPP_D21 to high to change LTE tx power to normal mode as
default.
BUG=None
BRANCH=poppy
TEST=Verified default LTE tx power mode is normal mode as default
Change-Id: I62e77196c2116924f437f61368f0ae7efd0e144c
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com>
Reviewed-on: https://review.coreboot.org/27661
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Nautilus-WiFi board doesn't have external pull-up on USB2_OC2# route,then
abnormal over-current is asserted on USB type-A port.
It causes USB type-A port to be blocked, so we need this internal pull-up.
BUG=b:111578984
BRANCH=poppy
TEST=Verified over-current not triggered abnormally on basic sku board
Change-Id: I159f686cef9c8d254f390d7f1dff8011f43fc066
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com>
Reviewed-on: https://review.coreboot.org/27542
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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For supporting new SKU, we need to override GPIO table and device configuration.
The board ID of 2nd SKU of nautilus is started from 9, so we would determine SKU with it.
BUG=b:80052672
BRANCH=poppy
TEST=emerge-nautilus coreboot
Change-Id: I7242f23f47010664cc29ea86a126e63c9dd62ccd
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com>
Reviewed-on: https://review.coreboot.org/27147
Reviewed-by: Enrico Granata <egranata@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Due to schematic, we need to correct USB OC pin configuration.
- OC0 for Type-C Port 1
- OC1 for Type-C Port 0
- OC2 for Type-A Port
- OC3 to NC
BUG=NONE
BRANCH=poppy
TEST=emerge-nautilus coreboot
Change-Id: Ic71baef646926cc6aadcc5dda7cb14f00e8d3687
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com>
Reviewed-on: https://review.coreboot.org/27099
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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This change configures GPP_E22 to GPO_HIGH to enable CABC feature
on nautilus board.
BUG=b:68789889
BRANCH=poppy
TEST=emerge-nautilus coreboot
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com>
Change-Id: Ifed0d37bf8147aa1b580f594f36f186051c2eb52
Reviewed-on: https://review.coreboot.org/25120
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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As per the latest schematics, this change configures GPP_B0 as wake
source for WLAN.
BUG=NONE
BRANCH=master
TEST=emerge-nautilus coreboot
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com>
Change-Id: I72b940452cfbbe471279ef117a868a8ae0b65b8b
Reviewed-on: https://review.coreboot.org/23526
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This change uses gpio_keys driver to add ACPI node for pen eject event.
BUG=b:71329519
TEST=Verified using evtest that pen eject event results in events as
expected.
Change-Id: Ib293c2ca532c8ed9e2587143b1a69300cd9fa4e9
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/23238
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
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This change updates the camera power enable GPIOs as per the latest
schematics. With this update, since one of the enable GPIOs is using a
UART0 pin, set UART0 to PchSerialIoSkipInit in devicetree so that
FSP-S does not re-configure the UART0 GPIOs.
BUG=b:68964831
Change-Id: I5d9126ed8ca2b714f6276f4d3a24c243d7654774
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/23414
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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- Add pen device property into devicetree.cb.
- Set GPP_C9 to 0 as default.
BUG=none
BRANCH=master
TEST=emerge-nautilus coreboot and check pen device operation
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com>
Change-Id: I050671c8b46fd92b1dd9164be2646727cd67da9f
Reviewed-on: https://review.coreboot.org/23010
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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GPP_F3 is not connected on poppy or any of its variants. This change
configures GPP_F3 as NC on poppy and all the variants.
BUG=b:70160119
Change-Id: I303276ab9546d56c846755fa3a6142978f6b8c92
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/22917
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Variants nautilus and soraka currently provide the exact same
definition for variant_cros_gpios as provided by the baseboard. This
change removes the function defintions from variants so that the weak
definition in baseboard can be used.
Change-Id: Ic88623f34039792f0f9fb46842b24e4f1290981b
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/22705
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Enable Dialog DA7219 codec i2c device and add required SSDT parameters
BUG=b:68686020
TEST=With req'd driver support in kernel v4.4 verify audio on headset
Change-Id: Ic815c929f29bec0d26a2981e9933b752c2d84c70
Signed-off-by: Naveen Manohar <naveen.m@intel.com>
Signed-off-by: Shruthi Sudhakar <shruthi.sudhakar@intel.com>
Reviewed-on: https://review.coreboot.org/22264
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Update GPIO settings to meet nautilus's schematic design.
BRANCH=master
BUG=b:66462881
TEST=emerge-nautilus coreboot
Change-Id: I11930df62130431764702371a3ba84949a65ba30
Signed-off-by: Chris Wang <chriswang@ami.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/22183
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: shkim <sh_.kim@samsung.com>
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Create Nautilus board which derives from Poppy, a KBL reference board.
BRANCH=master
BUG=b:66462881
TEST=Build (as initial setup)
Change-Id: I6ca5ab821a7ba1746b37dfd3ea1ed367094d4f52
Signed-off-by: Chris Wang <chriswang@ami.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/21895
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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