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path: root/src/mainboard/google/poppy/variants/nami
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2018-08-14mb/google/poppy/variant/nami: Add TSR2 on DPTFT.H. Lin
Add TSR2 DART/DTRT package BUG=b:110451144 BRANCH=nami TEST=emerge-nami coreboot chromeos-bootimage Test image with dptf.dv Change-Id: I3328e17328415f5ebdcf84263e5456e11e55f769 Signed-off-by: T.H. Lin <t.h_lin@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/27999 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2018-08-02mb/google/poppy/variants/nami: Tune Fan speedSumeet Pawnikar
Tuning of fan speed for different temperature values. Earlier while running few benchmarks, fan was always getting on and starting at higher speed. With this change fan will start with lower speed and slowly speed gets increased if temperature continue going high. Thermal team provided these data after fine tuning of fan speed. BUG=None. TEST=Verified on Nami running with different benchmarks and observed fan speed. Change-Id: Ic3be9e44deef9570200c71807a2ee712d9f20876 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/27683 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-02mb/google/poppy/variants/nami: Enable mbox command for ISL VR c-state issueShelley Chen
There is a potential IMVP8 issue for KBL that affects Intersil VRs Nami is using one of the affected parts. The fix is to use an updated microcode and also send a mailbox box command from FSP. BUG=b:112081534 BRANCH=None TEST=Build and boot Nami Verify that suspend/resume and consecutive reboots are working Change-Id: I6ec18a4c3fae6a66cf8a95685d91a8ba51e2697c Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/27780 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-08-01mb/google/poppy/variant/nami: Overwrite AC/DC loadlinesGaggery Tsai
This patch adds a function to overwrite AC/DC loadlines for differnt projects. BUG=b:111761175 BRANCH=None TEST=emerge-nami coreboot chromeos-bootimage and use DCI to dump AC/DC loadline settings. Tested on Vayne and Akali. Change-Id: Id0068c5334c257b9f4c32b6088becbfe8391a864 Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com> Reviewed-on: https://review.coreboot.org/27644 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-07-30mb/google/poppy/variants/nami: Fix fan is always ONJohn Su
Add the new setting for fan performance state. BUG=b:111860513, b:11865138 TEST=Fan do not run below trip point Change-Id: I894460b8b418217e2477608094c37018437cbb78 Signed-off-by: John Su <john_su@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/27662 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2018-07-24mb/google/poppy/variant/nami: Add custom VBT for panel T8/T10T.H. Lin
Fix VBT SSF setting for panel T8/T10 as Akali/Akali360 panel has T8 minimum 33.3 ms and T10 minimum of 100 ms. BUG=b:111530392 BRANCH=nami TEST=emerge-nami coreboot chromeos-bootimage Test & measure T8/T10 waveform Change-Id: I642a1aa0b2d13b33e6113f94e73dfc77834766d4 Signed-off-by: T.H. Lin <t.h_lin@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/27507 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-07-13mb/google/poppy/variants/nami: Use Pantheon VBTIvy Jian
Add new Pantheon sku-id for loading vbt-pantheon.bin BUG=b:78663963 BRANCH=firmware-nami-10775.B TEST=Boots to OS and display comes up. Check the board specific vbt binary loaded. Change-Id: I1ee156372754ac0e77caae5959a9ca9884de95f4 Signed-off-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/27432 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-11skylake: Remove "IshEnable"li feng
Remove "IshEnable" from soc_intel_skylake_config since it's not used anymore. Enable/disable ISH by checking if ISH device is turned on or not. Refer to https://review.coreboot.org/#/c/coreboot/+/26485/. BUG=b:79244403 BRANCH=none TEST=Built. Change-Id: I4d2889af118659852431c87cb516fd19b577efc5 Signed-off-by: li feng <li1.feng@intel.com> Reviewed-on: https://review.coreboot.org/26521 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-07-02mb/google/poppy/variants/nami: Perform PL2 setting for sonaJohn Su
According to sona thermal table, PL2 need to check cpu id. And then set PL2 value. BUG=b:110867809 TEST=The thermal team verify OK Change-Id: I5759fb3c685e3d4eef1be054541f950843d19874 Signed-off-by: John Su <john_su@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/27260 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2018-06-25mb/google/poppy/variants/nami: Prevent leakage with touchscreen on PantheonCrystal Lin
We found GPP_C3 keeps high when system in S0ix mode. It caused 1.8V leakage. To fix this problem, add GPP_C3 into config for Pantheon Synaptics touchscreen. BUG=b:78436458 BRANCH=None TEST=Let DUT in S0ix mode and check GPP_C3 is normal. Change-Id: Idb2dab93178af1dae54265e49522b473b69a35af Signed-off-by: Crystal Lin <crystal_lin@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/27177 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-25mb/google/nami: Enable xDCIShelley Chen
This change enables xDCI controller on nami. BUG=b:110443736 BRANCH=None TEST=None Change-Id: Ieb63e0d65ac1a142c151a3f93afe306b80a5d99a Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/27181 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-22mb/google/poppy/variants/nami: Fix non-working thermal sensor QT2 PSVJohn Su
Modify DPTF TRT parameters to solve thermal sensor QT2 PSV problem. BUG=b:109941652 TEST=The thermal team verify OK Change-Id: Id9d39d8282712a0341fea10f74c0e40bb1ac9d7c Signed-off-by: John Su <john_su@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/27088 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-06-15mb/google/poppy/variants/nami: Update DPTF table from version 1.5John Su
Update dptf.asl and TCC parameters from tuning of the thermal team. BUG=b:72974136 TEST=Match the result from DPTF UI Change-Id: Ic0ffc169ad3939cacb46824ed23999c61a23d2c4 Signed-off-by: John Su <john_su@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/27086 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-11mb/google/poppy/variants/nami: Add EC_ENABLE_TBMC_DEVICEShelley Chen
Add tablet motion control config to nami devices. BUG=None BRANCH=None TEST=run evtest make sure tablet switch value is 1 in tablet mode and 0 when not in tablet mode Change-Id: Ie1480934dc003d9b467883e001ed89f9a3694d10 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/26970 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-07mb/google/poppy/variants/nami: Disable rear camera/DMIC for SonaAmanda Huang
Since there are two cameras on Nami and only one camera on Sona. We need to disable rear camera/DMIC on all Sona sku. BUG=b:109710674 BRANCH=master TEST=Verify if only front camera/DMIC shown on Sona Change-Id: Id84ee22c9ffc15db78be3bbad148af5cd7dc866e Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/26876 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-06-07mb/google/poppy/variants/nami: Disable rear camera/DMIC for PantheonAmanda Huang
Since there are two cameras on Nami and only one camera on Pantheon. We need to disable rear camera/DMIC on all Pantheon sku. BUG=b:109720689 BRANCH=master TEST=Verify if only front camera/DMIC shown on Pantheon Change-Id: Ibe48a945dc57f2c05344479253040ad1945d92fd Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/26875 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-06-06mb/google/poppy/variants/nami: Add delay to enable_gpio during Elan power onShelley Chen
During measurement of signals during Elan touchscreen power on, saw that the enable_gpio delay was not sufficient as there is a +1.5 ms delay during power on. Adding more delay to take this into account. BUG=b:78311818 BRANCH=None TEST=probe power on signals to ensure meet timing requirements Change-Id: Id661a202188a97aef97514ebecd0be6fc022d21e Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/26725 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-06-06mb/google/poppy/variants/nami: Fix Elan touchscreen power off sequenceShelley Chen
Power off does not seem to use the ACPI _OFF function, but rather the smihandler. Creating variant_smi_sleep function for nami to handle the power off sequence during reboot/power off. BUG=b:78311818 BRANCH=None TEST=Run "poweroff" command from AP console with SMI_DEBUG enabled Make sure delays are consistent with spec Change-Id: Ifeea545fe268be249793b3e508c51f5e4c1a3460 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/26724 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-06-06soc/intel/common/block: Add common chip config blockSubrata Banik
Adding common chip config structure which will be used to return data to common code. When common code requires soc data, code used to fetch entire soc config structure. With this change, common code will only get the data/structure which is required by common code and not entire config. For now, adding i2c, gspi and lockdown configuration which will be used by common code. BUG=none BRANCH=b:78109109 TEST=compile code for APL/SKL/CNL. Boot using SKL/APL/CNL and check values are returned properly using common structure. Change-Id: I7f1671e064782397d3ace066a08bf1333192b21a Signed-off-by: Subrata Banik <subrata.banik@intel.com> Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/26189 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Hannah Williams <hannah.williams@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-05mb/google/poppy/variants/nami: Disable rear camera/DMIC for vayne skuid 3A67Van Chen
Since Vayne added one more skuid 3A67, we need to disable rear camera/DMIC for vayne skuid 3A67. BUG=b:75073617 BRANCH=master TEST=Verify if only front camera/DMIC shown on Vayne Change-Id: I9131b4c41bf189829be4e7e6bfaf4a96765cfa15 Signed-off-by: Van Chen <van_chen@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/26855 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-05soc/intel/skylake: Add option to skip coreboot MP initSubrata Banik
This patch provides option for mainboard to skip coreboot MP initialization if required based on use_fsp_mp_init. Option for mainboard to skip coreboot MP initialization * 0 = Make use of coreboot MP Init * 1 = Make use of FSP MP Init Default coreboot does MP initialization. Change-Id: I8de24e662963f4600209ad1b110dc950ecfb3a27 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/26818 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-03mb/google/poppy/variants/nami: Load vayne VBT binaryIvy Jian
Load vbt-vayne.bin by reading sku-id. BUG=b:80509366 TEST=Boots to OS and display comes up. Check the board specific vbt binary loaded. Change-Id: Ia26ea4a9b7679aeb9d98f19ffaa1b686af828339 Signed-off-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/26749 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-05-25mb/google/poppy/variants/nami: Perform PL2 setting in variant_devtree_udpateFurquan Shaikh
This change moves PL2 override to variant_devtree_update for two reasons: 1. This function was added to basically override devtree settings in variant specific code. So, it would be a good idea to perform all the overrides in a single place. 2. Adding a device for performing nami_enable would require changes to devicetree and special handling for calling this device enable. Thus, nami_enable was never getting called. BUG=b:80148703 Change-Id: Ifa24a7b6e99cad2368b3d656a757f26297373121 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/26499 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-05-25mb/google/poppy/variants/nami: Use GPP_E4 for BT_OFF#Frank Wu
The BT W_DISABLE2# pin is connected to GPP_E4 in the latest schematic. Update GPP_E4 as GPO and set 1 as default. BUG=b:79993692, b:72007632 BRANCH=None TEST=Enable/disable BT/WLAN by following command. Enable: localhost ~ # iotools mmio_write32 0xfdae0590 0x40000201 localhost ~ # iotools mmio_write32 0xfdae05a0 0x40000201 Disable: localhost ~ # iotools mmio_write32 0xfdae0590 0x40000200 localhost ~ # iotools mmio_write32 0xfdae05a0 0x40000200 Change-Id: I9ef1a5314652ab29172d246abd58ee4e1a8a6299 Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/26502 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-18mb/google/poppy/variants/nami: Fix SoC I2C CLK is abnormalChris Zhou
The I2C CLKs of SoC should be 400kHz, but waveform show 460kHz to 470kHz. Add I2C parameters to adjust I2C CLKs which 5% lower than 400kHz. BUG=b:78819970 TEST=The I2C CLKs are 5% lower than 400kHz. Change-Id: I2c3012b5b59c089801cda8fd7b0c433aad9df36d Signed-off-by: Chris Zhou <chris_zhou@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/26282 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Shelley Chen <shchen@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-17mb/google/poppy/variants/nami: Update DPTF tableJohn Su
Update dptf.asl from tuning of the thermal team. BUG=b:72974136 TEST=Match the result from DPTF UI. Change-Id: I21ddc337359c3e11ad9756e61ba174b33dfc3c75 Signed-off-by: John Su <john_su@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/26209 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2018-05-17mb/google/poppy: Disable one ALS nodeAmanda Huang
Since there are two ALS device nodes on Nami, need to remove one. BUG=b:79227879 BRANCH=master TEST=Verify if only one ALS node is found in /sys/bus/iio/devices Change-Id: I850af06bec833739afa0c8c516d351d81952ce2c Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/26271 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-16mb/google/poppy/variants/nami: Load pantheon VBT binaryIvy Jian
Load pantheon.bin by reading sku-id. BUG=b:78663963 TEST=Boots to OS and display comes up. Check the board specific vbt binary loaded. Change-Id: I66cb43d87363b3e8b1a1498cdae8eeeb8b75219d Signed-off-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/26267 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-05-16mb/google/poppy/variants/nami: Enable synaptics touchscreen supportIvy Jian
BUG=b:74595040 BRANCH=master TEST= 1. emerge-nami coreboot chromeos-bootimage 2. Booted on Pantheon with S7817 PCBa connected 3. Check touchscreen device is enabled by evtest /dev/input/event4: SYTS7817:00 06CB:7817 Change-Id: Ic11684d5ed961af5eb704909f7d06eb0898068c2 Signed-off-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/25915 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-05-12mb/google/poppy/variants/nami: Provide implementation of mainboard_vbt_filenameFurquan Shaikh
This change adds board-specific implementation of mainboard_vbt_filename which returns "vbt.bin" by default. This is in preparation to allow multiple vbt binaries to be added to single image. More sku_id specific names will be added in follow-up CLs. BUG=b:79396300 Change-Id: I3821d55bfbe9e5773bd2eb0b0003045a80158d8c Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/26227 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-05-11mb/google/poppy/variants/nami: add 2-channel LPDDR3 memoryT.H. Lin
hynix/H9CCNNNCLGALAR-NUD nayna/NT6CL256T32CM-H1 BUG=b:79443146 BRANCH=Nami TEST=emerge-nami coreboot chromeos-bootimage Change-Id: I3a362080b9e60adecbac14d5cfe193da44bf87c8 Signed-off-by: T.H. Lin <t.h_lin@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/26187 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-05-09mb/google/poppy/variants/nami: Add support for getting OEM name from CBFSFurquan Shaikh
This change: 1. Allows mainboard to add OEM table to CBFS 2. Provides mainboard specific smbios_mainboard_manufacturer that reads OEM ID from EC using CBI and compares it against the OEM ID in CBFS table to identify the right OEM string. BUG=b:74617340 Change-Id: Iff54b12745de3efa7be0801c9a3a9f2a57767dde Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/26142 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-05-08mb/google: Get rid of device_tElyes HAOUAS
Use of device_t has been abandoned in ramstage. Change-Id: I8e549e4222ae2ed6b9c46f81c5b5253e8b227ee8 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26086 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-05-07mb/google/poppy/variants/nami: Invert polarity of EMR_GARAGE_DET#Shelley Chen
This gpio should be active low, but is not currently configured that way. Changing gpio configuration to reflect that. BUG=b:73121017, b:77941823 BRANCH=None TEST=iotools mmio_read32 0xfdae0588 (GPP_E1) Make sure that when pen is ejected, gpio is low and when pen is inserted, gpio is high. Also tested that wake upon pen eject is working. Change-Id: Ic49eea6412c3378dca39a3338b43df12bc27037d Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/26017 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-02mb/google/poppy/variants/nami: Enable touchscreen through ACPIShelley Chen
Currently, we've set TOUCHSCREEN_DIS gpio to disabled. Enabling through ACPI. Set reset/enable/stop_off_ms variables to get timings of power off sequence correct. BUG=b:78311818 BRANCH=None TEST=./util/abuild/abuild -p none -t google/poppy -x -a Change-Id: Ib1543f41f24cbe8c33aeb02e6aa43fd3dd977ed4 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/25754 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2018-05-01mb/google/poppy/variants/nami: Enable Synaptics touchpadivy_jian
BUG=b:74595037 TEST= 1. emerge-nami coreboot chromeos-bootimage 2. check touchpad function 3. evtest /dev/input/event5: PNP0C50:00 06CB:CD84 Change-Id: I47cb1b13881f0d52860f0afe4bbca7483409de54 Signed-off-by: ivy_jian <ivy_jian@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/25913 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-24mb/google/poppy/variants/nami: Add keyboard backlight supportZhuohao Lee
This change adds keyboard backlight feature for Nami platform BUG=b:78360907 BRANCH=none TEST=keyboard backlight works when EC reports correct info. Change-Id: I3fceb83e155032b6e9f1763c4e2a29e7521269d2 Signed-off-by: Zhuohao Lee <zhuohao@chromium.org> Reviewed-on: https://review.coreboot.org/25782 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-04-18mb/google/poppy/variants: Set VmxEnable to 1Furquan Shaikh
This change sets VmxEnable to 1 to match the kernel setting. If this feature is enabled at the kernel level and not in FSP, then there is an issue where FSP expects it to be disabled so it forces a cold reboot on every warm reboot. BUG=b:78129261 BRANCH=poppy Change-Id: Idedbde1d8eb0c9e959733b7b50e5dec804d61cae Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/25698 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-17mb/google/poppy/variants/nami: Update GPIOsShelley Chen
Updating some GPIOs based on changes in the latest schematics. Also renaming signals to match that of latest schematics. BUG=b:73749640 BRANCH=None TEST=./util/abuild/abuild -p none -t google/poppy -x -a Make sure different SKUs still boot. Change-Id: I7d912f4bc6765f065c75c68a45bdf9ee844e0c1d Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/25646 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-04-17mb/google/poppy/variants/nami: Enable DPTF and configure DPTF parametersFrank Wu
The commit enables DPTF function. The DPTF parameters are provided by thermal team. BUG=b:72974136 BRANCH=poppy TEST=emerge-nami coreboot then check the parameters in DPTF ui tool Change-Id: I9b7ae34ee64f19ef783a8c1571831b2293105a18 Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/25564 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-04-16mb/google/poppy/variants/nami: Add SPD file for PantheonChris Zhou
Add SPD file for sdp hynix_dimm_H5AN8G6NCJR-VKC (ram id: 15). BUG=b:77893710 TEST=Verified that the device with this memory part boots to OS fine. Change-Id: I434d42ff12e6dae39e5676f36ba6cf00b3a48b06 Signed-off-by: Chris Zhou <chris_zhou@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/25655 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-04-16mb/google/poppy/variants/nami: Add SPD file for PantheonChris Zhou
Add SPD file for sdp micron_dimm_MT40A512M16LY-075E (ram id: 14). BUG=b:77930401 TEST=Verified that the device with this memory part boots to OS fine. Change-Id: Ia44e70948e57c2f19664d874ae005ac39d748f92 Signed-off-by: Chris Zhou <chris_zhou@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/25654 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-04-10mb/google/poppy: Disable rear camera for all vayne skuAmanda Huang
Since there are two cameras on Nami and only one camera on Vayne. We need to disable rear camera on all Vayne sku. BUG=b:75073617 BRANCH=master TEST=Verify if only front camera shown on Vayne Change-Id: I6e7c1e8791462f00ad8336372954ee0a9465d9b8 Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/25563 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-04-05mb/google/poppy/variants/nami: Add SPD file for Vaynechriszhou
Add SPD file for sdp hynix_dimm_H5AN8G6NAFR-UHC (ram id: 6). BUG=b:77290144 TEST=Verified that the device with this memory part boots to OS fine. Change-Id: I33503de21c9fc14537c00c092986fd4d2998dace Signed-off-by: chriszhou <chris_zhou@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/25461 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Shelley Chen <shchen@google.com>
2018-03-28soc/intel/skylake: Limit xDCI feature when VBOOT is enabledDuncan Laurie
Use the common xDCI function to check if the controller is allowed in the current mode before enabling it. Otherwise, disable the PCI device if it has been enabled in devicetree. To make the SOC behavior consistent the XdciEnable config option is removed in favor of direct control by devicetree.cb and the mainboards that had defined it were adjusted accordingly. This was tested on an Eve board with xDCI enabled in devicetree.cb to ensure the xDCI device is enabled in developer mode and disabled in normal mode. Change-Id: Ic3c84beac87452f17490de32082030880834501d Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/25365 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-03-28mb/google/poppy/variants/nami: Add SPD file for sona.Van Chen
Add SPD file for sdp samsung_dimm_K4A8G165WC-BCTD (ram id: 8). BUG=b:76086834 TEST=Verified that the device with this memory part boots to OS fine. Change-Id: I49fa114f07ad2eef10f18de9f6c3380173681bdd Signed-off-by: Van Chen <van_chen@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/25379 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-03-21mb/google/poppy/variants/nami: change type of board_sku_id() to uint32_tZhuohao Lee
Tools/scripts, like mosys/arc-setup, use int (4 bytes) to read the sku id. In order to support "-1", we need to use uint32_t (4 bytes) instead of using uint16_t (2 bytes) data type. Otherwise, tools/scripts will read 65535 instead of -1. Another reason to change this is that sku_id can be supported by ec up to 4 bytes. BUG=b:73792190 TEST=mosys output "Platform not supported" for -1 sku id arc-setup read -1 sku id Change-Id: Ib3baa8419f138abeb412ac09c2e7dc608e3b758b Signed-off-by: Zhuohao Lee <zhuohao@chromium.org> Reviewed-on: https://review.coreboot.org/25252 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-03-19mb/google/poppy: Config GPIO for DMIC by different sku idamanda_hwang
BUG=b:74177699 BRANCH=poppy TEST=Verify audio recorder function by different SKU ID Change-Id: Ic6570703f6ab4a1b03cbba8370fc0f597ab6bcf2 Signed-off-by: amanda_hwang <amanda_hwang@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/25148 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-03-15mb/google/poppy/variants/nami: Add gpio-keys ACPI node for PENHShelley Chen
Use gpio_keys driver to add ACPI node for pen eject event. Also setting gpio wake pin for wake events. BUG=b:73121017 BRANCH=None TEST=./util/abuild/abuild -p none -t google/poppy -x -a Change-Id: I5d87d938ac3a4e52e676850b9d8b80e83726275d Signed-off-by: Shelley Chen <shchen@chromium.org> Reviewed-on: https://review.coreboot.org/25162 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-03-15mb/google/poppy/variants/nami: Use GPP_B4 as Touchscreen Power EnableShelley Chen
Touchscreen power enable for Nami has moved from GBB_C22 to GPP_B4 in the latest schematics. BUG=b:74347464 BRANCH=None TEST=./util/abuild/abuild -p none -t google/poppy -x -a Change-Id: I3b1794d44f25c0d42d082d63b9e3ec3dfcef7528 Signed-off-by: Shelley Chen <shchen@chromium.org> Reviewed-on: https://review.coreboot.org/25154 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-03-13mb/google/poppy/variants/nami: Use internal pulldown for MEM_CONFIG_4Furquan Shaikh
Since nami proto did not have any external pull on MEM_CONFIG_4, use a weak internal pull down before reading it. BUG=b:74420123 TEST=Verified that the value read for MEM_CONFIG_4 is correct on nami. Change-Id: I45989d2ca35b863f391baba9e2f2e602033217d4 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/25103 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-03-09mb/google/poppy/variants/nami: Fix typo in nami MakefileFurquan Shaikh
Change SECONDARY_SPD_SOURCES to SEC_SPD_SOURCES as that is what the spd target expects. TEST=Verified that sec-spd.bin is present in coreboot.rom Change-Id: I4299df1eb9009095ef899c5b83823750dfc715d8 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/25083 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-03-08mb/google/poppy/variants/nami: Define smbios_mainboard_sku to return SKU IDsShelley Chen
Return proper SKU IDs so that mosys can return the proper variant. BUG=b:74059798 BRANCH=None TEST=./util/abuild/abuild -p none -t google/poppy -x -a Change-Id: I665fa491de6e277fea5cc071b1f04a21317bccba Signed-off-by: Shelley Chen <shchen@chromium.org> Reviewed-on: https://review.coreboot.org/25028 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-03-08mb/google/poppy : Get SKU_ID from EC for Nami/Vayneamanda_hwang
CBI abbreviates Cros Board Info. BUG=b:74177699 BRANCH=master TEST=Verify CPU log shows expected SKU ID on Nami. Change-Id: I42dd177de8c49cf3c122c2ebb1fcf42e5ba4cd75 Signed-off-by: amanda_hwang <amanda_hwang@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/24996 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-03-08mb/google/poppy/variants/nami: Add WACOM EMR supportjasper lee
Add WACOM EMR in devicetree I2C #2. BUG=b:72062737 BRANCH=master TEST=Verify EMR on nami Change-Id: Icbe809a48959e5749262aeb1b89b09c4bdafbbc2 Signed-off-by: jasper lee <jasper_lee@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/24997 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-03-07mb/google/poppy/variants/nami: Add SPD files for namijasper lee
This change adds SPD files for memory IDs 7 on nami. BUG=b:73807138 Change-Id: I25fe3b347057eea75c58bfb88df41bdb28cc1460 Signed-off-by: jasper lee <jasper_lee@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/25007 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-03-07mb/google/poppy/variants/nami: Add memory detection logicShelley Chen
Alkali will use LPDDR3, so need to have Nami support both DDR4 and LPDDR3. We do this with the PCH_MEM_CONFIG4 GPIO. BUG=b:73514687 BRANCH=None TEST=None Change-Id: Ife6740ce0e8fe109ded7b954134171ba91895628 Signed-off-by: Shelley Chen <shchen@chromium.org> Reviewed-on: https://review.coreboot.org/25000 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-03-07mb/google/poppy/variants/nami: Add spd filesShelley Chen
Add spd files for LPDDR3 based on info received from factory team. BUG=b:73287172 BRANCH=None TEST=None Change-Id: I8924ce97ea422ef1e9a5becb5ea2fda3bf77d8cf Signed-off-by: Shelley Chen <shchen@chromium.org> Reviewed-on: https://review.coreboot.org/25001 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-03-05mb/google/poppy/variants: Set pch_trip_temp to 75CFurquan Shaikh
Similar to Soraka, this change sets the pch_trip_temp value to 75C. This is important so that PMC can shutdown the thermal sensor when CPU is in C-state and DTS temp <= pch_trip_temp. BUG=b:74089135 Change-Id: Ic46fa0681796b821dfb014ab91734c960df7846a Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/24968 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-02-28mb/google/poppy/variants/nami: Enable elan touchscreenCrystal Lin
BUG=b:72062694 BRANCH=master TEST=Verify touchscreen on nami works with this change. Change-Id: Iaec71a11121b3d2849f12d18cda0e506be2ace09 Signed-off-by: Crystal Lin <crystal_lin@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/23872 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-02-20mb/google/poopy/variants/nami: Add Pmax settingGaggery Tsai
This patch adds the Pmax setting in device tree. The Pmax is from MAX(PL4_sku1, PL4_sku2, ..) + ROPmax. Given ROPmax is 30W and the maximum PL4 is from U42, hence the Pmax = 71W + 30W = 101W. BUG=b:72138778 BRANCH=None TEST=USE=fw_debug emerge-nami chromeos-mrc coreboot chromeos-bootimage & ensure the Pmax value is passed to FSP-S. Change-Id: Ief6a134dc5b6bd2b8e07b4a44450e99ff26402d9 Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com> Reviewed-on: https://review.coreboot.org/23640 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-02-10mb/google/poppy/variants/nami: set oem_id, oem_table_id fields of acpi_header_tKaiyen Chang
This change makes Nami platform update the two fields: *oem_id* and *oem_table_id*, if the Maxim codec is detected. Change is made to correct the audio topology file name that is being read from oem_id fields, loaded and displayed in dmesg. BUG=b:70646770 TEST=Verify kernel reads new strings. Change-Id: I513a997f312e2d37d76da0379feb017d1f591f9a Signed-off-by: Kaiyen Chang <kaiyen.chang@intel.com> Reviewed-on: https://review.coreboot.org/23670 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-02-08mb/google/poppy/variants/nami: Revise AC/DC loadlinesGaggery Tsai
This patch revises AC/DC loadlines from VRTT reports. +----------------+-------+-------+-------+-------+ | Domain/Setting | SA | IA | GTUS | GTS | +----------------+-------+-------+-------+-------+ | AcLoadline | 11 | 2.4 | 3.1 | 3.1 | | DcLoadline | 10 | 2.46 | 3.1 | 3.1 | +----------------+-------+-------+-------+-------+ BUG=b:72351128 b:72129954 BRANCH=None TEST=emerge-nami coreboot chromeos-bootimage & ensure the settings are passed to FSP. Change-Id: Ib8aeb82973c42723d7b623967f8085c8f1d926eb Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com> Reviewed-on: https://review.coreboot.org/23635 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-02-07mb/google/poppy/variants/nami: Change WiFi wake pin to GPP_E22Furquan Shaikh
This change updates the WiFi device wake pin to GPP_E22 from WAKE# (to match the latest schematic changes). Since WiFi was the only device using WAKE# pin, DSX_EN_WAKE_PIN is removed from deep_sx_config as well. BUG=b:72697650 TEST=Verified: 1. Wake-on-wifi works. 2. Device is able to enter G3 without WAKE# pin causing unwanted wakes from deep S5. Change-Id: Ibde81f73cca322f9b8b45baf8ee18ae00521467d Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/23594 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-01-25mb/google/poppy/variants/nami: Disable SATAKane Chen
This change disables SATA controller in order to make SATA IP enter low power status. BUG=b:72332817 TEST=cat /sys/kernel/debug/pmc_core/pch_ip_power_gating_status and verify SATA IP enters low power state Change-Id: I72a98bc3d0b47aebc0d7be534f4a7503084b257f Signed-off-by: Kane Chen <kane.chen@intel.com> Reviewed-on: https://review.coreboot.org/23354 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-01-25mb/google/poppy/variants/nami: Enable elan touchpad wakeup system from S3/S0ixVan Chen
BUG=b:71839089 TEST= 1. emerge-nami coreboot chromeos-bootimage 2. powerd_dbus_suspend 3. touch touchpad to wakeup system 4. localhost ~ # cat /var/log/eventlog.txt | 2018-01-21 17:01:59 | S0ix Enter | 2018-01-21 17:02:04 | S0ix Exit | 2018-01-21 17:02:04 | Wake Source | GPIO | 80 Change-Id: Ie550cfa3f7b5fd105f89c16076d428743392d0e4 Signed-off-by: Van Chen <van_chen@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/23363 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-01-23mb/google/poppy/variants/nami: Remove iccmax setting from devicetreeFurquan Shaikh
Change e1a75d4(soc/intel/skylake: Override KBL IccMax settings) provides correct iccmax settings for kbl-u based on the SKU. Thus, there is no need to override these values in devicetree. This change gets rid of iccmax settings in the nami devicetree. Change-Id: Ie7220bae71fcc597fc20c5e98793d4ea7af5650e Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/23265 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-01-15mb/google/poppy/variants/nami: Enable elan touchpadvan_chen
BUG=b:71838954 TEST= 1. emerge-nami coreboot chromeos-bootimage 2. check touchpad function 3. evtest /dev/input/event5: Elan Touchpad Change-Id: I14471d1473a3b3ecf15aaf362b47874704cd3bf0 Signed-off-by: van_chen <van_chen@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/23133 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-01-12mb/google/poppy/variants/nami: Fix DA7219 IRQ issueKaiyen Chang
Change PAD_CFG_GPI_GPIO_DRIVE to PAD_CFG_GPI_APIC for GPIO D9 to meet the requirement of DA7219 IRQ pin. BUG=b:70646770 BRANCH=none TEST=Use aplay and arecord to verify headphone function. Change-Id: Id6cff8325c4c7f02f6f4df547fde286e2ef83d5c Signed-off-by: Kaiyen Chang <kaiyen.chang@intel.com> Reviewed-on: https://review.coreboot.org/23160 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-01-02mb/google/poppy/variants/nami: Add empty_ddr4.spd.hex for DDR4Kane Chen
The spd size of DDR4 is 512, but the size empty.spd.hex is 256. With empty.spd.hex and DDR4, it will cause mainboard_get_spd_data loads spd data incorrectly due to the offset is wrong. Change-Id: Iea3f216898525a2a602fabf1835c8a0c1245ee57 Signed-off-by: Kane Chen <kane.chen@intel.com> Reviewed-on: https://review.coreboot.org/23038 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-12-22soc/intel/skylake: Add PcieRpClkSrcNumber UPD configuartion supportDivya Chellap
New UPD PcieRpClkSrcNumber introduced in FSP V2.9.2 to configure clock source number of PCIe root ports. This UPD array is set to clock source number(0-6) for all the enabled PCIe root ports, invalid(0x1F) is set for disabled PCIe root ports. BUG=b:70252901 BRANCH=None TEST= Perform the following 1. Build and boot soraka 2. Verify PCIe devices list using lspci command 3. Perform Basic Assurance Test(BAT) on soraka Change-Id: I95ca0d893338100b7e4d7d0b76c076ed7e2b040e Signed-off-by: Divya Chellap <divya.chellappa@intel.com> Reviewed-on: https://review.coreboot.org/22947 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-12-20mb/google/poppy/variants/nami: Add SPD files for namiFurquan Shaikh
This change adds SPD files for memory IDs 1-4 on nami. BUG=b:70182907 Change-Id: Ic43f944c0cde18244fe4c4d21314b831d048a3a2 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/22942 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Gaggery Tsai <gaggery.tsai@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-12-20mb/google/poppy: Enable speaker and codec for namiGaggery Tsai
Nami uses MAX98357A speaker amplifier and DA7219 codec. This patch adds max98357a and da7219 under I2C #3 in devicetree and adds SPK DMIC nhlt support for 4CH DMIC. BUG=b:70646770 TEST=emerge-nami coreboot Change-Id: Iecf4059f8ea3d5e34f33f0be227897a8cca636fa Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com> Reviewed-on: https://review.coreboot.org/22861 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-12-19mb/google/poppy/variants/nami: Fix SATA configs againFurquan Shaikh
This change really fixes the SataMode to select non-RAID mode and enables SATA which was incorrectly disabled in a71276b (mb/google/poppy/variants/nami: Fix SataMode configuration in devicetree). BUG=b:70160119 Change-Id: Ied6adabdc1d2458972bde628616a198cd41f9f3e Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/22918 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-12-19mb/google/poppy: Configure GPP_F3 as NCFurquan Shaikh
GPP_F3 is not connected on poppy or any of its variants. This change configures GPP_F3 as NC on poppy and all the variants. BUG=b:70160119 Change-Id: I303276ab9546d56c846755fa3a6142978f6b8c92 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/22917 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-12-19mb/google/poppy/variants/nami: Fix GPIO configuration for DEVSLPFurquan Shaikh
Nami uses DEVSLP1 and not DEVSLP0. This change updates the GPIO configuration for DEVSLP to match the latest version of schematics. BUG=b:70160119 Change-Id: Ifa181322011a4b8947ecd0fa44dcf790b0d8f657 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/22916 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-12-17mb/google/poppy/variants/nami: Fix SataMode configuration in devicetreeFurquan Shaikh
Similar to Fizz, SataMode on nami should be set to AHCI. This change fixes the configuration error done in 903472c (mb/google/poppy/variants/nami: Add support for nami board). BUG=b:70160119 Change-Id: Ia88b56ae6bd9121f8447f7c1a2f5a10990fb8ed5 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/22845 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-12-17mb/google/poppy/variants/nami: Fix GPIO config for PCH_SPK_ENFurquan Shaikh
PCH_SPK_EN uses GPP_A23 and not GPP_A22. This change fixes the gpio configuration error in the initial change 903472c (mb/google/poppy/variants/nami: Add support for nami board). BUG=b:70160119 Change-Id: I90d9c009369c53cfec47fe77356e181d5ecf7ad5 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/22844 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-12-12mb/google/poppy/variants/nami: Implement variant_memory_paramsFurquan Shaikh
This change provides implementation of variant_memory_params for nami. Since it uses DDR4 memory, DQ-DQS mapping table is not required. Also, Rcomp resistor values are provided based on SDP v/s DDP memory. BUG=b:70188937 Change-Id: Ic1d0cfdb7d8b02fa0be0a4c54b20057a4c2fc3ce Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/22779 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-12-07mb/google/poppy/variants/nami: Add support for nami boardFurquan Shaikh
This change adds variant nami derived from baseboard poppy. BUG=b:70160119 Change-Id: Ic6795d49d3e6e98a32f4af0b621e8bb463041412 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/22703 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
generated by cgit v1.2.3 (git 2.39.1) at 2024-09-19 13:41:21 +0000