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path: root/src/mainboard/google/poppy/variants/baseboard/gpio.c
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2020-10-21soc/intel,mb/*: get rid of legacy pad macrosMichael Niewöhner
Get rid of legacy pad macros by replacing them with their newer equivalents. TEST: TIMELESS-built board images match Change-Id: I078f9bb3c78f642afc6dcfd64d77be823a4485c2 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46567 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-05-11treewide: Remove "this file is part of" linesPatrick Georgi
Stefan thinks they don't add value. Command used: sed -i -e '/file is part of /d' $(git grep "file is part of " |egrep ":( */\*.*\*/\$|#|;#|-- | *\* )" | cut -d: -f1 |grep -v crossgcc |grep -v gcov | grep -v /elf.h |grep -v nvramtool) The exceptions are for: - crossgcc (patch file) - gcov (imported from gcc) - elf.h (imported from GNU's libc) - nvramtool (more complicated header) The removed lines are: - fmt.Fprintln(f, "/* This file is part of the coreboot project. */") -# This file is part of a set of unofficial pre-commit hooks available -/* This file is part of coreboot */ -# This file is part of msrtool. -/* This file is part of msrtool. */ - * This file is part of ncurses, designed to be appended after curses.h.in -/* This file is part of pgtblgen. */ - * This file is part of the coreboot project. - /* This file is part of the coreboot project. */ -# This file is part of the coreboot project. -# This file is part of the coreboot project. -## This file is part of the coreboot project. --- This file is part of the coreboot project. -/* This file is part of the coreboot project */ -/* This file is part of the coreboot project. */ -;## This file is part of the coreboot project. -# This file is part of the coreboot project. It originated in the - * This file is part of the coreinfo project. -## This file is part of the coreinfo project. - * This file is part of the depthcharge project. -/* This file is part of the depthcharge project. */ -/* This file is part of the ectool project. */ - * This file is part of the GNU C Library. - * This file is part of the libpayload project. -## This file is part of the libpayload project. -/* This file is part of the Linux kernel. */ -## This file is part of the superiotool project. -/* This file is part of the superiotool project */ -/* This file is part of uio_usbdebug */ Change-Id: I82d872b3b337388c93d5f5bf704e9ee9e53ab3a9 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41194 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-06mb/google/poppy: Use SPDX for GPL-2.0-only filesAngel Pons
Done with sed and God Lines. Only done for C-like code for now. Change-Id: Idfc7a5713e231c4756b5faca8984c6598fe1e65a Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40190 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-18mainboard/google: Remove copyright noticesPatrick Georgi
They're listed in AUTHORS and often incorrect anyway, for example: - What's a "Copyright $year-present"? - Which incarnation of Google (Inc, LLC, ...) is the current copyright holder? - People sometimes have their editor auto-add themselves to files even though they only deleted stuff - Or they let the editor automatically update the copyright year, because why not? - Who is the copyright holder "The coreboot project Authors"? - Or "Generated Code"? Sidestep all these issues by simply not putting these notices in individual files, let's list all copyright holders in AUTHORS instead and use the git history to deal with the rest. Change-Id: I09cc279b1f75952bb397de2c3f2b299255163685 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39607 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2018-10-08Move compiler.h to commonlibNico Huber
Its spreading copies got out of sync. And as it is not a standard header but used in commonlib code, it belongs into commonlib. While we are at it, always include it via GCC's `-include` switch. Some Windows and BSD quirk handling went into the util copies. We always guard from redefinitions now to prevent further issues. Change-Id: I850414e6db1d799dce71ff2dc044e6a000ad2552 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/28927 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-08-07mb/google/poppy: Add variant callback for romstage GPIO configurationFurquan Shaikh
This change adds variant callback to get GPIO configuration table in romstage and configures these GPIOs before memory training is performed. BUG=b:111860510 BRANCH=poppy Change-Id: I1eb51356fb3f4c0f4ff29b22dbcde6dbece303ad Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/27863 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-04-24compiler.h: add __weak macroAaron Durbin
Instead of writing out '__attribute__((weak))' use a shorter form. Change-Id: If418a1d55052780077febd2d8f2089021f414b91 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/25767 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Justin TerAvest <teravest@chromium.org>
2018-03-19mb/google/poppy: Config GPIO for DMIC by different sku idamanda_hwang
BUG=b:74177699 BRANCH=poppy TEST=Verify audio recorder function by different SKU ID Change-Id: Ic6570703f6ab4a1b03cbba8370fc0f597ab6bcf2 Signed-off-by: amanda_hwang <amanda_hwang@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/25148 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-03-14mb/google/poppy/variants/baseboard: Add gpio-keys ACPI node for PENHNicolas Boichat
This change uses gpio_keys driver to add ACPI node for pen eject event. BUG=b:74413116 TEST=Verified using evtest that pen eject event results in events as expected. Change-Id: I6019d633f4337137bb9fbba770040cb5b30da773 Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://review.coreboot.org/25147 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-01-12mb/google/poppy: Remove digitizer reset control from ACPIFurquan Shaikh
Digitizer power is not controlled by SoC. Also, since the digitizer uses I2C-HID driver in Linux kernel, the device is put into sleep anytime system is suspended. Thus, there is no need to control the reset gpio using ACPI power resource. TEST=Verified that digitizer device is properly detected on boot-up and after suspend/resume. Change-Id: Id11b8412d0ac48b2701d53b0a22ad3b747b544ec Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/23212 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-01-09mb/google/poppy: Add internal pull-up on pen eject signalFurquan Shaikh
Since the current hardware revision does not have external pull on the pen eject signal, this change adds internal pull-up on it. Change-Id: I426d9833d7efbd8735b6f2b4896d1012b62cb4b8 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/23143 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Tony Lin <tonycwlin@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-12-19mb/google/poppy: Configure WWAN gpiosFurquan Shaikh
BUG=b:70773281 Change-Id: If9b575568cabcbee03ad190b69d9c033890f7fa6 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/22927 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-12-19mb/google/poppy: Configure GPP_B0 for WLAN wakeFurquan Shaikh
As per the latest schematics, this change configures GPP_B0 for WLAN wake and uses corresponding gpe bit in ACPI node for WLAN. This hasn't been tested yet. BUG=b:70775494 Change-Id: I5198b8083a87d00f890b45986e5e3f62b81686c2 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/22928 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-12-19mb/google/poppy: Configure pen reset and eject linesFurquan Shaikh
This change configures the GPIOs for pen reset and eject lines and exports required properties using ACPI table. BUG=b:70773138 Change-Id: I52f6c3dced54259cde8ee6753275622622e15954 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/22926 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-12-19mb/google/poppy: Configure GPP_B8 for WLAN_PE_RSTFurquan Shaikh
BUG=b:62726961 Change-Id: I5a88e67d5a22f8a39427c95821ffee4f2fd717fa Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/22920 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-12-19mb/google/poppy: Configure GPP_F3 as NCFurquan Shaikh
GPP_F3 is not connected on poppy or any of its variants. This change configures GPP_F3 as NC on poppy and all the variants. BUG=b:70160119 Change-Id: I303276ab9546d56c846755fa3a6142978f6b8c92 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/22917 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-12-06mb/google/poppy: Disable SPI TPMFurquan Shaikh
Mainboard poppy is no longer using SPI TPM. This change disables GSPI0 in device tree and udpates gpio configuration accordingly. Change-Id: I713e41c45e323bf13aa79412ec679c90121a52b2 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/22698 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-09skylake mainboards: Use PAD_CFG_GPI_GPIO_DRIVER instead of PAD_CFG_GPIFurquan Shaikh
Change 1760cd3e (soc/intel/skylake: Use common/block/gpio) updated all skylake boards to use common gpio driver. Common gpio code defines PAD_CFG_GPI without GPIO_DRIVER ownership. However, for skylake PAD_CFG_GPI set GPIO_DRIVER ownership by default. This resulted in Linux kernel failing to configure all GPIO IRQs since the ownership was not set correctly. (Observed error in dmesg: "genirq: Setting trigger mode 3 for irq 201 failed (intel_gpio_irq_type+0x0/0x110)") This change fixes the above issue by replacing all uses of PAD_CFG_GPI in skylake mainboards to PAD_CFG_GPI_GPIO_DRIVER. BUG=b:67507004 TEST=Verified on soraka that the genirq error is no longer observed in dmesg. Also, cat /proc/interrupts has the interrupts configured correctly. Change-Id: I7dab302f372e56864432100a56462b92d43060ee Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/21912 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-05mb/google/soraka: Camera PMIC run time power controlNaresh G Solanki
Currently PMIC (tps68470) is in active state even when cameras are not in use. PMIC is put into SLEEP mode only when entering S3 via smihandler. With this change PMIC will be put into SLEEP mode as soon as sensors & VCM voltage outputs are turned off. This will allow run time power saving when camera is not in use. PMIC will be reset in first boot & across S3 & S0ix cycles. Also, remove the smi handler for PMIC power management & handle it as part of sensor and VCM ACPI PowerResource. BUG=b:63903239 TEST= Build for Soraka. Check Camera probe, Capture image across S3 & S0ix cycles. Also checked the following & found no regression: 1. Typical camera use cases 2. Stability tests related to camera 3. Reliability tests related to camera 4. PnP tests related to camera 5. Latency related tests with camera Change-Id: I23b0c0a887c9eb5d29b89f14aebba273b01228e0 Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com> Reviewed-on: https://review.coreboot.org/20741 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rajmohan Mani <rajmohan.mani@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-06-14mainboard/google/{poppy,soraka}: Disable unused GSPI1 interfaceFurquan Shaikh
TEST=Verified that board still boots to OS without any error. Change-Id: I02d2a6cbcab92766a35993bfd20aaeed4ca22c90 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/20143 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-06-07mainboard/google/poppy: Add support for ELAN deviceFurquan Shaikh
Add support for ELAN 5515 device. BUG=b:62331218 Change-Id: Id91a41743330c9e356293cfda7b2e3743dcd480c Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/20040 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-05-26mainboard/google/poppy: Add PowerResource for touchscreen deviceFurquan Shaikh
1. Do not enable touchscreen device by default in gpio configuration. 2. Select use of PowerResource for touchscreen device in devicetree so that the ACPI subsystem can take care of powering on/off the device. When system enters suspend, touchscreen device is powered off and on resume, it is powered back on. BUG=b:62028489 TEST=Verified 100 cycles of suspend-resume. Touchscreen still works on poppy. Change-Id: Ia0bebc7259b10cc60a9fa5b53542dfdd9685663e Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/19829 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-05-03mainboard/google/poppy: Add support for cr50 I2C TPMFurquan Shaikh
1. Add support for using cr50 I2C TPM on poppy. This will not be enabled until the next build. 2. Also, configure GPIOs for SPI and I2C TPM only if the corresponding Kconfig options are set. BUG=b:36265511 TEST=Verified on a reworked board that I2C TPM communication works fine. Change-Id: I3b293b8d410a6973a6dfea393c17d0be425b6a28 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/19518 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-05-03mainboard/google/poppy: Update GPIO table for next buildFurquan Shaikh
Update GPIO table to match the schematics for next build. Change-Id: I949a14bfaa7972f2257a0b11ee81dcb0771e2f7f Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/19517 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2017-04-19mainboard/google/poppy: Provide cros_gpio variant APIFurquan Shaikh
Add support for ChromeOS GPIO ACPI table information by providing weak implementation from the baseboard. BUG=b:37375693 Change-Id: I641afe6bb45f106ddebde081a8ac2c64278ebeb9 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/19324 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-04-19mainboard/google/poppy: Add variant API for board_id and gpioFurquan Shaikh
Provide APIs for board_id() and gpio table functionality. Default weak implementations are provided from the baseboard. BUG=b:37375693 Change-Id: Ic3c946e6cb12b3c8ef3e83a1037ed0fc8cffbded Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/19323 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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