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2024-01-24mb/google/oak to rex: Rename Makefiles from .inc to .mkMartin Roth
The .inc suffix is confusing to various tools as it's not specific to Makefiles. This means that editors don't recognize the files, and don't open them with highlighting and any other specific editor functionality. This issue is also seen in the release notes generation script where Makefiles get renamed before running cloc. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I85cda24aa7dec82d23e8a321dac03ec737f4c503 Reviewed-on: https://review.coreboot.org/c/coreboot/+/80108 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-06mainboard: Add SPDX license headers to MakefilesMartin Roth
To help identify the licenses of the various files contained in the coreboot source, we've added SPDX headers to the top of all of the .c and .h files. This extends that practice to Makefiles. Any file in the coreboot project without a specific license is bound to the license of the overall coreboot project, GPL Version 2. This patch adds the GPL V2 license identifier to the top of all makefiles in the mainboard directory that don't already have an SPDX license line at the top. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: Ic451e68b1ad9ccdf34484dd98bd7fca7e177ef22 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68982 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Tim Crawford <tcrawford@system76.com> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2020-09-06mb: remove duplicated Make code for spd.bin generationMichael Niewöhner
Drop duplicated code for spd.bin generation that is provided globally in lib/Makefile.inc. For all affected boards it has been verified that the output binary functionally matches the original one. The changed execution order of Make instructions influenced the cbfs file order. Hence, the rom images can't be compared directly. Thus, the output files of the two timeless abuild runs have been compared. Further, it was verified that the final files in cbfs stay identical, by comparing the extracted cbfs of each board. The boards (possibly) needing modification could be found with something like this (with false positives, though): find src/mainboard -name Makefile.inc | \ xargs egrep 'SPD_BIN|SPD_DEPS' | cut -d: -f1 | sort -u Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Change-Id: Icd3ac0fd6c901228554115c6350d88bb49874587 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44774 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-09-02mb/google/poppy/var/rammus: Update SPD table for RammusKane Chen
1. Add new SPD file, "samsung_dimm_K4E8E324ED-EGCG.spd.hex". 2. Add SPD support in Rammus memory table, as follows: SPD_SOURCES += samsung_dimm_K4E8E324ED-EGCG # 0b0110 SPD_SOURCES += samsung_dimm_K4E6E304ED-EGCG # 0b0111 BUG=b:166576463 BRANCH=firmware-rammus-11275.B TEST=emerge-rammus coreboot chromeos-ec chromeos-bootimage Flash FW to DUT, and make sure system boots up. Signed-off-by: Kane Chen <kane_chen@pegatron.corp-partner.google.com> Change-Id: I82386507c4e996e0a59c26ce50de3bced45b1196 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44854 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Zhuohao Lee <zhuohao@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-09mb/[google/intel/lenovo]/*: fix posix shell bug with SPD filesGreg V
FreeBSD's sh (basic posix shell) did not interpret the '\%o' escape in the same way bash/zsh do. As a result, the decoded files ended up with ASCII numbers instead of the decoded binary data. Change-Id: I95b414d959e5cd4479fcf100adcf390562032c68 Signed-off-by: Greg V <greg@unrelenting.technology> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35867 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-05-15mb/google/poppy/variants/rammus: Support new onboard Hynix memoryKane Chen
Add hynix_dimm_H9CCNNNCLGALAR-NVD for new onboard memory support. BUG=b:130337306 BRANCH=firmware-rammus-11275.B TEST=emerge-rammus coreboot chromeos-ec chromeos-bootimage Flash FW to DUT, and make sure system boots up. Signed-off-by: YanRu Chen <kane_chen@pegatron.corp-partner.google.com> Change-Id: Ibd02953d0c6ac62fa4d7751fd8b103b74433aa73 Reviewed-on: https://review.coreboot.org/c/coreboot/+/32674 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-05-14mb/google/poppy/variant/atlas: Add SPDs for Samsung D-die chipsCaveh Jalali
This adds the SPDs for Samsung D-die 16Gbit and 32Gbit LPDDR3-2133 chips. BUG=b:132206809 TEST=boots on atlas with C-die and D-die memory chips localhost ~ # mosys memory spd print all 0 | LPDDR3 | SO-DIMM 1 | LPDDR3 | SO-DIMM 0 | 1-78: Samsung | 00000000 | K4EBE304ED-EGCG 1 | 1-78: Samsung | 00000000 | K4EBE304ED-EGCG 0 | 8192 | 2 | 64 1 | 8192 | 2 | 64 0 | LPDDR3-800, LPDDR3-1066, LPDDR3-1333, LPDDR3-1600, LPDDR3-1866, LPDDR3-2133 1 | LPDDR3-800, LPDDR3-1066, LPDDR3-1333, LPDDR3-1600, LPDDR3-1866, LPDDR3-2133 localhost ~ # Change-Id: I8ba000aeeb77f07d7f18bda86b3c07f5b50478b8 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32780 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-12-21mb/google/poppy/variants/nami: Add micron_dimm_MT40A512M16TB-062EJ SPDFrank Wu
Add SPD file for micron_dimm_MT40A512M16TB-062EJ (ram id: 12) BUG=b:121217853 BRANCH=firmware-nami-10775.B TEST=emerge-nami coreboot chromeos-bootimage Change-Id: I45e6a7a183556fb085f5442cd6bb429d79ef4235 Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/30327 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-12-21mb/google/poppy/variants/nami: Add micron_dimm_MT40A256M16LY-075F SPDIvy Jian
Add SPD file for sdp micron_dimm_MT40A256M16LY-075F (ram id: 11) BUG=b:120884302 BRANCH=firmware-nami-10775.B TEST=emerge-nami coreboot chromeos-bootimage Change-Id: Icf731bfefd550e9b94b6404bc870d4d76451deb1 Signed-off-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/30183 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-12-11mb/google/poppy/variants/nami: Modify SPD for hynix memory partRen Kuo
correct memory part name form hynix_dimm_H5ANAG6NCMR-VKC to hynix_dimm_H5AN4G6NAFR-UHC BUG=b:113983573 BRANCH=Nami TEST=emerge-nami coreboot chromeos-bootimage Change-Id: I0c33343eb1269919fba324333897805da1d1ff9b Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/30076 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>
2018-11-08mb/google/poppy/variants/nami: add the hynix memory partsRen Kuo
add the memory parts as ram id 10: hynix_dimm_H5ANAG6NAFR-UHC BUG=b:113983573 BRANCH=Nami TEST=emerge-nami coreboot chromeos-bootimage Change-Id: I137259b88f39779768a58959a2dcc565645eee6d Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/29524 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-10-10mb/google/poppy/variants/nami: Add samsung_dimm_K4AAG165WB-MCRC SPDChris Zhou
Add SPD file for sdp samsung_dimm_K4AAG165WB-MCRC (ram id: 9) BUG=b:112679174 TEST=emerge-nami coreboot chromeos-bootimage Change-Id: Iac1e3ca4b009cc9be94608cd342f535fa581a5eb Signed-off-by: Chris Zhou <chris_zhou@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/28974 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-12rammus: add SPD mapping for rammus and shyvana supportkane_chen
Add MICRO 4G and 8G SPD file. BUG=none BRANCH=master TEST=emerge-rammus coreboot chromeos-ec chromeos-bootimage Flash FW to DUT, and make sure system boots up. Change-Id: I7cb5b7f2bcdc6fbe0cbc640cad4af014f1a0edd6 Signed-off-by: YanRu Chen <kane_chen@pegatron.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/28484 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-10mb/google/poppy/variants/nami: Add SPD for two memory partsRen Kuo
add two memory parts and ram id: hynix_dimm_H5ANAG6NCMR-VKC micron_dimm_MT40A1G16KNR-075E BUG=b:113983573 BRANCH=Nami TEST=emerge-nami coreboot chromeos-bootimage Change-Id: Ia052f16b6c1e64ee6458fbdeea56a482a728c35a Signed-off-by: Ren Kuo <Ren.Kuo@quantatw.com> Reviewed-on: https://review.coreboot.org/28536 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-29mb/google/poppy: Fix bytes 145-146 in nayna_dimm_NT6CL256T32CM SPDT.H. Lin
nayna/NT6CL256T32CM-H1 file change byte 145/146 to be"20" for JEDEC spec BUG=b:79443146,b:109708239 BRANCH=nami TEST=emerge-nami coreboot chromeos-bootimage Test on R69.10825 with mosys Change-Id: Iadc820111f0aed34e5b46d7e23dff44cb5bb811d Signed-off-by: T.H. Lin <t.h_lin@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/27275 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-21mb/google/poppy/variants/nocturne: add two new memory optionsNick Vaccaro
- add K4E6E304EC-EGCF and K4EBE304EC-EGCF to memory strapping table - add SPD files for K4E6E304EC-EGCF and K4EBE304EC-EGCF BUG=b:110277021 BRANCH=none TEST=none Change-Id: If1322311bd91842d6d32725822d91fd6d9e8077c Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/27123 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Caveh Jalali <caveh@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-05-11mb/google/poppy/variants/atlas: add SPD for new samsung 4GB memoryCaveh Jalali
This adds a new SPD entry for samsung's new 4GB memory and updates atlas to use it instead of the previous gen memory. BUG=b:79444337 TEST=booted on atlas Change-Id: I19567736c45a1321586378c3d964c2cbebe24755 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://review.coreboot.org/26185 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-05-11mb/google/poppy/variants/nami: add 2-channel LPDDR3 memoryT.H. Lin
hynix/H9CCNNNCLGALAR-NUD nayna/NT6CL256T32CM-H1 BUG=b:79443146 BRANCH=Nami TEST=emerge-nami coreboot chromeos-bootimage Change-Id: I3a362080b9e60adecbac14d5cfe193da44bf87c8 Signed-off-by: T.H. Lin <t.h_lin@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/26187 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-04-16mb/google/poppy/variants/nami: Add SPD file for PantheonChris Zhou
Add SPD file for sdp hynix_dimm_H5AN8G6NCJR-VKC (ram id: 15). BUG=b:77893710 TEST=Verified that the device with this memory part boots to OS fine. Change-Id: I434d42ff12e6dae39e5676f36ba6cf00b3a48b06 Signed-off-by: Chris Zhou <chris_zhou@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/25655 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-04-16mb/google/poppy/variants/nami: Add SPD file for PantheonChris Zhou
Add SPD file for sdp micron_dimm_MT40A512M16LY-075E (ram id: 14). BUG=b:77930401 TEST=Verified that the device with this memory part boots to OS fine. Change-Id: Ia44e70948e57c2f19664d874ae005ac39d748f92 Signed-off-by: Chris Zhou <chris_zhou@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/25654 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-04-05mb/google/poppy/variants/nami: Add SPD file for Vaynechriszhou
Add SPD file for sdp hynix_dimm_H5AN8G6NAFR-UHC (ram id: 6). BUG=b:77290144 TEST=Verified that the device with this memory part boots to OS fine. Change-Id: I33503de21c9fc14537c00c092986fd4d2998dace Signed-off-by: chriszhou <chris_zhou@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/25461 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Shelley Chen <shchen@google.com>
2018-03-28mb/google/poppy/variants/nami: Add SPD file for sona.Van Chen
Add SPD file for sdp samsung_dimm_K4A8G165WC-BCTD (ram id: 8). BUG=b:76086834 TEST=Verified that the device with this memory part boots to OS fine. Change-Id: I49fa114f07ad2eef10f18de9f6c3380173681bdd Signed-off-by: Van Chen <van_chen@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/25379 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-03-27mainboard/google/poppy: Add SPD for Hynix H9CCNNNCLGALAR-NUDDuncan Laurie
Add an SPD for this particular Hynix memory type to the poppy board so it can be used by poppy variants. BUG=b:75454415 Change-Id: I2249c7a4f2c83ec2b3266047a74b9bc22dad43be Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/25368 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-03-07mb/google/poppy/variants/nami: Add SPD files for namijasper lee
This change adds SPD files for memory IDs 7 on nami. BUG=b:73807138 Change-Id: I25fe3b347057eea75c58bfb88df41bdb28cc1460 Signed-off-by: jasper lee <jasper_lee@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/25007 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-03-07mb/google/poppy/variants/nami: Add spd filesShelley Chen
Add spd files for LPDDR3 based on info received from factory team. BUG=b:73287172 BRANCH=None TEST=None Change-Id: I8924ce97ea422ef1e9a5becb5ea2fda3bf77d8cf Signed-off-by: Shelley Chen <shchen@chromium.org> Reviewed-on: https://review.coreboot.org/25001 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-03-05mb/google/poppy: Allow use of optional secondary SPDFurquan Shaikh
This change adds support for variants to use secondary SPD if required. This enables a variant to have different types of memory supported using the same image. BUG=b:73514687 Change-Id: I3add65ead99c510f2d6ec899fbf2cb9a06c79b0c Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/24972 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-02-13mb/google/poppy: Fix the SPD for samsung_dimm_K4A8G165WBFurquan Shaikh
Original SPD provided by the vendor had bytes after 254 shifted by 16 bytes. This change fixes the SPD data based on the latest details received from the vendor. BUG=b:72749394 TEST=Verified that the device with this memory part boots to OS fine. Also, mosys is able to dump the right memory information. Change-Id: I6938dea761c5785048aad69eeeaf50e2d0fa8ca1 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/23729 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-01-02mb/google/poppy/variants/nami: Add empty_ddr4.spd.hex for DDR4Kane Chen
The spd size of DDR4 is 512, but the size empty.spd.hex is 256. With empty.spd.hex and DDR4, it will cause mainboard_get_spd_data loads spd data incorrectly due to the offset is wrong. Change-Id: Iea3f216898525a2a602fabf1835c8a0c1245ee57 Signed-off-by: Kane Chen <kane.chen@intel.com> Reviewed-on: https://review.coreboot.org/23038 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-12-20mb/google/poppy/variants/nami: Add SPD files for namiFurquan Shaikh
This change adds SPD files for memory IDs 1-4 on nami. BUG=b:70182907 Change-Id: Ic43f944c0cde18244fe4c4d21314b831d048a3a2 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/22942 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Gaggery Tsai <gaggery.tsai@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-03google/nautilus: add spd data by ram idChris Wang
update with nautilus memory spds. RAM_ID = 0 => K4E8E324EB-EGCF RAM_ID = 1 => K4E6E304EB-EGCF RAM_ID = 2 => K4EBE304EB-EGCG BRANCH=master BUG=b:66462881 TEST=emerge-nautilus coreboot Change-Id: I29d8a76b170aee64bb0125276df0e4709012daba Signed-off-by: Chris Wang <chriswang@ami.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/22175 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: shkim <sh_.kim@samsung.com>
2017-05-24mb/google/poppy: Update SPD dataNaresh G Solanki
Though SPD is rightly selected (i.e., H9CCNNNBKTALBR-NUD), it displays wrong part number during boot in coreboot logs. So correct part number info within the SPD. TEST= Build for Soraka & make sure part number is rightly printed. Change-Id: I67f676fb6ee9d685fa7aa41fdc4b00355e6d33c7 Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com> Reviewed-on: https://review.coreboot.org/19692 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-05-19mainboard/google/poppy/variants/soraka: Add SPD for K3QFAFA0CM-AGCFFurquan Shaikh
BUG=b:37712455 Change-Id: Ia3d13ac7c18be8fa92603b6501a2e5df476adcf0 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/19766 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-05-19mainboard/google/poppy: Fix SPD for micron MT52L256M64D2PP-107Furquan Shaikh
Fix SPD as per the vendor-provided data. BUG=b:37712790 Change-Id: Ib87c316479f4a05e64ca4acb540d7aacfa7338e9 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/19749 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-04-28mainboard/google/soraka: Add support for memory configs 1,2,7 and 8Furquan Shaikh
BUG=b:37712455 Change-Id: I3209aaef774712edab5e9f656ee84bfb6917b1c1 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/19472 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2017-04-28mainboard/google/poppy: Add SPDs for memory config 1 and 2Furquan Shaikh
BUG=b:37712790 Change-Id: I7764b4ec55b0beea82eeb6c379ef38ceeb1fb04e Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/19471 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-04-19mainboard/google/poppy: Provide memory configuration variant APIFurquan Shaikh
Add support for memory configuration by providing weak implementation from the baseboard. All SPD files are present under spd/ directory. SPD_SOURCES must be provided by the variants to ensure that required SPD hex files are included in the SPD binary. BUG=b:37375693 Change-Id: Ic9bcc03d5a35bebd14061680f264ac072b3c0634 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/19325 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-04-19mainboard/google/poppy: Provide baseboard and variant conceptsFurquan Shaikh
In order to be able to share code across different poppy variants, provide the concept of baseboard and variants. New directory layout: variants/baseboard - code variants/baseboard/include/baseboard - headers variants/poppy - code variants/poppy/include/variant - headers New boards would then add themselves under their board name within "variants" directory. This is purely an organizational change. BUG=b:37375693 Change-Id: If6c1c5f479cfffe768abf27495d379744104e2dc Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/19322 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-01-13mainboard/google/poppy: Correct the index for SPD binariesFurquan Shaikh
BUG=chrome-os-partner:60513 BRANCH=None TEST=Picks up correct SPD for index. Change-Id: Iac683ab3b8151747940b0ad7e257da3d9b0ac622 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/18112 Tested-by: build bot (Jenkins) Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-19google/poppy: Add new boardFurquan Shaikh
Add poppy board files using kabylake and FSP 2.0. BUG=chrome-os-partner:60713 BRANCH=None TEST=Compiles successfully Change-Id: Ic9aa5093b319690ae893a21cab98d9b843000e6c Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/17866 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-15 11:34:04 +0000