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path: root/src/mainboard/google/poppy/Kconfig
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2017-06-19mainboard/google/{poppy,soraka}: Remove MIPI camera support from devicetree.cbV Sowmya
Remove MIPI camera related register entries from devicetree.cb. BUG=b:38326541 BRANCH=none TEST=Build and boot poppy and soraka. Change-Id: Ic6a6a98d4c8ed6cba760eae5fd87bc2a3f15d7d2 Signed-off-by: V Sowmya <v.sowmya@intel.com> Reviewed-on: https://review.coreboot.org/19619 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-06-19mb/google/poppy: Add option to disable TPMNaresh G Solanki
Disable TPM when VBOOT_MOCK_SECDATA is enabled. BUG=None BRANCH=None TEST= Build image using USE="mocktpm" emerge-poppy coreboot depthcharge vboot_reference chromeos-bootimage . Verify boot is successful with mock tpm. Change-Id: Iee527ed17cffb7d25d9089e48a194d99ac8c3cd1 Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com> Reviewed-on: https://review.coreboot.org/20158 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-06-14mainboard/google/{poppy,soraka}: Enable generation of SPI TPM ACPI nodeFurquan Shaikh
Now that we dynamically disable TPM interface based on config options, add support for generation of SPI TPM ACPI node if SPI TPM is used. Change-Id: I87d28a42b48ba916c70e45a061c5efd91a8a59bf Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/20142 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2017-06-01mainboard/google/poppy: Enable H1 I2C TPMFurquan Shaikh
Enable H1 I2C TPM in Kconfig and devicetree for poppy. CQ-DEPEND=CL:513513,CL:*381534 BUG=b:36265511 BRANCH=None TEST=Compiles successfully. Change-Id: I4c6c94fa05abf9f5374505ded5956e879ac79726 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/19926 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nicolas Boichat <drinkcat@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-05-17mainboard/google/poppy/variants/soraka: Enable H1 I2C TPMFurquan Shaikh
1. Add a separate devicetree file for soraka variant and add H1 node. 2. Enable H1 TPM for soraka. BUG=b:36265511 Change-Id: Id9947dce9b7f755971f0199f043af8d251d275ab Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/19519 Reviewed-by: Nicolas Boichat <drinkcat@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Rajneesh Bhardwaj <rajneesh.bhardwaj@intel.com>
2017-05-17mainboard/google/poppy: Correct I2C bus number for TPMFurquan Shaikh
TPM is on I2C bus 1. Fix that. BUG=b:36265511 Change-Id: I7fb696ca7281a0c099dd325d794dd4551cf20a53 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/19710 Reviewed-by: Nicolas Boichat <drinkcat@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Naresh Solanki <naresh.solanki@intel.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-05-03mainboard/google/poppy: Add support for cr50 I2C TPMFurquan Shaikh
1. Add support for using cr50 I2C TPM on poppy. This will not be enabled until the next build. 2. Also, configure GPIOs for SPI and I2C TPM only if the corresponding Kconfig options are set. BUG=b:36265511 TEST=Verified on a reworked board that I2C TPM communication works fine. Change-Id: I3b293b8d410a6973a6dfea393c17d0be425b6a28 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/19518 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-04-28mainboard/google/poppy: Enable separate MRC cache for recovery modeFurquan Shaikh
Enable separate MRC cache for recovery mode. This requires change in flash layout to accomodate another region for RECOVERY_MRC_CACHE. BUG=b:37682566 TEST=Verified following scenarios: 1. Boot into recovery does not destroy normal mode MRC cache. 2. Once recovery MRC cache is populated, all future boots in recovery mode re-use data from the cache. 3. Forcing recovery mode to retrain memory causes normal mode to retrain memory as well. Change-Id: I4c748a316436001c5a33754084ab4a74243e21df Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/19457 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-04-24mainboard/google/poppy: use intel common tis_plat_irq_status()Aaron Durbin
Utilize the intel/common code for tis_plat_irq_status() to remove dependencies and code duplication on for bringing up a board requiring tis_plat_irq_status(). Change-Id: I2aaa1d7d3ce171dc1788438ff9990fce533deb6c Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/19371 Tested-by: build bot (Jenkins)
2017-04-24Kconfig: provide MAINBOARD_HAS_TPM_CR50 optionAaron Durbin
The CR50 TPM can do both SPI and I2C communication. However, there's situations where policy needs to be applied for CR50 generically regardless of the I/O transport. Therefore add MAINBOARD_HAS_TPM_CR50 to encompass that. Additionally, once the mainboard has selected CR50 TPM automatically select MAINBOARD_HAS_TPM2 since CR50 TPM is TPM 2.0. Change-Id: I878f9b9dc99cfb0252d6fef7fc020fa3d391fcec Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/19370 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins)
2017-04-19mainboard/google/poppy/variants/soraka: add soraka boardYH Lin
Create Soraka board which derives from Poppy, a KBL reference board. More Soraka specific changes need to be done later on. BRANCH=master BUG=b:36995255 TEST=Build (as initial setup) Change-Id: I8af68d2cf475df56336aa0e3bebe86a54ece1999 Signed-off-by: YH Lin <yueherngl@chromium.org> Reviewed-on: https://review.coreboot.org/19343 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-04-19mainboard/google/poppy: Provide baseboard and variant conceptsFurquan Shaikh
In order to be able to share code across different poppy variants, provide the concept of baseboard and variants. New directory layout: variants/baseboard - code variants/baseboard/include/baseboard - headers variants/poppy - code variants/poppy/include/variant - headers New boards would then add themselves under their board name within "variants" directory. This is purely an organizational change. BUG=b:37375693 Change-Id: If6c1c5f479cfffe768abf27495d379744104e2dc Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/19322 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-04-19mainboard/google/poppy: Prepare sharing directory for variantsFurquan Shaikh
Clean up Kconfig file in order to support variants for poppy. Add BOARD_GOOGLE_BASEBOARD_POPPY that can be set by various poppy variants to use the common baseboard configs. BUG=b:37375693 Change-Id: I399ecc8c3efb3af26e1fcf60fe2c75b24769fc0f Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/19321 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-04-19mb/google/poppy: Add camera supportV Sowmya
Add camera related support * Enable the SA Imaging Unit and CIO2 devices. * Enable TPS68470 PMIC and populate related ACPI objects. * Enable OV cameras and populate related ACPI objects. * Enable Dongwoon AF DAC and populate related ACPI objects. BUG=b:36580624 BRANCH=none TEST=Build and boot poppy. Dump and verify that ACPI tables have the required entries for all the camera devices. Change-Id: Ifbe878bb6b25fc976e935fee16c4d59fadd47fe2 Signed-off-by: Sowmya V <v.sowmya@intel.com> Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/18969 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2017-04-13mainboard/google/poppy: Add support for cr50 SPI TPMFurquan Shaikh
Put all configs required for enabling cr50 SPI TPM on poppy under POPPY_USE_SPI_TPM so that it can be enabled any time for testing SPI TPM on this board. Also, add required callback for irq status and devicetree config for GSPI0. BUG=b:36873582 Change-Id: I67793093c006c1325fc16f669a96126525f83243 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/19238 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-28vboot: Move remaining features out of vendorcode/google/chromeosJulius Werner
This patch attempts to finish the separation between CONFIG_VBOOT and CONFIG_CHROMEOS by moving the remaining options and code (including image generation code for things like FWID and GBB flags, which are intrinsic to vboot itself) from src/vendorcode/google/chromeos to src/vboot. Also taking this opportunity to namespace all VBOOT Kconfig options, and clean up menuconfig visibility for them (i.e. some options were visible even though they were tied to the hardware while others were invisible even though it might make sense to change them). CQ-DEPEND=CL:459088 Change-Id: I3e2e31150ebf5a96b6fe507ebeb53a41ecf88122 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/18984 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-17mainboard/google/poppy: Enable EC SW syncFurquan Shaikh
Now that EC on poppy is stable, it is time to switch on EC SW sync. BUG=b:36178824 BRANCH=None TEST=Verified that EC SW sync is done properly and device boots to OS. Change-Id: I1395ad8af73128a8dd220351f5b5da157659b19e Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/18838 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-02-21mainboard/google/poppy: Enable Maxim MAX98927 codecRizwan Qureshi
Enable Maxim 98927 codec i2c device and add required SSDT parameters. BUG=chrome-os-partner:62051 BRANCH=None TEST=with required driver support in kernel verify audio on poppy on-board speakers. Change-Id: Id731de42d77204d59f32ac4c33a245837d6e2107 Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Signed-off-by: Dylan Reid <dgreid@chromium.org> Reviewed-on: https://review.coreboot.org/18215 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Martin Roth <martinroth@google.com>
2017-02-21mainboard/google/poppy: Generate required nhlt tableRizwan Qureshi
poppy board uses Maxim 98927 speaker codec and Realtek RT5663 for headset. Select the apropriate NHLT blobs to be packaged in CBFS. Also, generate the required ACPI NHLT table for codec and the supported topology in poppy. BUG=chrome-os-partner:62051 BRANCH=None TEST=With the required driver support in kernel verify that the Audio plays on on-board speakers and headset, recording works from on-board mics and headset mics. Change-Id: I98c65038b35fe99a661807de0766e6eac2c80eed Signed-off-by: M Naveen <naveen.m@intel.com> Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com> Reviewed-on: https://review.coreboot.org/18214 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2017-02-20drivers/i2c: Use I2C HID driver for wacom devicesFurquan Shaikh
Wacom I2C driver does the same thing as I2C HID driver, other than defining macros for Wacom HID. Instead of maintaining two separate drivers providing the same functionality, update all wacom devices to use generic I2C HID driver. BUG=None BRANCH=None TEST=Verified that ACPI nodes for wacom devices are unchanged. Change-Id: Ibb3226d1f3934f5c3c5d98b939756775d11b792c Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/18401 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2017-02-20mainboard/{google,intel}: Change config option selectionFurquan Shaikh
Change config option selection from "config xyz default y" to "select xyz" if the config option has no dependencies. BUG=None BRANCH=None TEST=Verified that config option selection remains unchanged. Change-Id: I259ae40623b7f4d5589e2caa0988419ba4fefda4 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/18400 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2017-02-17mainboard/poppy: select SOC_INTEL_KABYLAKERizwan Qureshi
poppy is based on Kabylake SoC hence select the appropriate config. Change-Id: Ie339a3991eeccb8a7dba983a2b5ab5d1c996ce9d Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/18313 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-02-17mainboard/google/poppy: Generate digitizer node in SSDTFurquan Shaikh
Add support for generating digitizer node in SSDT using wacom i2c driver. BUG=None BRANCH=None TEST=Verified that the node shows up in SSDT. Change-Id: If7e1e2463778c2ff7263eff995def149457edcde Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/18373 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-02-14google/poppy: select NO_FADT_8042Jenny TC
Poppy doesn't support 8042 keyboard. Select NO_FADT_8042 to disable 8042 in FADT header. Kernel will not try to access 8042 region if 8042.FADT=0 BUG=chrome-os-partner:61858 TEST=Boot OS and verify FADT 8042 flag Change-Id: I00182eb4b059d4d9f0705d349dc98651e3955f0d Signed-off-by: Jenny TC <jenny.tc@intel.com> Reviewed-on: https://review.coreboot.org/18311 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-01-13mainboard/google/poppy: Disable EC SW syncFurquan Shaikh
BUG=chrome-os-partner:60513 BRANCH=None TEST=Verified that EC SW sync is disabled Change-Id: I399b26aa64084f5d5e91a2e585281dc48fa81c89 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/18114 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-19google/poppy: Add new boardFurquan Shaikh
Add poppy board files using kabylake and FSP 2.0. BUG=chrome-os-partner:60713 BRANCH=None TEST=Compiles successfully Change-Id: Ic9aa5093b319690ae893a21cab98d9b843000e6c Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/17866 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
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