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The name pci_domain was a bit misleading, since the construct is only
PCI specific in a particular (northbridge/cpu) implementation, but not
by concept. As implementations and hardware change, be more generic
about our naming. This will allow us to support non-PCI systems without
adding new keywords.
Change-Id: Ide885a1d5e15d37560c79b936a39252150560e85
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/2376
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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The commits adding support for the Google Parrot Chromebook
commit a7198b34ccf120df2a9e5b9f104812e96916ad08
Author: Stefan Reinauer <reinauer@chromium.org>
Date: Tue Dec 11 16:00:47 2012 -0800
Add support for Google Parrot Chromebook
Reviewed-on: http://review.coreboot.org/2026
and the Google Butterfly Chromebook
commit d7bd4eb003f5b6a13943418ae0ac53248a2e34d2
Author: Stefan Reinauer <reinauer@chromium.org>
Date: Mon Feb 11 11:11:36 2013 -0800
Add support for "Butterfly" Chromebook
Reviewed-on: http://review.coreboot.org/2359
had macros in `fadt.c` which were not aligned correctly and did
not adhere to the coding style which uses just one space after
`#define`. Fix this and use tabs instead of spaces everywhere.
Change-Id: I1422c57a3bdc2faa29d2a6e2064e4d3aeed0f1cb
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/2375
Tested-by: build bot (Jenkins)
Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
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Mainboards using `COREBOOT` as their OEM Table ID in their DSDT
header were copied from the same source and therefore had spaces
instead of a tab to align that comment for that header field. These
are mostly Intel based boards.
Fix that in accordance with the coding style [1].
[1] http://www.coreboot.org/Development_Guidelines#Coding_Style
Change-Id: I299b955930dbd50b9717e8ff141ce8f3fd534e5f
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/2277
Tested-by: build bot (Jenkins)
Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
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This mirrors the naming convention of handlers in
northbridge and southbridge.
Change-Id: I45d97c569991c955f0ae54ce909d8c267e9a5173
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/2058
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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AKA Acer C7 Chromebook
See http://www.google.com/intl/en/chrome/devices/acer-c7-chromebook.html
for more information. Thank you to Sage Electronic Engineering, LLC for
making this possible! http://www.se-eng.com/
Change-Id: Ic4e4d50045a82cbb82e1dea3cd5a04525a648612
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/2026
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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