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path: root/src/mainboard/google/octopus
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2018-05-19mb/google/octopus: enable xdci controllerJagadish Krishnamoorthy
BUG=b:79343083 BRANCH=NONE TEST=On Yorp board, lspci should list xdci, 00:15.1 USB controller Change-Id: I3a4878389a1b5b7abcaccf6ab16b67848aaaee83 Signed-off-by: Jagadish Krishnamoorthy <jagadish.krishnamoorthy@intel.com> Reviewed-on: https://review.coreboot.org/26358 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-05-18mb/google/octopus: Disable BT before S5 entryHannah Williams
The CNVi wifi/bt module prevents entry into S5 by keeping internal SoC clocks running. Therefore it's necessary to disable BT prior to S5 entry. BUG=b:79606769 TEST= Test if BT device works under following cases: 1. Power-on 2. Press powerbtn before OS entry 3. Power-on from S5 again Change-Id: Ibc14b4080a27de48d197e16d0eed162603482de2 Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/26238 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-11mb/google/octopus: Ignore standby state for DMIC pinsShamile Khan
This keeps Audio clock and data pins ON in S0ix to support Wake on Voice. BUG=b:77605180 BRANCH=none TEST=Checked that S0ix suspend/resume works. Validation of WoV was done on glkrvp previously. For Yorp, audio topology firmware updates are required for testing WoV. Change-Id: Idafe4e7d24fe16f8e8ff3dd86e299776ea860d03 Signed-off-by: Shamile Khan <shamile.khan@intel.com> Reviewed-on: https://review.coreboot.org/26202 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-08mb/google: Get rid of device_tElyes HAOUAS
Use of device_t has been abandoned in ramstage. Change-Id: I8e549e4222ae2ed6b9c46f81c5b5253e8b227ee8 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26086 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-05-04mainboard/google: Comment variant names in KconfigMartin Roth
It's very confusing trying to find the google platform names, because they seem all unsorted in Kconfig. They're actually sorted according to the variant name, but previously, that was impossible to tell. - Add a comment to the top of variants in Kconfig.name - Inset each variant name. If you start a prompt with whitespace, it gets ignored, so after trying various ways to indent, the arrow was the option I thought looked the best. It now looks like this: *** Beltino *** -> Mccloud (Acer Chromebox CXI) -> Monroe (LG Chromebase 22CV241 & 22CB25S) -> Panther (ASUS Chromebox CN60) -> Tricky (Dell Chromebox 3010) -> Zako (HP Chromebox G1) Butterfly (HP Pavilion Chromebook 14) Chell (HP Chromebook 13 G1) Cheza *** Cyan *** Change-Id: I35cb16b040651cd1bd0c4aef98494368ef5ca512 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/26020 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-05-02mb/google/octopus: Configure pins to reflect delta w.r.t yorpShamile Khan
Changes in pin usage between yorp and bip - LTE_OFF_ODL pin moved from GPIO_161 to GPIO_66 - I2S0 interface is not used in bip. It was used in yorp for DMIC Wake on Voice through Nuvoton EC. Also fix both bip and yorp pin settings for LTE_OFF_ODL (Enable LTE and add an internal pull up). Internal pull up can be removed later when sub-board (which will have an external pull up for this signal) is available. BUG=b:77869623 BRANCH=none TEST=Build coreboot for octopus. Change-Id: I8907bd63a43c4bc51ca991c3ec7c1cae9e39e2d1 Signed-off-by: Shamile Khan <shamile.khan@intel.com> Reviewed-on: https://review.coreboot.org/25804 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-04-30mb/google/octopus: Create phaser variantJustin TerAvest
This creates a phaser variant for octopus. Nothing is set in the variant files here; everything is picked up from baseboard. BUG=b:78572180 TEST=None Change-Id: Ia03e8af91741f1f7aa3a42ac28688b8b6a708932 Signed-off-by: Justin TerAvest <teravest@chromium.org> Reviewed-on: https://review.coreboot.org/25877 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-04-30mb/google/octopus: save dimm info as SMBIOS Table-17Ravi Sarawadi
Save FSP provided memory HOB info as SMBIOS Table-17 format. Firmware tools such as mosys, dmidecode uses SMBIOS Table-17 to report memory metadata. BUG=b:78651920 TEST=Build for Octopus and check 'dmidecode -t17' and 'mosys memory spd print all' to verify dimm info. Change-Id: I9b032b766a2927725b2378f7f720644d4459f602 Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com> Reviewed-on: https://review.coreboot.org/25881 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-04-30mb/google/octopus: Fix crossystem wpsw_cur errorHannah Williams
With only one entry for Write Protect gpio in the OIPG package, the sysfs entry /sys/devices/platform/chromeos_acpi/GPIO.x is created as "GPIO" instead of "GPIO.x". This was causing crossytem to return error for wpsw_cur. BUG=b:78009842 Change-Id: Ica60f342420d95d09a45580f2f940443c03601de Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/25892 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-04-28mb/google/octopus: Enable pull on ESPI_IO1 lineFurquan Shaikh
This change configures a weak internal pull-up on ESPI_IO1 line for octopus baseboard and variant bip. ESPI_IO1 is used as ALERT# line and is expected to be open-drain. However, there is no external pull on this line and so an internal pull-up is required to ensure proper eSPI communication. BUG=b:78497502 TEST=Verified that there is no eSPI communication failure between AP and EC during boot-up and on suspend/resume. Change-Id: Ic494aa7397b94bfd233ce10da8287660997b3377 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/25900 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Hannah Williams <hannah.williams@intel.com>
2018-04-26mb/google/octopus: Add dptf.asl in dsdt.aslSumeet Pawnikar
This patch enables dptf for Octopus by adding dptf.asl in dsdt.asl. BUG=b:74263914 BRANCH=None TEST=None Change-Id: I7194cdd2af88ff062ebcc92cc97b3cdc3d21ecd6 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/25809 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Justin TerAvest <teravest@chromium.org>
2018-04-25mb/google/octopus: Disable PCIE NPK deviceShaunak Saha
This patch sets the NPK device off for octopus. BUG=b:76115112 TEST=Build for Octopus and check that the logs do not report "PCI: 00:00.2 not found, disabling it". Change-Id: I3ac01f90cf946b019a6604a38dd1d6782f8d5759 Signed-off-by: Shaunak Saha <shaunak.saha@intel.com> Reviewed-on: https://review.coreboot.org/25801 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-24compiler.h: add __weak macroAaron Durbin
Instead of writing out '__attribute__((weak))' use a shorter form. Change-Id: If418a1d55052780077febd2d8f2089021f414b91 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/25767 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Justin TerAvest <teravest@chromium.org>
2018-04-21mb/google/bip: Add GPIO configuration settingsShamile Khan
These settings are identical to yorp settings except overrides are not provided for sleep_gpio[] table which is currently empty for yorp and cros_gpios[] table which is not expected to change for bip. BUG=b:77869623 BRANCH=none TEST=Build coreboot for bip. Change-Id: Icc205f576691427d78c9159dfdbced87e41a0517 Signed-off-by: Shamile Khan <shamile.khan@intel.com> Reviewed-on: https://review.coreboot.org/25741 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-04-19mb/google/octopus: Select DRIVERS_I2C_HIDFurquan Shaikh
This change selects DRIVERS_I2C_HID which is required for adding SSDT node for digitizer. BUG=b:78099046 Change-Id: I526c0ac7b88dec7b2b22d022d911840555f15cde Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/25710 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Justin TerAvest <teravest@chromium.org>
2018-04-17mb/google/octopus: Enable Yorp EC software syncJustin TerAvest
With one additional EC change, Yorp is able to flash the EC as part of software sync and successfully boot. This change is only made for Yorp as we want this disabled for Bip bringup. BRANCH=none BUG=b:77874283 TEST=Successful flash and boot on Yorp with this change TEST=Checked GBB flags on Yorp and Bip images with gbb_utility CQ-DEPEND=CL:1014397 Change-Id: I4969b254c6a58fba9dd8d2f31feb25b55c7a0c65 Signed-off-by: Justin TerAvest <teravest@chromium.org> Reviewed-on: https://review.coreboot.org/25692 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-16mb/google/octopus: Add Write Protect GPIO to cros_gpiosHannah Williams
This will enable crossystem to access WP GPIO BUG=b:78009842 TEST= wpsw_cur in crossystem reads the correct gpio Change-Id: Iedd0057d6bdfd5a666ff282bc784f7b98e8c96e8 Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/25673 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-04-12mb/google/octopus: Configure SMI for ESPIShaunak Saha
This patch enables EC SMI when ESPI is enabled. BUG=b:77857802 TEST= SMI is working in depthcharge. Change-Id: I52726194b8346488e5ad781e78e33c5d286d132f Signed-off-by: Shaunak Saha <shaunak.saha@intel.com> Reviewed-on: https://review.coreboot.org/25569 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-11mb/google/octopus: enable MRC recovery cacheAaron Durbin
Enable the recovery cache to speed up recovery flows. Also enable clearing of the normal mrc cache on recovery forced retrains. BUG=b:77871444 TEST=went into recovery twice. 2nd time it boots faster. Change-Id: Idfce42ac835637fa521545fadfedecd65df91d4c Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/25613 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-04-11mb/google/octopus: Select DRIVERS_SPI_ACPIFurquan Shaikh
This change selects DRIVERS_SPI_ACPI which is required to add SSDT node for SPI TPM. BUG=b:75306520 BRANCH=None TEST=None Change-Id: I0728062dae017522ba91a4b5cb16acf9f6bf4f28 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/25611 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Justin TerAvest <teravest@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-10mb/google/octopus: Capitalize MB part nameJustin TerAvest
This is for consistency with other platforms. BUG=b:77494826 BRANCH=None TEST=Sucessfully rebooted, saw updated name in SMBIOS Change-Id: I83d9075931d51b3aef8076e4567a85a808ee5047 Signed-off-by: Justin TerAvest <teravest@chromium.org> Reviewed-on: https://review.coreboot.org/25591 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-09mb/google/octopus: Enable EC wakeShaunak Saha
This patch sets the wake for EC to proper gpios. BUG=77605178 TEST=Test that lidopen wakes up the system from S3. Change-Id: Icbf30007403191005396027e74b9b6fb7319e006 Signed-off-by: Shaunak Saha <shaunak.saha@intel.com> Reviewed-on: https://review.coreboot.org/25539 Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-09mb/google/octopus/variants/baseboard: Add DPTF parametersSumeet Pawnikar
This patch adds the DPTF parameters for Octopus baseboard. These parameters are copied from reef/coral as initial reference values. BUG=None BRANCH=None TEST=Build coreboot for Octopus board. Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Change-Id: I069bae8c9ef43ebd1ee20945ef34a7f51991f621 Reviewed-on: https://review.coreboot.org/25339 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-04-06mb/google/octopus: Edge trigger cr50 interruptJustin TerAvest
Interrupts from cr50 are edge-triggered, not level-triggered. This change updates the GPIO configuration accordingly. BUG=b:75306520 BRANCH=None TEST=None Change-Id: I0c5fb4495b404412a78965c2de7f00248d0c684b Signed-off-by: Justin TerAvest <teravest@chromium.org> Reviewed-on: https://review.coreboot.org/25538 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-06mb/google/octopus/variants/baseboard: Enable DPTF supportSumeet Pawnikar
This patch enables DPTF support for Octopus baseboard. BUG=None BRANCH=None TEST=None Change-Id: I88a94c73ef0c9da708c0440f7edadd85488edfdb Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/25342 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-04-04mb/google/octopus/variants/baseboard: Set PL1 and PL2 valueSumeet Pawnikar
This patch sets PL1 value to ~6W. Here, 8W setting gives a run-time 6W actual measured power. Also, this patch sets PL2 value to 15W. BUG=None BRANCH=None TEST=Build and read the MSR 0x610. Change-Id: I2439a49b9917db0d9b05f333ce1c35003da493f6 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/25341 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-04-02mb/google/octopus: Fix Trackpad interrupt GPIO configHannah Williams
BUG=b:73137125 TEST= tested trackpad on Octopus Change-Id: Icc416e7be4e42bda188f74c69db150ba42562128 Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/25415 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-04-02mb/google/octopus: Make PMC I2C pads IOSTANDBY_IGNOREHannah Williams
This fixes wake from S0ix Change-Id: I3b340deafccbf909ec1f4b11ba9a77c6b13a89fd Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/25467 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-04-01mb/google/octopus: update SSP port and DMIC 4CH nhlt supportM Naveen
Patch corrects SSP configuration to enable audio on GLK boards. Octopus variant board uses max98357a speaker codec and 4CH DMIC, Select the appropriate NHLT blob to be packaged in CBFS. Change-Id: I101ed80f4421925120116b018424ef19d95a2a3a Signed-off-by: Naveen Manohar <naveen.m@intel.com> Reviewed-on: https://review.coreboot.org/25387 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.corp-partner.google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-03-30mb/google/octopus: Enable i2c4 which is the root port for audio codecShamile Khan
BUG=None BRANCH=None TEST=On octopus, "aplay -l" shows the Audio codec. Change-Id: I5d837d62f00d34edf28fd472ae0dbe7c0d94447a Signed-off-by: Shamile Khan <shamile.khan@intel.com> Reviewed-on: https://review.coreboot.org/25376 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-03-29mb/google/octopus: Fix wifi configurationFurquan Shaikh
This change updates devicetree and GPIO configurations to match the schematics: 1. pcie_rp...[2] is the one being used for wifi, thus, clk_req and deemphasis_enable for [2] need to be set instead of [0]. 2. WLAN power enable, wifi disable and PERST# GPIOs need to be configured correctly. BUG=b:76180142 TEST=Verified that wlan0 scan works. Change-Id: Ic51a94902e2cac3491081ade32079e5b88719f45 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/25417 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hannah Williams <hannah.williams@intel.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2018-03-27mb/google/octopus: Remove emmc tuning parameters from devicetreeFurquan Shaikh
Current emmc tuning parameters for octopus were copied over from other boards and result in failure to boot from emmc. This change gets rid of the emmc tuning parameters in devicetree. Once emmc tuning tests are run for octopus, these parameters can be added back. BUG=b:75986903 BRANCH=None TEST=Verified that octopus boots from eMMC without any errors in depthcharge. Change-Id: I7ac44a54afd1ecfe355a9654ac8e92133b67637f Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/25375 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-03-26mb/octopus: Set PNP config to PNP_PERF_POWERShaunak Saha
This patch sets the PNP config value to PNP_PERF_POWER. The config values for soc can be found in chip.h TEST = Build for octopus. Change-Id: I2239aa70cb708e6e1c06339ca9d517e7eaa198ed Signed-off-by: Shaunak Saha <shaunak.saha@intel.com> Reviewed-on: https://review.coreboot.org/25310 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-03-24mb/google/octopus: Select TPM options only if mocktpm is not selectedFurquan Shaikh
This change adds a new Kconfig option for mainboard octopus "HAS_TPM" that auto-selects all TPM related options only if VBOOT_MOCK_SECDATA is not selected. BUG=b:76203913 TEST=Compiles fine with mocktpm. Change-Id: Ib28fc47a70be58cd9a9ec65ce3b1cda68d558437 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/25340 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Jett Rink <jettrink@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-03-22mb/google/octopus: Add CLKREQ and de-emphasis settings for PCIe Wi-FIShamile Khan
BUG=b:73292699 BRANCH=None TEST=Build coreboot for Octopus board. Change-Id: Ic73ad38ad9a12bec614e530f7f35619246b9f57f Signed-off-by: Shamile Khan <shamile.khan@intel.com> Reviewed-on: https://review.coreboot.org/25288 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-03-21mb/google/octopus: Re-size flash WP_RO segmentSrinidhi N Kaushik
Update the size in WP_RO segment of the flash to accommodate builds using debug FSP. Change-Id: I0a0d1d0121b503ff390adf3ce25973d72e59fdeb Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Reviewed-on: https://review.coreboot.org/25253 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-03-21mb/google/octopus: Create bip variantJustin TerAvest
This creates a bip variant for octopus. Nothing is set in the variant files here-- everything is picked up from baseboard. BUG=b:75976864 TEST=None Change-Id: I7a8ac3d8bb71416f05ef1a605684d92d5902abda Signed-off-by: Justin TerAvest <teravest@chromium.org> Reviewed-on: https://review.coreboot.org/25285 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-03-21mb/google/octopus: Enable TPM on GSPIRavi Sarawadi
BUG=b:73133848 BRANCH=None TEST=Build coreboot for Octopus board. Tested the GSPI interface with a SPI EEPROM and got correct response to a RDID command Change-Id: Ia10ab9da0055b54a96134a6e4c51b2a229a6fecf Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com> Reviewed-on: https://review.coreboot.org/24907 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-03-19mb/google/octopus: Configure PERST_0 pinJustin TerAvest
According to the schematic, Octopus boards have WLAN_PE_RST connected to GPIO_164. This change configures that properly in devicetree. BUG=None TEST=None Change-Id: I2ba4839e036f02c5e0316d08599894879133894a Signed-off-by: Justin TerAvest <teravest@chromium.org> Reviewed-on: https://review.coreboot.org/25248 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-03-19mb/google/octopus: Fix GPIO config for DRAM_IDsJustin TerAvest
The GPIO pad configurations for GPIO68-71 are incorrectly configured as outputs. This change corrects them to be inputs. BUG=b:74932341 TEST=None Change-Id: I319f8a64d83c29ed150316c15a8d429cc7c024f3 Signed-off-by: Justin TerAvest <teravest@chromium.org> Reviewed-on: https://review.coreboot.org/25217 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-03-19mb/google/octopus: Configure PCH_WP_OD early.Justin TerAvest
The GPIO for EEPROM write-protect should be configured early, before romstage. This change configures that pad earlier. This pad is the same on the existing Octopus schematics. BUG=None TEST=None Change-Id: Idf296ba6aad75b890afabd6f7c7c51fbaf911214 Signed-off-by: Justin TerAvest <teravest@chromium.org> Reviewed-on: https://review.coreboot.org/25250 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-03-17mb/google/octopus: Do not configure GPIO_149 as GPOFurquan Shaikh
GPIO_149 is used as ESPI clock feedback and configuring it as a GPO results in EC communication failure. This change removes the configuration of GPIO_149 as GPO in ramstage so that it remains configured for ESPI (as it was when AP came out of reset). BUG=b:75348718 Change-Id: Ie4f21b12fae027cdba54ce147e6d1a88ee854792 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/25259 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-03-15mb/google/octopus: Enable audio components.Shamile Khan
Octopus uses MAX98357A speaker amplifier and DA7219 codec. Add device tree entries and Kconfig settings for these components. BUG=b:73292699,b:73230879 BRANCH=None TEST=Build coreboot for Octopus board. Change-Id: I27b5113677a8bd44dbbae587e27616d9e0b90d7f Signed-off-by: Shamile Khan <shamile.khan@intel.com> Reviewed-on: https://review.coreboot.org/25117 Reviewed-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-03-13mb/google/octopus: Add yorp variantJustin TerAvest
This creates a yorp variant for octopus; nothing too interesting now, just picks up values from the baseboard. BUG=b:74443669,b:74067452 TEST=Build Change-Id: I55af8f02d33138a3b6bab7860a665e3deb5595c2 Signed-off-by: Justin TerAvest <teravest@chromium.org> Reviewed-on: https://review.coreboot.org/25086 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-03-12mb/google/octopus: Fix lpddr4 skusJustin TerAvest
The current lpddr4 skus entries do not match the RAMID table in the schematic. This commit updates that so they are consistent. Thankfully, the values are the same as for glkrvp, so I just copied from there. BUG=b:74392818 TEST=None Change-Id: I2e63ea0b27ef58038e5a37949c31a808989c98c2 Signed-off-by: Justin TerAvest <teravest@chromium.org> Reviewed-on: https://review.coreboot.org/25063 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-03-08mb/google/octopus: Add gpio configs for communitiesShaunak Saha
This patch configures the gpios for all the gpio communites. Change-Id: Ibc16edd96f4ef6d55f3a99b195bf4920929b1578 Signed-off-by: Shaunak Saha <shaunak.saha@intel.com> Signed-off-by: Shamile Khan <shamile.khan@intel.com> Reviewed-on: https://review.coreboot.org/23799 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Justin TerAvest <teravest@chromium.org>
2018-03-08mb/google/octopus: Add device tree settingsShamile Khan
Change-Id: Id45409a9561671237410dd2f8f0bbfe61ff33562 Signed-off-by: Shamile Khan <shamile.khan@intel.com> Reviewed-on: https://review.coreboot.org/23846 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-02-28mb/google/octopus: Add LPDDR4 memory initRavi Sarawadi
Add LPDDR4 initialization support. BUG=b:73136980 BRANCH=None TEST=Build coreboot for Octopus board. Change-Id: Ieffcfa2f9d075eb0be13562f1a0c7ee503b005d9 Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com> Reviewed-on: https://review.coreboot.org/23832 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-02-15mb/google/octopus: Add new boardHannah Williams
Add octopus board using GLK soc. Copied base code from mainboard/intel/glkrvp. TODO: Fix as per octopus schematic. Change-Id: Ic8c25b3fafbfef31b8b3b802acb3bc53ee7146b6 Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/23685 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.39.1) at 2024-07-17 12:47:17 +0000