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Change-Id: I7eaf625e5acfcefdae7c81e186de36b42c06ee67
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72704
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
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The parallel mp code picks up lapics at runtime, so remove it from all
devicetrees that use this codebase.
Change-Id: I5258a769c0f0ee4bbc4facc19737eed187b68c73
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69303
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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Exposing the GPIOs via an ACPI PowerResource and the _CRS results in the
OS driver and ACPI thinking they own the GPIO. This can cause timing
problems because it's not clear which system should be controlling the
GPIO.
Previously, we flagged as an error any device which set the
'has_power_resource' flag but did not set 'disable_gpio_export_in_crs.'
There's no reason to require explicit disablement however, so drop the
superfluous 'disable' flag, and change the _CRS generation to check if
the GPIOs will be exported via the 'has_power_resource' flag instead.
BUG=b:265055477
TEST=build/boot skyrim, dump SSDT and verify touchscreen GPIOs only
listed under PRx, not under _CRS.
Change-Id: I837ae6c6fe4b8e1c4e10686406cba06bdb7759d2
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71849
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
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<gpio.h> chain-include <soc/gpio.h>.
Change-Id: Ia57d5cd33c70b6a755babd4db56c64c0e3666f9f
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71817
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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The currently assigned ACPI HID 'PNP0C50' is not a valid per Windows
WHQL validation tests. To ensure compatibility with both Windows and
Linux, set the HID to 'SYNA0000' and CID to 'ACPI0C50' as previously
done for other boards (eg, google/lulu).
TEST=boot Linux 5.1x, Windows 10 on bobba, verify all touchpad
functions work correctly.
Change-Id: I4fd66be21eeff5f37b58a8922c49683a28685064
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71074
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Switch from using ACPI "probed" flag to "detect" flag for all i2c
touchscreens and digitizers. This removes non-present devices from the
SSDT and relieves the OS of the burden of probing.
Test: build/boot Windows/Linux on various octopus variants, verify
touchscreens/digitizers functional, dump ACPI tables and verify only i2c
devices actually present on the board have entries in the SSDT.
Change-Id: I67c5bbae42e96ae21d37309e382b635321e6ef01
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63214
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The GPIOs themselves are configured as level triggered, and the drivers
(both Linux and Windows) work better with LEVEL vs EDGE triggering.
TEST=tested with rest of patch train
Change-Id: I13bc6920a0dfaf769091b1764a7584902d1f85d6
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63213
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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For octopus variants with a touchscreen/digitizer, drive the enable and
reset GPIOs high in romstage, then disable the reset GPIOs in ramstage.
Where available, only set the GPIOs for SKUs which have a touchscreen.
This will allow coreboot to detect the presence of i2c touchscreens
during ACPI SSDT generation (implemented in a subsequent commit).
TEST=tested with rest of patch train
Change-Id: Ia725b4054069c0a4f60afd7e0bca6e2fd5fdcbba
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63212
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add method variant_romstage_gpio_table() with empty weak implementation
to allow variants to override as needed for touchscreen power
sequencing (to be implemented in a subsequent commit). Call method
in romstage to program any GPIOs the variant may need to set.
TEST=tested with rest of patch train
Change-Id: I4a8e11945ae64b000051989089e0ebae22896c6b
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70905
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add NHLT endpoints for octopus boards using CS42L42 codec.
Reuse method to add da7219 endpoint as the routing is identical.
TEST=boot Windows, verify audio working with coolstar's audio drivers.
Change-Id: Id68997073752f5d90b6fe21f666a6140e22d65eb
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70371
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Remove flag in VBTs for 'Use fixed resolution at boot' to allow FSP/GOP
display init to use native panel resolution instead.
TEST=build/boot multiple google/octopus variants with edk2 payload,
verify boot logo not distorted/stretched.
Change-Id: Ia31ff28379282619dfa22a955bee1a768bb54bb8
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70373
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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This change override memory ID 3 to 1 to workaround the incorrect
memory straps in hardware.
We would use board_id 7 to identify the specific boards which need
to correct the memory ID.
BUG=b:259301885
BRANCH=Octopus
TEST=Verified on Phaser
Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com>
Change-Id: I2330b7e16a09f8cc76ed96e81a6165afa80a03a4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70353
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Derek Huang <derekhuang@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Henry Sun <henrysun@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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EC_HOST_EVENT_USB_CHARGER is no longer defined by the EC, so remove all
references.
BUG=b:216485035,b:258126464
BRANCH=none
TEST=none
Change-Id: I9e3e0e9b45385766343489ae2d8fc43fb0954923
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69374
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Jon Murphy <jpmurphy@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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Rename variant_base_gpio_table() to baseboard_gpio_table(), since the
GPIO table comes from the baseboard, and is overridden by a separate
table from the variant.
Drop the __weak qualifier as this function is not overridden.
Change-Id: I17db734784ce96cdf5e0486dc2ad057d73bfb15f
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67804
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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Rather than duplicating the entire set of GPIOs from the baseboard, use
the variant_override_gpio_table() method like all other octopus
variants do.
TEST=build/boot ampton, dump GPIOs and verify unchanged.
Change-Id: I36aa25bbee7c21a51d9fdd40405f492082455d9c
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67803
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Historically, ChromeOS devices have worked around the problem of OEMs
using several different parts for touchpads/touchscreens by using a
ChromeOS kernel-specific 'probed' flag (rejected by the upstream kernel)
to indicate that the device may or may not be present, and that the
driver should probe to confirm device presence.
Since c636142b, coreboot now supports detection for i2c devices at
runtime when creating the device entries for the ACPI/SSDT tables,
rendering the 'probed' flag obsolete for touchpads. Switch all touchpads
in the tree from using the 'probed' flag to the 'detect' flag.
Touchscreens require more involved power sequencing, which will be done
at some future time, after which they will switch over as well.
TEST: build/boot at least one variant for each baseboard in the tree.
Verify touchpad works under Linux and Windows. Verify only a single
touchpad device is present in the ACPI tables.
Change-Id: I47c6eed37eb34c044e27963532e544d3940a7c15
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67305
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Hook up FSP S UfsEnabled UPD (1d.0) to devicetree.
UFS only exist on GLK, and has been there since its
initial releases.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I1976bfd340c728c64aaf36d296ac41dcd47bfc61
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65044
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Change-Id: Ib2d0c6a23b66e6e61cc8ea09a443e19a4b37c66d
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63287
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
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Found using:
diff <(git grep -l '#include <boardid.h>' -- src/) <(git grep -l 'UNDEFINED_STRAPPING_ID\|BOARD_ID_UNKNOWN\|BOARD_ID_INIT\|board_id(\|ram_code(\|sku_id(' -- src/) |grep "<"
Change-Id: I2611be41e8730a9b189b1b0aa3fe62be0757b371
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60748
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <martinroth@google.com>
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Change-Id: I88406fa1b54312616e6717af3d924436dc4ff1a6
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58899
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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The only purpose of mainboard_chromeos_acpi_generate()
was to pass cros_gpio array for ACPI \\OIPG package
generation.
Promote variant_cros_gpio() from baseboards to ChromeOS
declaration.
Change-Id: I5c2ac1dcea35f1f00dea401528404bc6ca0ab53c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58897
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Found using:
diff <(git grep -l '#include <delay.h>' -- src/) <(git grep -l 'get_timer_fsb(\|init_timer(\|udelay(\|mdelay(\|delay(' -- src/) |grep "<"
Change-Id: I50fcbb16895662c7451fec1569a8a61398792531
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60607
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Add ALC5682I-VS codec support. ALC5682I-VD/ALC5682I-VS load different
hid name depending on SSFC.
BUG=b:198722640
BRANCH=octopus
TEST=Set CBI SSFC BIT9-11 to select codec, and test audio works
Change-Id: I80be12d88e100ce8586371fc49b36447859e24f8
Signed-off-by: Paul Huang <paul2_huang@pegatron.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59856
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marco Chen <marcochen@google.com>
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Add VBTs for all octopus variants currently supported by
ChromeOS recovery images. For variants which use multiple
VBTs and select at runtime, ensure these are added directly
to CBFS.
Change-Id: I4b5c4268f9255d658f9762d94488db66e0677830
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59327
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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This reverts commit adb393bdd6cd6734fa2672bd174aca4588a68016.
This relands commit 6260bf712a836762b18d80082505e981e040f4bc.
Reason for revert:
The original CL did not handle some devices correctly.
With the fixes:
* commit 36721a4 (mb/google/brya: Add GPIO_IN_RW to all variants'
early GPIO tables)
* commit 3bfe46c (mb/google/guybrush: Add GPIO EC in RW to early
GPIO tables)
* commit 3a30cf9 (mb/google/guybrush: Build chromeos.c in verstage
This CL also fix the following platforms:
* Change to always trusted: cyan.
* Add to early GPIO table: dedede, eve, fizz, glados, hatch, octopus,
poppy, reef, volteer.
* Add to both Makefile and early GPIO table: zork.
For mb/intel:
* adlrvp: Add support for get_ec_is_trusted().
* glkrvp: Add support for get_ec_is_trusted() with always trusted.
* kblrvp: Add support for get_ec_is_trusted() with always trusted.
* kunimitsu: Add support for get_ec_is_trusted() and initialize it as
early GPIO.
* shadowmountain: Add support for get_ec_is_trusted() and initialize
it as early GPIO.
* tglrvp: Add support for get_ec_is_trusted() with always trusted.
For qemu-q35: Add support for get_ec_is_trusted() with always trusted.
We could attempt another land.
Change-Id: I66b8b99d6e6bf259b18573f9f6010f9254357bf9
Signed-off-by: Hsuan Ting Chen <roccochen@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58253
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
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It's commented in <types.h> that it shall provide <commonlib/helpers.h>.
Fix for ARRAY_SIZE() in bulk, followup works will reduce the number
of other includes these files have.
Change-Id: I2572aaa2cf4254f0dea6698cba627de12725200f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58996
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Change-Id: Ibbdd589119bbccd3516737c8ee9f90c4bef17c1e
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58923
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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These issues were found and fixed by codespell, a useful tool for
finding spelling errors.
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: Ie34003a9fdfe9f3b1b8ec0789aeca8b9435c9c79
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58081
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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add CBI sku RAM ID 5 for 4GiB Capacity with dual channel and dual rank
with 4gb dram density.
BUG=b:178665760
BRANCH=Octopus
TEST=build fw and flash to the dut with RAMID 5, dut can boot up successfully.
Signed-off-by: Pan Sheng-Liang <sheng-liang.pan@quanta.corp-partner.google.com>
Change-Id: I922a518cffc4dac71caec68e6f7a55c6c5717438
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56982
Reviewed-by: Marco Chen <marcochen@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The change from Synaptics S7817 to Elan 3915N and pin distribution
of touch IC is the same.
The original Elan section was copied from reference design and
was never used before.
According to vendor spec definition IRQ trigger method needs to
change to level.
BUG=b:190574692
TEST=Build coreboot and check that device works
Change-Id: I44ee779242779c78ceafdddd34dca2571e714dd3
Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56380
Reviewed-by: Marco Chen <marcochen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch makes Ampton EC wake up AP from s0ix when the state of
charge drops to 2%.
Demonstrated as follows:
1. Boot Ampton.
2. Run powerd_dbus_suspend.
3. On EC, run battfake 2.
4. System resumes.
BUG=b:189540432
BRANCH=Octopus
TEST=Verified on Ampton.
Change-Id: I98d8e6ea185e8782ad675d4668678b341ca5d350
Signed-off-by: James Chao <james_chao@asus.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56341
Reviewed-by: Marco Chen <marcochen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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BUG=b:191213716
BRANCH=octopus
TEST=adjust SSFC value of CBI to select RT5682 or DA7219 then check
whether device tree is updated correspondingly by disabling unselected
one.
Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Change-Id: I2d5738442d2c173fd5b4802d8b5dff76b428c6f7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55564
Reviewed-by: Marco Chen <marcochen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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An error in script did not set the attribute properly:
- Entry CS0 is not used as sensor, but as ground,
- Entry CS1 is used as the startup sensor.
This fixes a regression caused by commit
689c25b9d6 (drivers/i2c: sx9310: Replace register map with descriptive names)
EQ=b:173341604
BRANCH=volteer
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Change-Id: I92c01209031e9a917d95b1cb2537b0ce7b93e66d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51893
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add audio codec module RT5682 in project and define GPIO_137 in the
override_table for SSFC framework to adjust IRQ configuration.
BUG=b:182221327
BRANCH=octopus
TEST=adjust SSFC value of CBI to select RT5682I or DA7219 then check whether device tree is updated correspondingly by disabling unselected one.
Signed-off-by: Kevin Chang <kevin.chang@lcfc.corp-partner.google.com>
Change-Id: I202f71f57ad2db84fb90b52f9ffd7a1fd05494a3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52878
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marco Chen <marcochen@google.com>
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Disable HSBIAS sense setting.
BUG=b:184103445
TEST=boot to check cs42l42 is functional.
Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Change-Id: I12c0e0a0f7490d35d36fe8ccbc940f29e1bb7976
Reviewed-on: https://review.coreboot.org/c/coreboot/+/53901
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Vitaly Rodionov <vitaly.rodionov@cirrus.corp-partner.google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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BUG=b:186380809
BRANCH=octopus
TEST=adjust SSFC value of CBI to select RT5682 or DA7219 then check
whether device tree is updated correspondingly by disabling unselected
one.
Change-Id: I0975a8b64452c3f636e6c5937c6918518ec5b4e9
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52720
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marco Chen <marcochen@google.com>
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Add cs42l42 codec support in fleex.
BUG=b:184103445
TEST=boot to check cs42l42 is functional.
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I1571003f8b272a573e6ab9fb525f17659bae8c4c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52363
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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This patch makes all Octopus variants resume from S0ix/S3 on AC plug
and unplug.
Change-Id: Iab054d77368bf2047b6d523188b8c401a7643aaa
Signed-off-by: Derek Basehore <dbasehore@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51654
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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|
Currently, if `get_wifi_sar_cbfs_filename()` returns NULL, then
`get_wifi_sar_limits()` assumes that the default filename is used for
CBFS SAR file. This prevents a board from supporting different models
using the same firmware -- some which require SAR support and some
which don't.
This change updates the logic in `get_wifi_sar_limits()` to return
early if filename is not provided by the mainboard. In order to
maintain the same logic as before, current mainboards are updated to
return WIFI_SAR_CBFS_DEFAULT_FILENAME instead of NULL in default
case.
Change-Id: I68b5bdd213767a3cd81fe41ace66540acd68e26a
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51485
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Fleex will use SSFC to support RTL5682.
BUG=b:178653122
TEST=abuild
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: Icb06eabe297c5562bd2171b52cc9671c342e6dfd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51423
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marco Chen <marcochen@google.com>
|
|
The current driver is using chip registers map to configure the SAR
sensor, which is opaque, especially when the datasheet is not published
widely.
Use more descriptive names, as defined in Linux kernel documentation at
https://www.kernel.org/doc/Documentation/devicetree/bindings/iio/proximity/semtech%2Csx9310.yaml
BUG=b:173341604
BRANCH=volteer
TEST=Dump all tables, check semtech property:
for i in $(find /sys/firmware/acpi/tables/ -type f) ; do
f=$(basename $i); cat $i > /tmp/$f.dat ; iasl -d /tmp/$f.dat
done
In SSDT.dsl, we have:
Package (0x06)
{
Package (0x02)
{
"semtech,cs0-ground",
Zero
},
Package (0x02)
{
"semtech,startup-sensor",
Zero
},
Package (0x02)
{
"semtech,proxraw-strength",
Zero
},
Package (0x02)
{
"semtech,avg-pos-strength",
0x0200
},
Package (0x02)
{
"semtech,combined-sensors",
Package (0x03)
{
Zero,
One,
0x02
}
},
Package (0x02)
{
"semtech,resolution",
"finest"
}
}
Change-Id: I8d1c81b56eaeef1dbb0f73c1d74c3a20e8b2fd7b
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50210
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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|
Fleex has other project share the same FW. Only fleex has LTE sku.
So we need to make sure it is fleex then check if LTE sku.
BUG=b:181946744
BRANCH=octopus
TEST=Check no SAR table can be loaded with sku id 4 and 5.
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I9f3d5fed4315fc716acad1a07735221d154c377e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51288
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marco Chen <marcochen@google.com>
Reviewed-by: Henry Sun <henrysun@google.com>
|
|
Change-Id: I960870fabde1dacfe52a8a35c253b0bd097d3e10
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50183
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
|
|
Disable DRRS in VBT to solve panel flick issue
SKU ID
49/51 will use vbt_garfour.bin
50/52 will use vbt_garfour_hdmi.bin
BUG=b:177783330
BRANCH=octopus
TEST=emerge-octopus coreboot chromeos-bootimage
check /run/debug/i915_drrs_status shows DRRS supported NO.
Cq-Depend: chrome-internal:3534569
Change-Id: I5ebb66ec043a6b409dd5abbc31da417f50dbad5c
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49635
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
UART pad configuration should not be done in common code, because that
may cause short circuits, when the user sets a wrong UART index. Thus,
add the corresponding pads to the early UART gpio table for the board as
a first step. Common UART pad config code then gets dropped in CB:48829.
Also switch to `bootblock_mainboard_early_init` to configure the pads in
early bootblock before console initialization, to make the console work
as early as possible. The board does not do any other gpio configuration
in bootblock, so this should not influence behaviour in a negative way
(e.g. breaking overrides).
Change-Id: Ieeb738afd54e77ee853ee109009f611411aa0d4a
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49426
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Do LPC/eSPI pad configuration at board-level to match other platforms by
adding an appropriate early gpio table in the bootblock.
The soc code gets dropped in CB:49410.
Change-Id: Ie33bae481f430a1c4410a0a4e2b2a34a3e78adaa
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49411
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
BUG=b:171757619
BRANCH=octopus
TEST=adjust SSFC value of CBI to select RT5682 or DA7219 then check
whether device tree is updated correspondingly by disabling unselected
one.
Change-Id: I37390535e263b4b9547ad7307278e3360ba836bd
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48945
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marco Chen <marcochen@google.com>
|
|
BUG=b:174118027
BRANCH=octopus
TEST=adjust SSFC value of CBI to select RT5682 or DA7219 then check
whether device tree is updated correspondingly by disabling unselected
one.
Signed-off-by: Marco Chen <marcochen@google.com>
Change-Id: Id37c4c5716ade0851cfcb24e12b390841e633ac9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48795
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Zhuohao Lee <zhuohao@chromium.org>
|
|
Enables backlight control under Windows 10.
Test: build/boot Windows 10 20H2 on google/ampton, verify
display backlight controls functional.
Change-Id: I779f7f3f5a111018fc7b5c50c5750a9eb815d670
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40594
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
|
|
Add devicetree configuration for G2TOUCH Touchscreen controller.
BUG=b:175513059
BRANCH=octopus
TEST=build bios, check i2c bus and verify touch screen works fine
Change-Id: Ib57597c4998f205c664e13befb4c44532b7dbd4f
Signed-off-by: rasheed.hsueh <rasheed.hsueh@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48552
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
|
|
This change adds support zinitix touchpad for casta/bluebird.
BRANCH=firmware-octopus-11297.B
BUG=b:175618033
TEST=built and verified touchpad worked on casta
Change-Id: I1a8f562de19d1a8160d52c65400553f0c68393e0
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48634
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
This CL add droid lte sku 37 38 39 40 to load wifi_sar-droid.hex.
BUG=none
BRANCH=octopus
TEST=emerge-octopus coreboot
Signed-off-by: Pan Sheng-Liang <sheng-liang.pan@quanta.corp-partner.google.com>
Change-Id: I55dda85b8f3e664d97834b712a2c6a48d1434010
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47697
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Add G2Touch touchscreen support for bobba.
BUG=b:171636614, b:169730666
BRANCH=octopus
TEST=emerge-octopus coreboot chromeos-bootimage, and check touchscreen
work.
Signed-off-by: Pan Sheng-Liang <sheng-liang.pan@quanta.corp-partner.google.com>
Change-Id: Ia361a56c050d7cbd7325b3c09fc34d8707441cc4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46808
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
As per HID over I2C Protocol Specification[1] Version 1.00 Section 7.4,
the interrupt line used by the device is required to be level triggered.
Hence, this change updates the configuration of the HID over I2C devices
to be level triggered.
References:
[1] http://download.microsoft.com/download/7/d/d/7dd44bb7-2a7a-4505-ac1c-7227d3d96d5b/hid-over-i2c-protocol-spec-v1-0.docx
BUG=b:172846122
TEST=./util/abuild/abuild
Change-Id: Ic334816712370da63471135da8dd598ab02d54ef
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47421
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
Add new SKU definition:
Garg360 (LTE DB,1A2C,TS, no stylus, rear camera) SKU ID - 39
BUG=b:170708728
BRANCH=octopus
TEST=emerge-octopus coreboot chromeos-bootimage
Change-Id: Ifec4e1360bd1aff3825bc6413b0a2ccd8b822075
Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47015
Reviewed-by: Marco Chen <marcochen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
variant_smi_sleep is called in smm stage so we need to add
variant.c into smm stage. Otherwise it will call the dummy one.
BUG=b:168075958
BRANCH=octopus
TEST=build image passed.
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I41df1a30b119ab3e04f9ae01955b6044f137527f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46847
Reviewed-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com>
Reviewed-by: Marco Chen <marcochen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Add G2Touch touchscreen support for dood.
BUG=b:171526389
BRANCH=octopus
TEST=emerge-octopus coreboot chromeos-bootimage, and check touchscreen
work.
Signed-off-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com>
Change-Id: Ica7d893de285c2dd1efcd43ac74919bdd5d5ac17
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46675
Reviewed-by: Marco Chen <marcochen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
This change reorganizes the CNVi device entries in mainboard
devicetree/overridetree and SoC chipset tree to make it consistent
with how other SoC internal PCI devices are represented i.e. without a
chip driver around the SoC controller itself.
Before:
chip drivers/wifi/generic
register "wake" = "..."
device pci xx.y on end
end
After:
device pci xx.y on
chip drivers/wifi/generic
register "wake" = "..."
device generic 0 on end
end
end
Change-Id: I22660047a3afd5994400341de0ca461bbc0634e2
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46865
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
|
|
LTE module Fibocom L850-GL is lost after idle overnight,
with this workaround, host will not initiate U3 wakeup
at the same time with device, which will avoid the race condition.
If this option is set in the devicetree, the bits[7:4] in XHCI MMIO BAR +
offset 0x80A4 (PMCTRL_REG) will be updated from default 9 to 0.
BUG=b:169645448
BRANCH=octopus
TEST=build coreboot with DisableXhciLfpsPM being set to 1 and flash
the image to the device. Run following command to check if
bits[7:4] is set 0:
>iotools mmio_read32 "XHCI MMIO BAR + 0x80A4"
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I3a04320b0e2441dce540a5afdc461f12de45c41b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46868
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marco Chen <marcochen@google.com>
|
|
LTE module Fibocom L850-GL is lost after idle overnight,
with this workaround, host will not initiate U3 wakeup
at the same time with device, which will avoid the race condition.
If this option is set in the devicetree, the bits[7:4] in XHCI MMIO BAR +
offset 0x80A4 (PMCTRL_REG) will be updated from default 9 to 0.
BUG=b:171478764
BRANCH=octopus
TEST=build coreboot with DisableXhciLfpsPM being set to 1 and flash
the image to the device. Run following command to check if
bits[7:4] is set 0:
>iotools mmio_read32 "XHCI MMIO BAR + 0x80A4"
Change-Id: I213fed2b56f216747b2727b69f97d46d8c0c872e
Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46701
Reviewed-by: Marco Chen <marcochen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
invoke LTE power off function to meet LTE power sequence while DUT is
in reboot state.
BUG=b:167565015
BRANCH=octopus
TEST=build and verify on the DUT with LTE
Change-Id: I825cefb524ddaf9a9cb6add31c2ee0eea484f978
Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46022
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Marco Chen <marcochen@google.com>
Reviewed-by: Henry Sun <henrysun@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Add goodix touch pad as below:
HWID : GXTP7288
CID : PNP0C50
I2C address : 0x2C
I2C speed : 400Khz
HID Descriptor Address : 0x20
BUG=b:171351666
BRANCH=octopus
TEST=build image and verify goodix touch pad working.
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: Idb4f8d3aff09712dcc98c8ae0c9ae30dc4049e29
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46614
Reviewed-by: Marco Chen <marcochen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
New SKU ID 5 is used for LTE touch SKU. This patch does LTE power off
for LTE sku and only use Wifi SAR table for non-LTE sku.
BUG=b:168001586
BRANCH=octopus
TEST=Check no SAR table can be loaded with sku id 4 and 5.
Change-Id: Ic0405d3e52aa813bbb1f350966a9e2825e595ce4
Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46643
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
BUG=b:170703029
BRANCH=octopus
TEST=emerge-octopus coreboot
Signed-off-by: James Chao <james_chao@asus.corp-partner.google.com>
Change-Id: I2bf642963283b8a31a3bd9504c40541ca2f64b34
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46344
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
|
|
This change switches all mainboard devices to use drivers/wifi/generic
instead of drivers/intel/wifi chip driver for Intel WiFi
devices. There is no need for two separate chip drivers in coreboot to
handle Intel and non-Intel WiFi devices since the differences can be
handled at runtime using the PCI vendor ID. This also allows mainboard
to easily multi-source WiFi chips and still use the same firmware
image without having to distinguish between the chip drivers.
BUG=b:169802515
BRANCH=zork
Change-Id: Ieac603a970cb2c9bf835021d1fb0fd07fd535280
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46035
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
|
|
ALS is not stuffed in octopus boards. Hence disable ALS ACPI devices.
BUG=b:169245831
BRANCH=octopus
TEST=Ensure that ALS devices are disabled in ACPI tables.
Change-Id: I5ad28f01b0515a41b314116eb2d05c520df0f86e
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45741
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
This patch makes Fleex EC wake up AP from s0ix when the state of
charge drops to 5%.
Demonstrated as follows:
1. Boot Fleex.
2. Run powerd_dbus_suspend.
3. On EC, run battfake 5.
4. System resumes.
BUG=b:163721887
BRANCH=Octopus
TEST=Verified on Fleex:
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Change-Id: I4a998ad0aef5a7cfc6fd18995bde5571e6127e77
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45967
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
|
|
Only do LTE power off for LTE sku in order to save extra 130ms delay
for non-LTE sku.
BUG=b:168075958
BRANCH=octopus
TEST=build image and verify on the DUT with LTE DB.
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: If983185ff2f09fb1b2553c6ff1a1473d3254de4b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45687
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marco Chen <marcochen@google.com>
|
|
Use Wifi SAR table for non-LTE sku only.
BUG=b:169115341
BRANCH=octopus
TEST=Check no SAR table can be loaded with sku id 4.
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I086fa14a9f23e4a0fc0ef8085040219c932dbf17
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45640
Reviewed-by: Marco Chen <marcochen@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
0x12 will be more stable according to validation result on SD card and
USB devices.
BUG=b:163382089
BRANCH=none
TEST=check if SD cards and USB devices work properly
Signed-off-by: Marx Wang <marx.wang@intel.com>
Change-Id: Ic98f27b6164daa3667009300439c61fed43a4a0b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45573
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Henry Sun <henrysun@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Change-Id: I4151d1a6ce94763432f307fbc8bc4afe229856ea
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44616
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
|
|
All octopus board share the same power off sequence.
Move to smihandler.c instead variant.c.
BUG=b:168075958
BRANCH=octopus
TEST=build image and verify on the DUT with LTE DB.
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I2be5a656fb42fff99c56d21aaa73ed9140caad37
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45436
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
GPIOs related to power sequence are
GPIO_67 - EN_PP3300
GPIO_117 - FULL_CARD_POWER_ON_OFF
GPIO_161 - PLT_RST_LTE_L
1. Power on: GPIO_67 -> 0ms -> GPIO_117 -> 30ms -> GPIO_161
2. Power off: GPIO_161 -> 30ms -> GPIO_117 -> 100ms -> GPIO_67
3. Power reset:
- keep GPIO_67 and GPIO_117 high and
- pull down GPIO_161 for 30ms then release it.
BUG=b:168075958
BRANCH=octopus
TEST=build image and verify on the DUT with LTE DB.
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I9b56ef8ff346c1d4edd5aad04d4a7396c4702ffc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45193
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Henry Sun <henrysun@google.com>
Reviewed-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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BUG=b:167297664
BRANCH=octopus
TEST=build fleex, and check touchscreen can work
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Change-Id: I910681c258ff5487830e795a8bd08c66be69b1d4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44980
Reviewed-by: Justin TerAvest <teravest@google.com>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Marco Chen <marcochen@google.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Henry Sun <henrysun@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Convert 0X -> 0x
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Change-Id: Iea3ca67908135d0e85083a05bad2ea176ca34095
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44926
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Disable xHCI compliance mode to prevent SS hub detection issue.
BRANCH=firmware-octopus-11297.B
BUG=none
TEST=built
Change-Id: I7a9bbc92565e752a8f8f4689519c100594596701
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44438
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Set default value of ModPhyIfValue parameter in FSPS_UPD.
Without this setting, it will be set to '0' and system may not detect
USB 3.0 device.
BUG=b:163382089
BRANCH=firmware-octopus-11297.B
TEST=Built
Change-Id: Ide3d1637f99dba28251102f771b6ce370cc5d8e4
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44436
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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Use tabs instead of eight (sometimes less) spaces.
Change-Id: Ic3d61f5210d21d9613fc50b47b90af71f544169a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44113
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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SKUID
51 - Garfour EVT (non-touch, TypeA DB)
52 - Garfour DVT (touch, HDMI DB)
BUG=b:161554087
BRANCH=octopus
TEST=emerge-octopus coreboot chromeos-bootimage
Change-Id: I3cb17c2b665c303da210817a531c869c6324b249
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43670
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Henry Sun <henrysun@google.com>
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due to overridetree.cb set disable_xhci_lfps_pm = 0,
need correct condition expression to let function work.
BUG=b:155955302
BRANCH=octopus
TEST=build coreboot with DisableXhciLfpsPM being set to 1 and flash
the image to the device. Run following command to check if
bits[7:4] is set 0:
>iotools mmio_read32 "XHCI MMIO BAR + 0x80A4"
Signed-off-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com>
Change-Id: Ia047c75611a35aafd15f2481bf64049e13d4a2ff
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42860
Reviewed-by: Marco Chen <marcochen@google.com>
Reviewed-by: Henry Sun <henrysun@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This change allows mainboard to configure different wakeup routes that
can be used by a GPIO key:
1. SCI: This is selected when SCI route is used to wake the system. It
results in _PRW property being exposed in ACPI tables.
2. GPIO IRQ: This is selected when GPIO controller wake is used to
wake the system. It is typically used when the input signal is not
dual routed and the GPIO controller block is not capable of applying
filters for IRQ and wake separately. In this case, _PRW is not exposed
in ACPI tables for the key device.
3. Disabled: No wakeup supported.
Based on these wakeup routes, gpio_keys_add_child_node() is updated to
expose _PRW and _DSD properties for wakeup appropriately.
Additionally, the change updates mainboards that were already using
gpio_keys to set wakeup_route attribute correctly and renames "wake"
to "wake_gpe" to make the usage clear.
BUG=b:159942427
Change-Id: Ib32b866b5f0ca559ed680b46218454bdfd8c6457
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42826
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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due to overridetree.cb set disable_xhci_lfps_pm = 0,
need correct condition expression to let function work.
BUG=b:146768983
BRANCH=octopus
TEST=build coreboot with DisableXhciLfpsPM being set to 1 and flash
the image to the device. Run following command to check if
bits[7:4] is set 0:
>iotools mmio_read32 "XHCI MMIO BAR + 0x80A4"
Signed-off-by: Pan Sheng-Liang <sheng-liang.pan@quanta.corp-partner.google.com>
Change-Id: I53621d7674a531adfa40e8703cb2cd01c50376b8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42564
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Henry Sun <henrysun@google.com>
Reviewed-by: Marco Chen <marcochen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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BUG=b:156564296
BRANCH=octopus
TEST=emerge-octopus coreboot
Change-Id: I99b04fec88da481e21b7a05807a4f1edeb3a5bdf
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42036
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
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Update processor power limit configuration parameters based on
common code base support for Intel Apollo Lake SoC based platforms.
BRANCH=None
BUG=None
TEST=Built and tested on octopus system
Change-Id: I609744d165a53c8f91e42a67da1b972de00076a5
Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41233
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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When any USB image disk is connected to the DUT through
HUAWEI/APPLE Dongle, press Ctrl + u on the dev screen,
it cannot boot from USB.
We found the SS hub cannot be enumerated. So disable xHCI
compliance mode.
BRANCH=octopus
BUG=b:155347573
TEST=Confirm successful boot from USB
Change-Id: Iea4a3df156da0627336f7d6c1e03837b6cf0e7f2
Signed-off-by: tong.lin <tong.lin@bitland.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40905
Reviewed-by: Marco Chen <marcochen@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Stefan thinks they don't add value.
Command used:
sed -i -e '/file is part of /d' $(git grep "file is part of " |egrep ":( */\*.*\*/\$|#|;#|-- | *\* )" | cut -d: -f1 |grep -v crossgcc |grep -v gcov | grep -v /elf.h |grep -v nvramtool)
The exceptions are for:
- crossgcc (patch file)
- gcov (imported from gcc)
- elf.h (imported from GNU's libc)
- nvramtool (more complicated header)
The removed lines are:
- fmt.Fprintln(f, "/* This file is part of the coreboot project. */")
-# This file is part of a set of unofficial pre-commit hooks available
-/* This file is part of coreboot */
-# This file is part of msrtool.
-/* This file is part of msrtool. */
- * This file is part of ncurses, designed to be appended after curses.h.in
-/* This file is part of pgtblgen. */
- * This file is part of the coreboot project.
- /* This file is part of the coreboot project. */
-# This file is part of the coreboot project.
-# This file is part of the coreboot project.
-## This file is part of the coreboot project.
--- This file is part of the coreboot project.
-/* This file is part of the coreboot project */
-/* This file is part of the coreboot project. */
-;## This file is part of the coreboot project.
-# This file is part of the coreboot project. It originated in the
- * This file is part of the coreinfo project.
-## This file is part of the coreinfo project.
- * This file is part of the depthcharge project.
-/* This file is part of the depthcharge project. */
-/* This file is part of the ectool project. */
- * This file is part of the GNU C Library.
- * This file is part of the libpayload project.
-## This file is part of the libpayload project.
-/* This file is part of the Linux kernel. */
-## This file is part of the superiotool project.
-/* This file is part of the superiotool project */
-/* This file is part of uio_usbdebug */
Change-Id: I82d872b3b337388c93d5f5bf704e9ee9e53ab3a9
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41194
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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LTE module Fibocom L850-GL is lost after idle overnight, with this workaround, host will not initiate U3 wakeup at the same time with device, which will avoid the race condition.
Disable XHCI LFPS power management. If the option is set in the devicetree, the bits[7:4] in XHCI MMIO BAR + offset 0x80A4 (PMCTRL_REG) will be updated from default 9 to 0.
BUG=b:155955302
BRANCH=octopus
TEST=build coreboot with DisableXhciLfpsPM being set to 1 and flash
the image to the device. Run following command to check if
bits[7:4] are set 0:
>iotools mmio_read32 "XHCI MMIO BAR + 0x80A4"
Signed-off-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com>
Change-Id: I88357f44317a5cff2e04508638eb065e5ada4c4c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41143
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marco Chen <marcochen@google.com>
Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
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This change moves all ACPI table support in coreboot currently living
under arch/x86 into common code to make it architecture
independent. ACPI table generation is not really tied to any
architecture and hence it makes sense to move this to its own
directory.
In order to make it easier to review, this change is being split into
multiple CLs. This is change 3/5 which basically is generated by
running the following command:
$ git grep -iIl "arch/acpi" | xargs sed -i 's/arch\/acpi/acpi\/acpi/g'
BUG=b:155428745
Change-Id: I16b1c45d954d6440fb9db1d3710063a47b582eae
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40938
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
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LTE module is lost after idle overnight, with this workaround,
host will not initiate U3 wakeup at the same time with device,
which will avoid the race condition.
Disable XHCI LFPS power management.
If the option is set in the devicetree, the bits[7:4] in
XHCI MMIO BAR + offset 0x80A4 (PMCTRL_REG) will be updated
from default 9 to 0.
BUG=b:146768983
BRANCH=octopus
TEST=build coreboot with DisableXhciLfpsPM being set to 1 and flash
the image to the device. Run following command to check if
bits[7:4] is set 0:
>iotools mmio_read32 "XHCI MMIO BAR + 0x80A4"
Signed-off-by: Pan Sheng-Liang <sheng-liang.pan@quanta.corp-partner.google.com>
Change-Id: Ib8e5ae79e097debf0c75ead232ddbb2baced2a2a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40303
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marco Chen <marcochen@google.com>
Reviewed-by: Henry Sun <henrysun@google.com>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
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SKUID:
49 - Garfour EVT (touch, TypeA DB)
50 - Garfour EVT (non-touch, HDMI DB)
BUG=b:152861752
BRANCH=octopus
TEST=emerge-octopus coreboot chromeos-bootimage
Change-Id: I656a2bb2404efded6da6697664748b6c8d2ca4e0
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40586
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Marco Chen <marcochen@google.com>
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Add VBT file, extracted from stock Google firmware, and
select its use via Kconfig.
Change-Id: I256c1c72d1d1e40ea9426fa717bfc4f9c950a91f
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40595
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Since the first LFPS timeout causes xHCI to enter compliance
mode, the SS hub cannot be enumerated. The resolution is to
disable xHCI compliance mode.
BRANCH=octopus
BUG=b:153782196
TEST=Verified usb operation successfully.
Signed-off-by: Julia Tsai <julia.tsai@lcfc.corp-partner.google.com>
Change-Id: If0bf68c8cf0a2a3b857395b6b82e46cc384ba65c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39874
Reviewed-by: Henry Sun <henrysun@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Since the first LFPS timeout causes xHCI to enter compliance
mode, the SS hub cannot be enumerated. The resolution is to
disable xHCI compliance mode.
BRANCH=octopus
BUG=b:149723583
TEST=Verified USB operation successfully.
Signed-off-by: tong.lin <tong.lin@bitland.corp-partner.google.com>
Change-Id: I3e6ab6ec0c4865cf2467da900f13d18468ff356f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39968
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Marco Chen <marcochen@google.com>
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Done with sed and God Lines. Only done for C-like code for now.
Change-Id: I8076155330100982de82d410b6579ac99ed89e7b
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40187
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add HID field in max98357a_config and allow mainboards to set it.
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Change-Id: I22d2d078a9a4eb6ab330da8439737ff5133086d4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39286
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Adds GMM into the baseboard of Octopus
For GLK, PCI device 3 is GMM according to
Document#: 569262(Glk EDS Vol-1 rev2-7)
Related to Gerrit review 39579
BUG=b:151115705
BRANCH=None
TEST=Flashed final image on Chromebook
Change-Id: I75b4a835c18c5eeb542b7f7b89deea45a31e47bd
Signed-off-by: Franklin He <franklinh@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39600
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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They're listed in AUTHORS and often incorrect anyway, for example:
- What's a "Copyright $year-present"?
- Which incarnation of Google (Inc, LLC, ...) is the current
copyright holder?
- People sometimes have their editor auto-add themselves to files even
though they only deleted stuff
- Or they let the editor automatically update the copyright year,
because why not?
- Who is the copyright holder "The coreboot project Authors"?
- Or "Generated Code"?
Sidestep all these issues by simply not putting these notices in
individual files, let's list all copyright holders in AUTHORS instead
and use the git history to deal with the rest.
Change-Id: I09cc279b1f75952bb397de2c3f2b299255163685
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39607
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
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Foob360 would prefer to use different SAR values. Since Foob360
sku id is 9.
BUG=b:149362272
BRANCH=octopus
TEST=build
Signed-off-by: peichao.wang <peichao.wang@bitland.corp-partner.google.com>
Change-Id: I8cc5d73629990f19d2c1044debdba4990c54d07e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39424
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marco Chen <marcochen@google.com>
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Leverage the common sku id space helper encoders and
set the sku id max to 0xff for legacy to ensure we
behave the same.
BUG=b:149348474
BRANCH=none
TEST=tested on hatch
Change-Id: I60a37a5f9659b8df4018872956f95e07a3506440
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39035
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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This is new elan touch screen IC, which includes touch panel and USI pen.
BUG=b:149800883
BRANCH=octopus
TEST=build bios and verify touch screen works fine
Signed-off-by: Tommie Lin <tong.lin@bitland.corp-partner.google.com>
Change-Id: Ibec3d08cc740e398a10a5c845181318724afc70a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38823
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Henry Sun <henrysun@google.com>
Reviewed-by: Marco Chen <marcochen@google.com>
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