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path: root/src/mainboard/google/octopus/variants/phaser/gpio.c
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2020-05-11treewide: Remove "this file is part of" linesPatrick Georgi
Stefan thinks they don't add value. Command used: sed -i -e '/file is part of /d' $(git grep "file is part of " |egrep ":( */\*.*\*/\$|#|;#|-- | *\* )" | cut -d: -f1 |grep -v crossgcc |grep -v gcov | grep -v /elf.h |grep -v nvramtool) The exceptions are for: - crossgcc (patch file) - gcov (imported from gcc) - elf.h (imported from GNU's libc) - nvramtool (more complicated header) The removed lines are: - fmt.Fprintln(f, "/* This file is part of the coreboot project. */") -# This file is part of a set of unofficial pre-commit hooks available -/* This file is part of coreboot */ -# This file is part of msrtool. -/* This file is part of msrtool. */ - * This file is part of ncurses, designed to be appended after curses.h.in -/* This file is part of pgtblgen. */ - * This file is part of the coreboot project. - /* This file is part of the coreboot project. */ -# This file is part of the coreboot project. -# This file is part of the coreboot project. -## This file is part of the coreboot project. --- This file is part of the coreboot project. -/* This file is part of the coreboot project */ -/* This file is part of the coreboot project. */ -;## This file is part of the coreboot project. -# This file is part of the coreboot project. It originated in the - * This file is part of the coreinfo project. -## This file is part of the coreinfo project. - * This file is part of the depthcharge project. -/* This file is part of the depthcharge project. */ -/* This file is part of the ectool project. */ - * This file is part of the GNU C Library. - * This file is part of the libpayload project. -## This file is part of the libpayload project. -/* This file is part of the Linux kernel. */ -## This file is part of the superiotool project. -/* This file is part of the superiotool project */ -/* This file is part of uio_usbdebug */ Change-Id: I82d872b3b337388c93d5f5bf704e9ee9e53ab3a9 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41194 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-06mb/google/octopus: Use SPDX for GPL-2.0-only filesAngel Pons
Done with sed and God Lines. Only done for C-like code for now. Change-Id: I8076155330100982de82d410b6579ac99ed89e7b Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40187 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-18mainboard/google: Remove copyright noticesPatrick Georgi
They're listed in AUTHORS and often incorrect anyway, for example: - What's a "Copyright $year-present"? - Which incarnation of Google (Inc, LLC, ...) is the current copyright holder? - People sometimes have their editor auto-add themselves to files even though they only deleted stuff - Or they let the editor automatically update the copyright year, because why not? - Who is the copyright holder "The coreboot project Authors"? - Or "Generated Code"? Sidestep all these issues by simply not putting these notices in individual files, let's list all copyright holders in AUTHORS instead and use the git history to deal with the rest. Change-Id: I09cc279b1f75952bb397de2c3f2b299255163685 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39607 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2019-04-23src: Use include <console/console.h> when appropriateElyes HAOUAS
Change-Id: Iddba5b03fc554a6edc4b26458d834e47958a6b08 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32214 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: David Guckian
2019-04-18mb/google/octopus: Set default configuration to low for gpio_178Wisley Chen
Set default configuration to low for gpio_178, and can remove the override setting for bobba/bloog/fleex/meep/phaser. For ampton, Change-Id I64a67f73564188ad0548a1a770169ef2bca47453 ( mb/google/ampton: Fix polarity of EN_PP3300_WLAN_L signal.) modified the pin setting. TEST=verified that boot into OS on meep board. suspend/resume, reboot, and no failure found. Change-Id: I7668ff4817edfca5c6cea63db779fcea21c7af92 Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32247 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-02-18mb/google/laser: Disable touch screen device that according to SKU IDpeichao.wang
We need disable touch screen device on laser SKU ID 6. BUG=none TEST=according to sku_id (Laser(convertible): 5, Laser14(clamshell): 6, Laser14(clamshell + touch):7) distinguish whether disable touch screen device. Signed-off-by: peichao.wang <peichao.wang@bitland.corp-partner.google.com> Change-Id: I6953c35a5e8c93d88fe63362156faa351e8ee71f Reviewed-on: https://review.coreboot.org/c/31428 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-27mb/google/octopus/var/phaser: Deprecate board id 0Furquan Shaikh
This change gets rid of bid0_override_table as part of clean up effort to deprecate bid0. Additionally, it updates the touchscreen enable GPIO in overridetree and gets rid of code in variant.c to update enable gpio at runtime. BUG=b:119885949 Change-Id: I527973747e7d81ec47997da57eeb15f38d3ac2fd Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/29787 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2018-11-27mb/google/octopus: Update GPIO_178 in early_gpio_table in baseboardFurquan Shaikh
This change updates the configuration of GPIO_178 to be active low as per latest revision on different octopus variants. This effectively: 1. Gets rid of early_gpio_table in different variants -- phaser, meep, fleex, bobba. 2. Deprecates board id < 2 for bobba, board id < 1 for fleex and phaser. 3. Adds special early_gpio_table in yorp which has GPIO_178 as an active high signal. BUG=b:119885949 Change-Id: I024199a8f1f96db57f8fa60c4d265789cd3a0493 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/29784 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Justin TerAvest <teravest@chromium.org>
2018-09-28src/*: normalize Google copyright headersPatrick Georgi
As per internal discussion, there's no "ChromiumOS Authors" that's meaningful outside the Chromium OS project, so change everything to the contemporary "Google LLC." While at it, also ensure consistency in the LLC variants (exactly one trailing period). "Google Inc" does not need to be touched, so leave them alone. Change-Id: Ia0780e31cdab879d2aaef62a2f0403e3db0a4ac8 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/28756 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Joel Kitching <kitching@google.com>
2018-09-26mb/google/octopus: Close unused I2C bus 7 include SCL and SDA for PhaserPeichao Wang
Since I2C bus 7 attached the touchscreen device however Phaser units that haven't it. So for avoiding side effects, we need close I2C bus 7 SCL and SDA respectively. BUG=none TEST=according to sku_id (Phaser: 0x1, Phaser360: 0x2, Phaser360s: 0x3) distinguish whether close these gpios. Change-Id: I8ad17761f2a053dc329bbec0a0a3284d47289666 Signed-off-by: Peichao.Wang <peichao.wang@bitland.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/28669 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Jett Rink <jettrink@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-06mb/google/octopus: Configure H1 interrupt pad using Rx level configFurquan Shaikh
This change configures GPIO_63 (which is used for H1 interrupts) as Rx Level. This ensures that the signal gets passed on to the next logic state as is and the APIC entry can be configured to trigger interrupt on level or edge as per the kernel driver expectation. TEST=Verified that no H1 interrupt timeouts are seen with 100 iterations of warm and 100 iterations of cold reboot. Change-Id: I7aac30300a4251d9b40276dcca7ebc6a6d814c40 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/28507 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-08-30mb/google/octopus: Add missing IOstandy settings.Shamile Khan
Also removed internal pull ups for CX_PREQ_L and CX_PREQ_L signals as they have external pull ups. BUG=b:110654510 TEST=On Yorp Proto 2, flashed image and verified that it boots to OS. Checked Wake-on-Wifi works with both cnvi and pcie modules. Also executed a few suspend resume cycles. Change-Id: I0a76cd2a1481c828fc092aaf7e870a411624879c Signed-off-by: Shamile Khan <shamile.khan@intel.com> Reviewed-on: https://review.coreboot.org/28328 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-26mb/google/octopus/variants/phaser: Provide override GPIO configFurquan Shaikh
This change provides override GPIO table for variant phaser depending upon the board id. Additionally, early_gpio_table is also provided for phaser since EN_PP3300_WLAN needs to be handled differently based on board id. BUG=b:111743717 TEST=Verified that GPIO configuration for the override GPIOs is different than before with this change. Change-Id: I4d2e829e1b886299442c17cecc069854b742b43c Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/27642 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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