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Enable the EC_AP_INT_ODL interrupt on GPIO_134 for all octopus boards
that support it. Also removing unnecessary IO standby support since we
don't use this pin to wake up the SoC.
BRANCH=octopus
BUG=b:122552125,b:120679547
TEST=CTS tests with changes
Change-Id: I018864ae5fa400372b5b443e49828e8202b9aa4d
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://review.coreboot.org/c/30788
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This change updates the configuration of GPIO_178 to be active low as
per latest revision on different octopus variants. This effectively:
1. Gets rid of early_gpio_table in different variants -- phaser, meep,
fleex, bobba.
2. Deprecates board id < 2 for bobba, board id < 1 for fleex and
phaser.
3. Adds special early_gpio_table in yorp which has GPIO_178 as an
active high signal.
BUG=b:119885949
Change-Id: I024199a8f1f96db57f8fa60c4d265789cd3a0493
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/29784
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
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As per internal discussion, there's no "ChromiumOS Authors" that's
meaningful outside the Chromium OS project, so change everything to the
contemporary "Google LLC."
While at it, also ensure consistency in the LLC variants (exactly one
trailing period).
"Google Inc" does not need to be touched, so leave them alone.
Change-Id: Ia0780e31cdab879d2aaef62a2f0403e3db0a4ac8
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/28756
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Joel Kitching <kitching@google.com>
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This change configures GPIO_63 (which is used for H1 interrupts) as Rx
Level. This ensures that the signal gets passed on to the next logic
state as is and the APIC entry can be configured to trigger interrupt
on level or edge as per the kernel driver expectation.
TEST=Verified that no H1 interrupt timeouts are seen with 100
iterations of warm and 100 iterations of cold reboot.
Change-Id: I7aac30300a4251d9b40276dcca7ebc6a6d814c40
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/28507
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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The change updates GPIO configuration for meep.
1. Update touchscreen power enable GPIO in devicetree.
2. Provide default override tables for GPIO configuration.
BUG=b:112955087
TEST=Boot on meep proto board with Intel (Jefferson Peak) wifi card.
Change-Id: Idb4e7a510eef15c2e118058d5848080782f4f665
Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Reviewed-on: https://review.coreboot.org/28252
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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