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path: root/src/mainboard/google/oak/gpio.h
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2018-07-20mediatek: Share GPIO code among similar SOCsTristan Shieh
Refactor GPIO code which will be reused among similar SOCs. BUG=b:80501386 BRANCH=none TEST=Boots correctly on Elm Change-Id: Icdd1f2a1dd1bd64a7218bf9c63bd4a0af1acbcc0 Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com> Reviewed-on: https://review.coreboot.org/27416 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2017-06-19google/oak: gpio: update RAM ID pins for RowanYidi Lin
RAMD_ID_1 moves to PAD_DSI_TE and RAM_ID_2 moves to PAD_RDP1_A on Rowan. BUG=chrome-os-partner:62672 BRANCH=none TEST=emerge-rowan coreboot Change-Id: Iae44934d8d669d696b83f9d3e3450a0e408fe062 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Gerrit-Rebase-Ignore-CLs-Before: https://chromium-review.googlesource.com/539234 Ignore-CL-Reviewed-on: https://chromium-review.googlesource.com/388068 Ignore-CL-Reviewed-on: https://chromium-review.googlesource.com/453778 Ignore-CL-Reviewed-on: https://chromium-review.googlesource.com/454921 Ignore-CL-Reviewed-on: https://chromium-review.googlesource.com/455118 Ignore-CL-Reviewed-on: https://chromium-review.googlesource.com/479613 Ignore-CL-Reviewed-on: https://chromium-review.googlesource.com/487023 Ignore-CL-Reviewed-on: https://chromium-review.googlesource.com/498587 Ignore-CL-Reviewed-on: https://chromium-review.googlesource.com/506785 Ignore-CL-Reviewed-on: https://chromium-review.googlesource.com/520572 Original-Commit-Id: 4da19b3c00578f96ec933cff9ad0c9988a4c4a30 Original-Change-Id: I64fd29de607a0b360d355fd3724e3a649adc658b Original-Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/448397 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/18583 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2017-04-24google/oak: Support cr50 over I2C on rowanVadim Bendebury
This patch enables TPM2 using cr50 over I2C for the Rowan board, and adds an mt8173 specific TPM IRQ polling function. The function relies on the appropriate EINT input configured to trigger the ready status on the rising edge. The cr50 TPM is on I2C address 0x50. The cr50 interrupt GPIO is also made available for use by depthcharge via the coreboot tables. BRANCH=none BUG=b:36786804 TEST=Boot rowan w/ serial enabled, verify coreboot and depthcharge are configured to use IRQ flow control when talking to the Cr50 TPM. Change-Id: If6cdd0e39e4ac86538f27f322c55c329179ee084 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Signed-off-by: Daniel Kurtz <djkurtz@chromium.org> Reviewed-on: https://review.coreboot.org/19364 Tested-by: build bot (Jenkins) Reviewed-by: Julius Werner <jwerner@chromium.org>
2017-02-23google/oak: Add initial support for RowanYidi Lin
Update GPIO controls and mainboard configurations for Rowan. [pg: use the opportunity to clean-up the gerrit-rebase task list with the entirely unrelated Ignore-CL-Reviewed-on lines] BUG=chrome-os-partner:62672 BRANCH=none TEST=emerge-rowan coreboot Change-Id: I110fb368b3d9fa9dfb2bf091342dfb511ff7c09c Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: f4252cbe94a7456108aaa522e170bca5dcb1fdd1 Original-Change-Id: I18ebc3ccf4c7d051839d7c50e9b0682ef8f09830 Original-Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/430557 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Ignore-CL-Reviewed-on: https://chromium-review.googlesource.com/341513 Ignore-CL-Reviewed-on: https://chromium-review.googlesource.com/327003 Ignore-CL-Reviewed-on: https://chromium-review.googlesource.com/355221 Ignore-CL-Reviewed-on: https://chromium-review.googlesource.com/354670 Ignore-CL-Reviewed-on: https://chromium-review.googlesource.com/361360 Ignore-CL-Reviewed-on: https://chromium-review.googlesource.com/361361 Ignore-CL-Reviewed-on: https://chromium-review.googlesource.com/361362 Ignore-CL-Reviewed-on: https://chromium-review.googlesource.com/361363 Ignore-CL-Reviewed-on: https://chromium-review.googlesource.com/382320 Ignore-CL-Reviewed-on: https://chromium-review.googlesource.com/405110 Ignore-CL-Reviewed-on: https://chromium-review.googlesource.com/405130 Ignore-CL-Reviewed-on: https://chromium-review.googlesource.com/419795 Ignore-CL-Reviewed-on: https://chromium-review.googlesource.com/424139 Ignore-CL-Reviewed-on: https://chromium-review.googlesource.com/430293 Ignore-CL-Reviewed-on: https://chromium-review.googlesource.com/430294 Ignore-CL-Reviewed-on: https://chromium-review.googlesource.com/430295 Ignore-CL-Reviewed-on: https://chromium-review.googlesource.com/427820 Ignore-CL-Reviewed-on: https://chromium-review.googlesource.com/427821 Ignore-CL-Reviewed-on: https://chromium-review.googlesource.com/427822 Reviewed-on: https://review.coreboot.org/18463 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-05-09google/oak: elm: Update the differences between oak-rev6 and elm-rev0Yidi Lin
- Remove the deprecated revison settings. - Change LID pin to SPI_CK. - Add i2c bus number and i2c slave address for elm. - Skip the pin configurations(ALC5514 and USB OC pins) belonging to Oak. - Add Hynix 4GB DRAM config BRANCH=none BUG=chrome-os-partner:51725 TEST=boot to kernel on elm-rev0 Change-Id: Ifaedd115c84d095ee289b576ff76af6b0aa3e545 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 2ed4543cdc7e84a0463b73dda96027270ec30272 Original-Change-Id: Id957374d7a67b8c72df1d07a6cecc1064d4e0356 Original-Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/332733 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/14692 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-01-13tree: drop last paragraph of GPL copyright header from new filesMartin Roth
This continues what was done in commit a73b93157f2 (tree: drop last paragraph of GPL copyright header) Change-Id: Ifb8d2d13f7787657445817bdde8dc15df375e173 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12914 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-03google/oak: Add board_id() and ram_code() implementationCC Ma
BRANCH=none BUG=none TEST=Oak build pass Change-Id: Ic2fd9b2ec0592d1f7195d72c60dab15961de0a9e Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 4d0b00a779b87b0b625cc2bccd8f7470b79e6410 Original-Change-Id: Id9f17d64e9e30946817b86ec8cdfe67ea3dbc798 Original-Signed-off-by: CC Ma <cc.ma@mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/292675 Original-Commit-Ready: Yidi Lin <yidi.lin@mediatek.com> Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/12607 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-03google/oak: Implement the code which reads GPIOs for ChromeOS.Yidi Lin
BUG=none BRANCH=none TEST=emerge-oak corebootk Change-Id: Ic1a0d640cac7fd98acd06d619736303fa449c0a1 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: ce465e8cbdf6465c072e476a91a400d78c959218 Original-Change-Id: Iade51db02f45264fdffe387e0563b60e637c0710 Original-Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/292674 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/12606 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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