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path: root/src/mainboard/google/nyan_big
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2014-11-13nyan*: Switching unused pin to GPIONeil Chen
Switching unused pin to GPIO to avoid SPI1 conflicting. BUG=chrome-os-partner:26701 BRANCH=none TEST=Built and boot on Nyan Original-Change-Id: I7de5b8d015f6d02baadd41b1b272dfc49d17c376 Original-Signed-off-by: Neil Chen <neilc@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/189970 Original-Reviewed-by: Gabe Black <gabeblack@chromium.org> (cherry picked from commit edf12f441adb2395fe2718bed98d79eb3b128f6b) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I562b58ba02825b16d374d9f0328f6c75431edc63 Reviewed-on: http://review.coreboot.org/7420 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2014-11-13nyan: big: Only delay when and as long as necessary in the PMIC setup code.Gabe Black
The PMIC setup code was unconditionally waiting for 10ms after each register write. It might be possible for there to be an excess of current from lots of rails switching around at the same time, but we can avoid that with a much shorter delay in a few strategic places. This change also moves the write to LDO3 to just under SD1 because LDO3 should track SD1. The duration and position for the delays and moving LDO3 were provided by Dan Coggin at nvidia. BUG=chrome-os-partner:25467 TEST=Built and booted on nyan rev1. Measured a 230 ms decrease in boot time. BRANCH=None Original-Change-Id: I14805bf1b6242bdd0b286f37ae7d635c03909677 Original-Signed-off-by: Gabe Black <gabeblack@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/189016 Original-Tested-by: Gabe Black <gabeblack@chromium.org> Original-Reviewed-by: Gabe Black <gabeblack@chromium.org> Original-Reviewed-by: Daniel Coggin <dcoggin@nvidia.com> Original-Commit-Queue: Gabe Black <gabeblack@chromium.org> (cherry picked from commit 06c4d346deeb47809cd88655a9fa6712ceef9491) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I3ce0bdeb4ee60499f6c192fe0803a4cab3d7a8af Reviewed-on: http://review.coreboot.org/7419 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2014-11-13nyan: big: Set the i2c controller frequencies appropriately.Gabe Black
These had been set to something fairly random which results in a very slow clock on the bus itself. The new settings take into consideration the speed the devices on the bus can run at. The TPM can't seem to handle speeds above 40KHz, but some documentation suggests that it should be able to handle up to at least 100KHz. BUG=chrome-os-partner:25467 TEST=Built and booted on nyan rev1. Built for big. BRANCH=None Original-Change-Id: Iee98957c7e492c7dd08b071aeef3cce75c4a9e56 Original-Signed-off-by: Gabe Black <gabeblack@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/189015 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Original-Tested-by: Gabe Black <gabeblack@chromium.org> Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Original-Commit-Queue: Gabe Black <gabeblack@chromium.org> (cherry picked from commit afca97a29aeb99d3899b713d0e57a3b3214f0d96) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Iab0c50b2119ac322252564354c90b5cb2d255c97 Reviewed-on: http://review.coreboot.org/7418 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2014-11-13Nyan: Set DMA Reserve to 2MBDaisuke Nojiri
When using LPAE, the address space is split to 2MB blocks. This change makes the space reserved for DMA consistent with the block size. TEST=Booted nyan with and without LPAE. Built nyan_big. BUG=None BRANCH=None Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Tested-by: Daisuke Nojiri <dnojiri@chromium.org> Original-Change-Id: I75c77484f6ca9f23b583ef651956d0265a9b4474 Original-Reviewed-on: https://chromium-review.googlesource.com/188571 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Original-Commit-Queue: Daisuke Nojiri <dnojiri@chromium.org> Original-Tested-by: Daisuke Nojiri <dnojiri@chromium.org> (cherry picked from commit 16a40a48c2e3fc131a348d5e7d377d26f4b20aaf) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Ib79c9491dc504d28f811bbf0d91cffd292f5eb86 Reviewed-on: http://review.coreboot.org/7413 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2014-11-13nyan: Select the CD570M Tegra124 model.Gabe Black
This indirectly selects an appropriate PLLX frequency so the main CPUs run as fast as they can but not faster. BUG=chrome-os-partner:25467 TEST=Booted on nyan rev1. BRANCH=None Original-Change-Id: Ibe61f5e35246b272771debf4fdf90c79b21eb5d0 Original-Signed-off-by: Gabe Black <gabeblack@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/188603 Original-Commit-Queue: Gabe Black <gabeblack@chromium.org> Original-Tested-by: Gabe Black <gabeblack@chromium.org> Original-Reviewed-by: Gabe Black <gabeblack@chromium.org> (cherry picked from commit 947ecbce3cb6e4d7ab07d3ffd5b4694ca6270cde) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I9163ddea7f246ae7207a8a715ebae2c9627a7e37 Reviewed-on: http://review.coreboot.org/7410 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2014-11-13nyan: nyan_big: Mark the address range covering the SRAM as cachable.Gabe Black
The SRAM is very likely faster than going all the way out to DRAM for data, but I don't think it's part of the cores themselves and won't be as fast as the L1 caches. Enabling caching for this region reduces the time it takes to get to the payload by about 75% when serial output is disabled and the main part of display init is commented out. BUG=chrome-os-partner:25467 TEST=Built and booted on nyan. BRANCH=None Original-Change-Id: I7ff26dea9d50e7d9a76e598e5654488481286b35 Original-Signed-off-by: Gabe Black <gabeblack@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/188459 Original-Reviewed-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-by: Hung-Te Lin <hungte@chromium.org> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Original-Tested-by: Gabe Black <gabeblack@chromium.org> Original-Commit-Queue: Gabe Black <gabeblack@chromium.org> (cherry picked from commit ac8b9b30490d511ca1b207af6845d50e08ac130f) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: If79dcd1b116f30b778788ba4fd45d362ff5d8e6e Reviewed-on: http://review.coreboot.org/7407 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2014-11-13nyan: big: Check dram_end when setting up caching in ROM stage.Gabe Black
When setting up caching on nyan and big, we would set the region after DRAM to the end of the address space as uncachable. DRAM may actually extend beyond the end of the address space, so that may result in address aliasing or other problems. This change adds a check to make sure there's actually space there. BUG=None TEST=Built for big. BRANCH=None Original-Change-Id: Ic0a98550222f9dfc0aeafd67a2dd1c0c8f4ece44 Original-Signed-off-by: Gabe Black <gabeblack@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/186769 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Original-Commit-Queue: Gabe Black <gabeblack@chromium.org> Original-Tested-by: Gabe Black <gabeblack@chromium.org> (cherry picked from commit 1866a4d2a001beb97779b611b8b69c63175048f4) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: If1ca8b5bd4efab8962e03c0d9eaa70c0327ea6b5 Reviewed-on: http://review.coreboot.org/7405 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2014-11-12tegra124: Program PWM1 to drive panel backlightAndrew Chew
Repurpose config->pwm to mean the particular PWM device (we use PWM1 on nyan), and add code to program the PWM device. BUG=none TEST=emerge-nyan chromeos-coreboot-nyan, regenerate bootimage, and boot. See that the backlight comes up in the bootloader, and brightness can be adjusted via pwm_bl driver in the kernel. Original-Change-Id: I2db047e5ef23c0e8fb66dd05ad6339d60918d493 Original-Signed-off-by: Andrew Chew <achew@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/185772 Original-Reviewed-by: Andrew Bresticker <abrestic@chromium.org> (cherry picked from commit 0dee98dd0c8510ecd630b5c6cb9ea49724dc8b55) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Ie53610f3afa30b2d8f484685fb0e8c0b12cd8241 Reviewed-on: http://review.coreboot.org/7402 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-11-12tegra124: Port a PWM clocking change to big.Gabe Black
The generic tegra124 code will use one of the PWMs to drive the backlight of the display, but the PWM clock was enabled only for nyan. This change enables it for big as well. BUG=none TEST=Built for Big BRANCH=None Original-Change-Id: I5171da7c41f4b4db931563ada3e8e4ebf74ec3d9 Original-Signed-off-by: Gabe Black <gabeblack@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/186767 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Original-Commit-Queue: Gabe Black <gabeblack@chromium.org> Original-Tested-by: Gabe Black <gabeblack@chromium.org> (cherry picked from commit 687f3771fb3e6b340a818fa7594b3ac0630fdeaf) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Ifd14a22a98e7fe273ec28c460b928b8a83c84b66 Reviewed-on: http://review.coreboot.org/7404 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-11-12tegra124: nyan: Keep in memory structures below 4GB.Gabe Black
We'd been putting some data structures like the framebuffer and the cbmem at the end of memory, but that may not actually be addressable as identity mapped memory. This change clamps the addresses those structures are placed at so they stay below 4GB. BUG=None TEST=Booted on nyan. Went into recovery mode and verified that there was a recovery screen. Forced memory size to be 4GB and verified that the recovery screen still shows up. BRANCH=None Original-Change-Id: I9e6b28212c113107d4f480b3dd846dd2349b3a91 Original-Signed-off-by: Gabe Black <gabeblack@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/185571 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Original-Commit-Queue: Gabe Black <gabeblack@chromium.org> Original-Tested-by: Gabe Black <gabeblack@chromium.org> (cherry picked from commit 63ea1274a838dc739d302d7551f1db42034c5bd0) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I970c1285270cb648bc67fa114d44c0841eab1615 Reviewed-on: http://review.coreboot.org/7397 Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Tested-by: build bot (Jenkins)
2014-11-12nyan: Use asm volatile instead of plain asm so it doesn't get optimized out.Gabe Black
If an asm blob isn't marked as volatile, gcc is free to throw it out if it doesn't think it produces any values that are actually used. To prevent that from happening, add volatile to some asm blobs in the nyan romstage code. BUG=None TEST=Booted on nyan rev1. BRANCH=None Original-Change-Id: I819e068e738e94ea749fcb72bba2eee080e1dfb1 Original-Signed-off-by: Gabe Black <gabeblack@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/185610 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Original-Commit-Queue: Gabe Black <gabeblack@chromium.org> Original-Tested-by: Gabe Black <gabeblack@chromium.org> (cherry picked from commit 76c09581d6ca4dc6c2f9048f599822939f439d11) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I0b32197abf0ddc5f454f9c2415a65d98c60ca48b Reviewed-on: http://review.coreboot.org/7396 Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins)
2014-11-10arm: Redesign, clarify and clean up cache related codeJulius Werner
This patch changes several cache-related pieces to be cleaner, faster or more correct. The largest point is removing the old arm_invalidate_caches() function and surrounding bootblock code to initialize SCTLR and replace it with an all-assembly function that takes care of cache and SCTLR initialization to bring the system to a known state. It runs without stack and before coreboot makes any write accesses to be as compatible as possible with whatever state the system was left in by preceeding code. This also finally fixes the dreaded icache bug that wasted hundreds of milliseconds during boot. Old-Change-Id: I7bb4995af8184f6383f8e3b1b870b0662bde8bd4 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/183890 (cherry picked from commit 07a35925dc957919bf88dfc90515971a36e81b97) nyan_big: apply cache-related changes from nyan This applies the same changes from 07a3592 that were applied to nyan. Old-Change-Id: Idcbe85436d7a2f65fcd751954012eb5f4bec0b6c Reviewed-on: https://chromium-review.googlesource.com/184551 Commit-Queue: David Hendricks <dhendrix@chromium.org> Tested-by: David Hendricks <dhendrix@chromium.org> Reviewed-by: David Hendricks <dhendrix@chromium.org> (cherry picked from commit 4af27f02614da41c611aee2c6d175b1b948428ea) Squashed the followup patch for nyan_big into the original patch. Change-Id: Id14aef7846355ea2da496e55da227b635aca409e Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> (cherry picked from commit 4cbf25f8eca3a12bbfec5b015953c0fc2b69c877) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/6993 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-10-22tegra/nyan*: sdram updatesTom Warren
nyan_big: Add 204MHz BCT for bringup, use 1.2V for VDD_CPU Reviewed-on: https://chromium-review.googlesource.com/183939 (cherry picked from commit a6df76afb5342b805baca749abb8265e15748dc1) nyan_big: Add initial 792MHz BCT Reviewed-on: https://chromium-review.googlesource.com/183975 (cherry picked from commit 61d0122fdce6dc9479666bb0a5bc079c6389f78a) nyan_big: use RAM_CODE[3:2] for ram code Reviewed-on: https://chromium-review.googlesource.com/184076 (cherry picked from commit 35e5c5e473f871cdc897473a31586afbececd716) tegra124: support tri-state Board Id Reviewed-on: https://chromium-review.googlesource.com/183855 (cherry picked from commit 1a9d1bd73aa2cd0c36203b247976ad0d00a360e4) nyan*: Fix SPI pinmux configuration Reviewed-on: https://chromium-review.googlesource.com/184281 (cherry picked from commit ac4106b673c285af66d72392bd4a8522aba98489) nyan_big: Add 4GB 204/792MHz BCTs Reviewed-on: https://chromium-review.googlesource.com/184159 (cherry picked from commit 5ff002d09f8db0543b58962f6c0d24627fb0937e) tegra124: Add function for obtaining DRAM size via MC regs Reviewed-on: https://chromium-review.googlesource.com/184535 (cherry picked from commit d4580c46de649903a266a99eb11c9126ba385b48) tegra124/nyan*: Obtain DRAM size dynamically Reviewed-on: https://chromium-review.googlesource.com/184431 (cherry picked from commit a7db71744771decc04cf1966efba70bf4897cfa3) tegra124: Rearrange iRAM layout to allow more space for romstage Reviewed-on: https://chromium-review.googlesource.com/184240 (cherry picked from commit 6bdaabbc068146a4516c724b71d31bb777dabcfc) tegra124: Fix MemoryType field name in SDRAM parameters. Reviewed-on: https://chromium-review.googlesource.com/185113 (cherry picked from commit 9caccd1e86a8c683402fab87d9f3a49b87496e97) nyan_big: Initialize SDRAM without BootROM. Reviewed-on: https://chromium-review.googlesource.com/183624 (cherry picked from commit a1cbc00aa80ec1ea52e833a8e31c8e4b27160e70) tegra124: move FB_SIZE_MB to a more appropriate location Reviewed-on: https://chromium-review.googlesource.com/184930 (cherry picked from commit ddea486fd4410394417c4e59039d46a324918bdc) nyan: Initialize SDRAM without BootROM. Reviewed-on: https://chromium-review.googlesource.com/185114 (cherry picked from commit 1ff51b580b28553919f91b11b443251b048cf26b) tegra124: Save SDRAM parameters to PMC registers for LP0 Reviewed-on: https://chromium-review.googlesource.com/182928 (cherry picked from commit 7476b4bd0ecdc312476cce871d22f57915a0bd86) tegra124: Rewrite SDRAM parameter saving code to be more efficient Reviewed-on: https://chromium-review.googlesource.com/184388 (cherry picked from commit 25084bd0407624e4b2ff82388c32af1198c501a6) nyan: Slightly change the way SDRAM parameter files are set up Reviewed-on: https://chromium-review.googlesource.com/185286 (cherry picked from commit a31887b804f23e031c395113db582cd71f3d1b6d) Squashed 16 commits for SDRAM support on nyan and nyan_big. Change-Id: I07419985376277083d62400dd14fe8273f6d5ca8 Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6949 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-10-17Add board_info for all Google/Intel boards mitting the fileStefan Reinauer
Change-Id: Iac53462ab3621d96ba15e2fde2800212584246db Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/7072 Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins)
2014-09-24big: Create a nyan_big mainboard which is a copy of nyan.Gabe Black
The nyan_big mainboard is very similar to nyan, but will be different in a few ways. For instance, the BCT will be different, and the GPIOs may need to be configured slightly differently. This change also adds prefixes to the kconfig variables in "choice" blocks for both boards since having multiple instances of choice blocks with the same options confuses kconfig even if all of the instances have mutually exclusive dependencies. Change-Id: I290a32e47fc118bd4b86d543df617ad324325dbc Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://chromium-review.googlesource.com/183532 Reviewed-by: Tom Warren <twarren@nvidia.com> Reviewed-by: David Hendricks <dhendrix@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> (cherry picked from commit d1a453fe1aa68b3d12936dd48cc6c94b54f81579) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6927 Tested-by: build bot (Jenkins)
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