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Change-Id: If68303cd59b287c8a5c982063b2ab75fd74898d6
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81477
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Jakub Czapiga <czapiga@google.com>
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Change-Id: Ibbdd589119bbccd3516737c8ee9f90c4bef17c1e
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58923
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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Little point to replicate a string already provided both
as a global Kconfig and global mainboard_part_number.
Change-Id: I1fd138c711ebbb37c39b2c8f554b1f2e1a364424
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50719
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: ron minnich <rminnich@gmail.com>
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Stefan thinks they don't add value.
Command used:
sed -i -e '/file is part of /d' $(git grep "file is part of " |egrep ":( */\*.*\*/\$|#|;#|-- | *\* )" | cut -d: -f1 |grep -v crossgcc |grep -v gcov | grep -v /elf.h |grep -v nvramtool)
The exceptions are for:
- crossgcc (patch file)
- gcov (imported from gcc)
- elf.h (imported from GNU's libc)
- nvramtool (more complicated header)
The removed lines are:
- fmt.Fprintln(f, "/* This file is part of the coreboot project. */")
-# This file is part of a set of unofficial pre-commit hooks available
-/* This file is part of coreboot */
-# This file is part of msrtool.
-/* This file is part of msrtool. */
- * This file is part of ncurses, designed to be appended after curses.h.in
-/* This file is part of pgtblgen. */
- * This file is part of the coreboot project.
- /* This file is part of the coreboot project. */
-# This file is part of the coreboot project.
-# This file is part of the coreboot project.
-## This file is part of the coreboot project.
--- This file is part of the coreboot project.
-/* This file is part of the coreboot project */
-/* This file is part of the coreboot project. */
-;## This file is part of the coreboot project.
-# This file is part of the coreboot project. It originated in the
- * This file is part of the coreinfo project.
-## This file is part of the coreinfo project.
- * This file is part of the depthcharge project.
-/* This file is part of the depthcharge project. */
-/* This file is part of the ectool project. */
- * This file is part of the GNU C Library.
- * This file is part of the libpayload project.
-## This file is part of the libpayload project.
-/* This file is part of the Linux kernel. */
-## This file is part of the superiotool project.
-/* This file is part of the superiotool project */
-/* This file is part of uio_usbdebug */
Change-Id: I82d872b3b337388c93d5f5bf704e9ee9e53ab3a9
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41194
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Done with sed and God Lines. Only done for C-like code for now.
Change-Id: Iea5f9af845fda3ffff303aed402edea8b9eb219a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40183
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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They're listed in AUTHORS and often incorrect anyway, for example:
- What's a "Copyright $year-present"?
- Which incarnation of Google (Inc, LLC, ...) is the current
copyright holder?
- People sometimes have their editor auto-add themselves to files even
though they only deleted stuff
- Or they let the editor automatically update the copyright year,
because why not?
- Who is the copyright holder "The coreboot project Authors"?
- Or "Generated Code"?
Sidestep all these issues by simply not putting these notices in
individual files, let's list all copyright holders in AUTHORS instead
and use the git history to deal with the rest.
Change-Id: I09cc279b1f75952bb397de2c3f2b299255163685
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39607
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
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This patch changes all existing instances of clrsetbits_leXX() to the
new endian-independent clrsetbitsXX(), after double-checking that
they're all in SoC-specific code operating on CPU registers and not
actually trying to make an endian conversion.
This patch was created by running
sed -i -e 's/\([cs][le][rt]bits\)_le\([136][624]\)/\1\2/g'
across the codebase and cleaning up formatting a bit.
Change-Id: I7fc3e736e5fe927da8960fdcd2aae607b62b5ff4
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37433
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
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Change-Id: I901cb35488e08f58cdf97f3a8d0f5a8d03560f86
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33729
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Also adapt all users of these symbols
Change-Id: Ibf924a283d438de49a93ce661b0d9ca1a81cd6d1
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32956
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
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MMIO operations are arch-agnostic so the include
path should not be arch/.
Change-Id: I0fd70f5aeca02e98e96b980c3aca0819f5c44b98
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/31691
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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When <symbols.h> was first introduced, it only declared a handful of
regions and we didn't expect that too many architectures and platforms
would need to add their own later. However, our amount of platforms has
greatly expanded since, and with them the need for more special memory
regions. The amount of code duplication is starting to get unsightly,
and platforms keep defining their own <soc/symbols.h> files that need
this as well.
This patch adds another macro to cut down the definition boilerplate.
Unfortunately, macros cannot define other macros when they're called, so
referring to region sizes as _name_size doesn't work anymore. This patch
replaces the scheme with REGION_SIZE(name).
Not touching the regions in the x86-specific <arch/symbols.h> yet since
they don't follow the standard _region/_eregion naming scheme. They can
be converted later if desired.
Change-Id: I44727d77d1de75882c72a94f29bd7e2c27741dd8
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/31539
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Use of device_t has been abandoned in ramstage.
Change-Id: I8e549e4222ae2ed6b9c46f81c5b5253e8b227ee8
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26086
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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1. Currenty, boot reason is being added to elog only for some
ARM32/ARM64 platforms. Change this so that boot reason is logged by
default in elog for all devices which have CHROMEOS selected.
2. Add a new option to select ELOG_WATCHDOG_RESET for the devices that
want to add details about watchdog reset in elog. This requires a
special region WATCHDOG to be present in the memlayout.
3. Remove calls to elog add boot reason and watchdog reset from
mainboards.
BUG=chrome-os-partner:55639
Change-Id: I91ff5b158cfd2a0749e7fefc498d8659f7e6aa91
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15897
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
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It encourages users from writing to the FSF without giving an address.
Linux also prefers to drop that and their checkpatch.pl (that we
imported) looks out for that.
This is the result of util/scripts/no-fsf-addresses.sh with no further
editing.
Change-Id: Ie96faea295fe001911d77dbc51e9a6789558fbd6
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/11888
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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As per discussion with lawyers[tm], it's not a good idea to
shorten the license header too much - not for legal reasons
but because there are tools that look for them, and giving
them a standard pattern simplifies things.
However, we got confirmation that we don't have to update
every file ever added to coreboot whenever the FSF gets a
new lease, but can drop the address instead.
util/kconfig is excluded because that's imported code that
we may want to synchronize every now and then.
$ find * -type f -exec sed -i "s:Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, *MA[, ]*02110-1301[, ]*USA:Foundation, Inc.:" {} +
$ find * -type f -exec sed -i "s:Foundation, Inc., 51 Franklin Street, Suite 500, Boston, MA 02110-1335, USA:Foundation, Inc.:" {} +
$ find * -type f -exec sed -i "s:Foundation, Inc., 59 Temple Place[-, ]*Suite 330, Boston, MA *02111-1307[, ]*USA:Foundation, Inc.:" {} +
$ find * -type f -exec sed -i "s:Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.:Foundation, Inc.:" {} +
$ find * -type f
-a \! -name \*.patch \
-a \! -name \*_shipped \
-a \! -name LICENSE_GPL \
-a \! -name LGPL.txt \
-a \! -name COPYING \
-a \! -name DISCLAIMER \
-exec sed -i "/Foundation, Inc./ N;s:Foundation, Inc.* USA\.* *:Foundation, Inc. :;s:Foundation, Inc. $:Foundation, Inc.:" {} +
Change-Id: Icc968a5a5f3a5df8d32b940f9cdb35350654bef9
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/9233
Tested-by: build bot (Jenkins)
Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
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This patch is a raw application of the following spatch to src/:
@@
expression A, V;
@@
- writel(V, A)
+ write32(A, V)
@@
expression A, V;
@@
- writew(V, A)
+ write16(A, V)
@@
expression A, V;
@@
- writeb(V, A)
+ write8(A, V)
@@
expression A;
@@
- readl(A)
+ read32(A)
@@
expression A;
@@
- readb(A)
+ read8(A)
BRANCH=none
BUG=chromium:444723
TEST=None (depends on next patch)
Change-Id: I5dd96490c85ee2bcbc669f08bc6fff0ecc0f9e27
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 64f643da95d85954c4d4ea91c34a5c69b9b08eb6
Original-Change-Id: I366a2eb5b3a0df2279ebcce572fe814894791c42
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/254864
Reviewed-on: http://review.coreboot.org/9836
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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We've had gpiolib.h which defines a few common GPIO access functions for
a while, but it wasn't really complete. This patch adds the missing
gpio_output() function, and also renames the unwieldy
gpio_get_in_value() and gpio_set_out_value() to the much easier to
handle gpio_get() and gpio_set(). The header is renamed to the simpler
gpio.h while we're at it (there was never really anything "lib" about
it, and it was presumably just chosen due to the IPQ806x include/
conflict problem that is now resolved).
It also moves the definition of gpio_t into SoC-specific code, so that
different implementations are free to encode their platform-specific
GPIO parameters in those 4 bytes in the most convenient way (such as the
rk3288 with a bitfield struct). Every SoC intending to use this common
API should supply a <soc/gpio.h> that typedefs gpio_t to a type at most
4 bytes in length. Files accessing the API only need to include <gpio.h>
which may pull in additional things (like a gpio_t creation macro) from
<soc/gpio.h> on its own.
For now the API is still only used on non-x86 SoCs. Whether it makes
sense to expand it to x86 as well should be separately evaluated at a
later point (by someone who understands those systems better). Also,
Exynos retains its old, incompatible GPIO API even though it would be a
prime candidate, because it's currently just not worth the effort.
BUG=None
TEST=Compiled on Daisy, Peach_Pit, Nyan_Blaze, Rush_Ryu, Storm and
Veyron_Pinky.
Change-Id: Ieee77373c2bd13d07ece26fa7f8b08be324842fe
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 9e04902ada56b929e3829f2c3b4aeb618682096e
Original-Change-Id: I6c1e7d1e154d9b02288aabedb397e21e1aadfa15
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/220975
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9400
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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This patch aligns tegra124 to the new SoC header include scheme.
Also alphabetized headers in affected files since we touch them anyway.
BUG=None
TEST=Tested with whole series. Compiled Nyan, Nyan_Big and Nyan_Blaze.
Change-Id: Ia82ab86b2af903690cc6c9d310f7bdda3425ea7c
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 4d23774e071ec22781991ff20fbf63802f620c88
Original-Change-Id: Ia126cff8590117788d1872e50608c257d2659c1f
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/224504
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9326
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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This patch creates a new mechanism to define the static memory layout
(primarily in SRAM) for a given board, superseding the brittle mass of
Kconfigs that we were using before. The core part is a memlayout.ld file
in the mainboard directory (although boards are expected to just include
the SoC default in most cases), which is the primary linker script for
all stages (though not rmodules for now). It uses preprocessor macros
from <memlayout.h> to form a different valid linker script for all
stages while looking like a declarative, boilerplate-free map of memory
addresses to the programmer. Linker asserts will automatically guarantee
that the defined regions cannot overlap. Stages are defined with a
maximum size that will be enforced by the linker. The file serves to
both define and document the memory layout, so that the documentation
cannot go missing or out of date.
The mechanism is implemented for all boards in the ARM, ARM64 and MIPS
architectures, and should be extended onto all systems using SRAM in the
future. The CAR/XIP environment on x86 has very different requirements
and the layout is generally not as static, so it will stay like it is
and be unaffected by this patch (save for aligning some symbol names for
consistency and sharing the new common ramstage linker script include).
BUG=None
TEST=Booted normally and in recovery mode, checked suspend/resume and
the CBMEM console on Falco, Blaze (both normal and vboot2), Pinky and
Pit. Compiled Ryu, Storm and Urara, manually compared the disassemblies
with ToT and looked for red flags.
Change-Id: Ifd2276417f2036cbe9c056f17e42f051bcd20e81
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: f1e2028e7ebceeb2d71ff366150a37564595e614
Original-Change-Id: I005506add4e8fcdb74db6d5e6cb2d4cb1bd3cda5
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/213370
Reviewed-on: http://review.coreboot.org/9283
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Tauner <stefan.tauner@gmx.at>
Reviewed-by: Aaron Durbin <adurbin@google.com>
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Pull out the common usb setup utmip functions from t124 into tegra usb.h. These
can be reused for t132 as well.
BUG=chrome-os-partner:31293
BRANCH=None
TEST=Compiles successfully for nyan, big and blaze
Change-Id: Idddd40e409b56875436db6918d05f2889d83870b
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 12f12cb30a033cce645f53457d13a987aeec22a1
Original-Change-Id: I83f83bafad0f52ad651fe5989430f41142803f2b
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/211200
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/8927
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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The VDDIO to GEN2 I2C SCL/SDA pins is 1.8V and the external
pull-up voltage is 3.3V (the external 3.3V > I/O 1.8V) thus
the pinmux E_OD bit of these two pins needs to be set to
ensure GEN2 I2C pads work fine on 3.3V.
BRANCH=nyan
BUG=none
TEST=observed voltage drop from 3.3V to 2.36V on gen2 i2c
on blaze w/o this change. the waveform looks good on both
scl/sda pins w/ this change.
Original-Change-Id: I1b97f0c9c7580d1e532c3bdf7ac8690241ee7ee3
Original-Signed-off-by: Ken Chang <kenc@nvidia.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/200996
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
(cherry picked from commit 2db39166ec525e56a19746f38a867305a2687365)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I0c84eade89311baf0a6f180cb5cc9e2145f6b7ea
Reviewed-on: http://review.coreboot.org/7952
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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BUG=none
BRANCH=nyan
TEST=built and booted on Big under various modes, verified that
expected boot mode showed up using "mosys eventlog list"
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Original-Change-Id: I8d98487a2cb910874c8d741008ae59a6c89102e7
Original-Reviewed-on: https://chromium-review.googlesource.com/199691
Original-Commit-Queue: David Hendricks <dhendrix@chromium.org>
Original-Tested-by: David Hendricks <dhendrix@chromium.org>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
(cherry picked from commit 9f4b2574c1af23dcdc01706e9a118441f46a0f97)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: Ibbf264a1e05323dfddb7cdb270ee6f2d49e83eff
Reviewed-on: http://review.coreboot.org/7946
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Tested-by: build bot (Jenkins)
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When warm booting, SD card reader on Tegra 124 needs to be reset by setting
power GPIO to zero. Since we don't really access SD card in Coreboot, set it to
zero and let payloads enable power when they need to access SD cards.
CQ-DEPEND=CL:196783
BRANCH=nyan
BUG=chrome-os-partner:27053
TEST=emerge-nyan coreboot depthcharge chromeos-bootimage
# With related changes in depthcharge, boots SD card successfully.
Original-Change-Id: I2d368eb9480c978e9e343648b58a729028c94622
Original-Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/196774
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Original-Tested-by: Andrew Bresticker <abrestic@chromium.org>
(cherry picked from commit 62bb7d04dff1a87474a8557f144b24e6b7d006ae)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I3429535d0d032f9db89d8e70a525a6281102537a
Reviewed-on: http://review.coreboot.org/7865
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Enable pinmux clamp function to avoid pinmux conflict.
For pins which are configured to tristate enabled, the inputs to the
controller will be clamped to zero. This can be used to avoid pinmux
conflicts since the tristate bit is set to 1 in the power-on-reset
pinmux setting.
With pinmux clamp enabled, we need to configure all the input pins
to tristate disabled.
BUG=chrome-os-partner:27091
BRANCH=None
TEST=built and booted successfully, display worked fine.
Original-Change-Id: Id79a717f2025c812908c7152d439351208aee8d2
Original-Signed-off-by: Ken Chang <kenc@nvidia.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/194060
Original-Reviewed-by: Gabe Black <gabeblack@chromium.org>
(cherry picked from commit c95d6fe79810612cfad721667657cdcb87068d23)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I1b23df8b90f83ea2b2c08c4364d90fe71533a5a0
Reviewed-on: http://review.coreboot.org/7775
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
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This enables event logging support for Nyan platforms.
Right now this doesn't do a whole lot. We can add events in
later CLs.
BUG=none
BRANCH=none
TEST=built and booted for Nyan Rev. 1, eventlog gets initialized
if necessary and can be printed by "mosys eventlog list"
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Original-Change-Id: Id77a78f55c8bff9ef0ffc7109c8b03c270e8b6b1
Original-Reviewed-on: https://chromium-review.googlesource.com/191200
Original-Reviewed-by: Gabe Black <gabeblack@chromium.org>
Original-Tested-by: David Hendricks <dhendrix@chromium.org>
Original-Commit-Queue: David Hendricks <dhendrix@chromium.org>
(cherry picked from commit 1bb1a00863a63e53379b02f2b466d4d8ae3cef50)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I3a5d896d97dfc66ec37114bd3bac3f34e1c22bf7
Reviewed-on: http://review.coreboot.org/7774
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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The SPI drivers for tegra and exynos5420 have code in them which waits for a
frame header and leaves filler data out. The SPI driver shouldn't have support
for frame headers directly. If a device uses them, it should support them
itself. That makes the SPI drivers simpler and easier to write.
When moving the frame handling logic into the EC support code, EC communication
continued to work on tegra but no longer worked on exynos5420. That suggested
the SPI driver on the 5420 wasn't working correctly, so I replaced that with
the implementation in depthcharge. Unfortunately that implementation doesn't
support waiting for a frame header for the EC, so these changes are combined
into one.
BUG=None
TEST=Built and booted on pit. Built and booted on nyan. In both cases,
verified that there were no error messages from the SPI drivers or the EC
code.
BRANCH=None
Original-Change-Id: I62a68820c632f154acece94f54276ddcd1442c09
Original-Signed-off-by: Gabe Black <gabeblack@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/191192
Original-Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Original-Commit-Queue: Gabe Black <gabeblack@chromium.org>
Original-Tested-by: Gabe Black <gabeblack@chromium.org>
(cherry picked from commit 4fcfed280ad70f14a013d5353aa0bee0af540630)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: Id8824523abc7afcbc214845901628833e135d142
Reviewed-on: http://review.coreboot.org/7706
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <gaumless@gmail.com>
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This is required to send 1.5Mhz clock to Max98090 and get a right beep sound.
BUG=chrome-os-partner:26609
TEST=Booted Nyan. Verified Max98090 can beep. Measured frequency by smartphone.
BRANCH=none
Original-Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Original-Change-Id: Ie3ff6df6759cb23d78dc05069553ddb4eb8e508a
Original-Reviewed-on: https://chromium-review.googlesource.com/191791
Original-Reviewed-by: Hung-Te Lin <hungte@chromium.org>
(cherry picked from commit 2f75a147f26ac334fff174a1f9618a2bbe290fe9)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: If8c7871dc8202f98ccf23fb0afad1e7745fbf174
Reviewed-on: http://review.coreboot.org/7457
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
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To enable EFS, we need to be able to talk to the TPM and the EC before the RAM
stage starts. That means we need to set up the pins for those busses, clock
those controllers and take them out of reset.
BUG=None
TEST=Built for nyan, nyan_big, and nyan_blaze. Booted on nyan. With other
changes which implement EFS on nyan, saw EC and TPM communication work when in
vboot.
BRANCH=None
Original-Change-Id: Ic65d69fd42beec5f03084c8cb970927c2f69dfb6
Original-Signed-off-by: Gabe Black <gabeblack@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/191390
Original-Reviewed-by: Gabe Black <gabeblack@chromium.org>
Original-Commit-Queue: Gabe Black <gabeblack@chromium.org>
Original-Tested-by: Gabe Black <gabeblack@chromium.org>
(cherry picked from commit d9c176536b1e2eba47fdca90dd3346052573223e)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: Id3117bd0c36f8b92d85cc0cefde2bed9d8de90d0
Reviewed-on: http://review.coreboot.org/7456
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
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Switching unused pin to GPIO to avoid SPI1 conflicting.
BUG=chrome-os-partner:26701
BRANCH=none
TEST=Built and boot on Nyan
Original-Change-Id: I7de5b8d015f6d02baadd41b1b272dfc49d17c376
Original-Signed-off-by: Neil Chen <neilc@nvidia.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/189970
Original-Reviewed-by: Gabe Black <gabeblack@chromium.org>
(cherry picked from commit edf12f441adb2395fe2718bed98d79eb3b128f6b)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I562b58ba02825b16d374d9f0328f6c75431edc63
Reviewed-on: http://review.coreboot.org/7420
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
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These had been set to something fairly random which results in a very slow
clock on the bus itself. The new settings take into consideration the speed
the devices on the bus can run at. The TPM can't seem to handle speeds above
40KHz, but some documentation suggests that it should be able to handle up to
at least 100KHz.
BUG=chrome-os-partner:25467
TEST=Built and booted on nyan rev1. Built for big.
BRANCH=None
Original-Change-Id: Iee98957c7e492c7dd08b071aeef3cce75c4a9e56
Original-Signed-off-by: Gabe Black <gabeblack@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/189015
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Original-Tested-by: Gabe Black <gabeblack@chromium.org>
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Original-Commit-Queue: Gabe Black <gabeblack@chromium.org>
(cherry picked from commit afca97a29aeb99d3899b713d0e57a3b3214f0d96)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: Iab0c50b2119ac322252564354c90b5cb2d255c97
Reviewed-on: http://review.coreboot.org/7418
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
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Configure pin H1 for PWM1, and enable the PWM clock.
BUG=none
TEST=emerge-nyan chromeos-coreboot-nyan
Original-Change-Id: I2f91ebd4666bd227686c08cedf3c1aa7abbe8215
Original-Signed-off-by: Andrew Chew <achew@nvidia.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/185770
Original-Reviewed-by: Andrew Bresticker <abrestic@chromium.org>
(cherry picked from commit 069636d9299f64dd64466d45d2297593b37df4f2)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: Ic41515842fb883f44f228c77b4cd266e16124d99
Reviewed-on: http://review.coreboot.org/7400
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
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tegra124: use pll_c_out1 as sclk parent
Reviewed-on: https://chromium-review.googlesource.com/180865
(cherry picked from commit 418337a5bde70df6a770222201c51bf3e8892d5f)
tegra124: take LP cluster out of reset
Reviewed-on: https://chromium-review.googlesource.com/180866
(cherry picked from commit 74cdc68ea9b29da9af313635787e82bacb9e23e3)
tegra124: norrin: display code clean up
Reviewed-on: https://chromium-review.googlesource.com/181003
(cherry picked from commit 63843ec61b3b47ffc985edcb589771591c5c9f17)
tegra124: Change the display hack to use window A
Reviewed-on: https://chromium-review.googlesource.com/182001
(cherry picked from commit ef245e42eb17b2eb0e8712f252353a95ee6fc01a)
tegra124: norrin: Initialize frame buffer
Reviewed-on: https://chromium-review.googlesource.com/182090
(cherry picked from commit b7c1d1b3c9519cbbe1615737aed4c4c0efed2167)
nyan: do not enable pull-ups on SPI1 (EC) data pins
Reviewed-on: https://chromium-review.googlesource.com/181063
(cherry picked from commit 2f55188501ebcae9e01b12831f152d4520c7047c)
tegra124: Add source for the LP0 resume blob.
Reviewed-on: https://chromium-review.googlesource.com/183152
(cherry picked from commit a00d099bf710c297320d7edff7f7c608283d1b0b)
tegra124: Revise Memory Controller registers structure definition.
Reviewed-on: https://chromium-review.googlesource.com/182992
(cherry picked from commit ae83564cdd1d46c8166df1a95703e8cb1060c0a1)
tegra124: Add more PMC register details.
Reviewed-on: https://chromium-review.googlesource.com/183231
(cherry picked from commit d62ed2c19693284f10c2a12f4295091de3ace829)
tegra124: Add SDRAM configuration header file from cbootimage.
Reviewed-on: https://chromium-review.googlesource.com/182613
(cherry picked from commit 193ed2a104af38f6c41a332a649ce06a3238e0a4)
tegra124: Revise sdram_param.h for Coreboot.
Reviewed-on: https://chromium-review.googlesource.com/182614
(cherry picked from commit 311b0568c5de627435a5b035a7a1e40ecc2672f8)
tegra124: Fix EMC base address.
Reviewed-on: https://chromium-review.googlesource.com/183602
(cherry picked from commit 587c8969292ccecfa29c7720bcf24c704ed4ac4e)
tegra124: Add EMC registers definition.
Reviewed-on: https://chromium-review.googlesource.com/183622
(cherry picked from commit 67a8e5c7e87a1cc6bf006ad806751b549ffd3d5a)
tegra124: Never touch MEM(MC)/EMC clocks in ramstage.
Reviewed-on: https://chromium-review.googlesource.com/183623
(cherry picked from commit 8e3bb34d4ae37feae89b4a39850b2988a334d023)
tegra124: use RAM_CODE[3:2] for ram code
Reviewed-on: https://chromium-review.googlesource.com/183833
(cherry picked from commit 0154239467064ffcbdb82fc4c6b629f5d0c3568d)
tegra124: Allow setting PLLM (clock for SDRAM).
Reviewed-on: https://chromium-review.googlesource.com/183621
(cherry picked from commit a534e5b7c61d655eedd409dbd7780a4f90d40683)
tegra124: SDRAM Initialization.
Reviewed-on: https://chromium-review.googlesource.com/182615
(cherry picked from commit 5a60ae93b0603ee0d4806132be0360f3b1612bce)
tegra124: Get RAM_CODE for SDRAM initialization.
Reviewed-on: https://chromium-review.googlesource.com/183781
(cherry picked from commit a5b7ce70525d7ffef3fac90b8eb14b3f3787f4d8)
Squashed 18 nyan/tegra commits for memory and display.
Change-Id: I59a781ee8dc2fd9c9085373f5a9bb7c8108b094c
Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
Reviewed-on: http://review.coreboot.org/6914
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins)
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tegra124: Set Tx FIFO threshold value to recommended setting
Reviewed-on: https://chromium-review.googlesource.com/175200
(cherry picked from commit c8f086711c6ae2db70fc8e0d84b54f5952fbe0ad)
tegra124: add CLK_X definitions
Reviewed-on: https://chromium-review.googlesource.com/175220
(cherry picked from commit 3f8a844bd2f151e06d82d1a7fac4492c6bc9417d)
tegra124: fix incorrect struct member in clk_rst.h
Reviewed-on: https://chromium-review.googlesource.com/175270
(cherry picked from commit 967193d5984a086c297988caa580b61cb4d0414c)
tegra124: add the _x clocks to clock_enable_clear_reset
Reviewed-on: https://chromium-review.googlesource.com/175539
(cherry picked from commit df4c515d73b02061e5c98f51efd50e04b10d63f5)
tegra124: add clock support code for graphics.
Reviewed-on: https://chromium-review.googlesource.com/175162
(cherry picked from commit b8eb6ab4cdc5a583636c10fa05f947a244f94819)
tegra124: Clean up some #defines for DMA
Reviewed-on: https://chromium-review.googlesource.com/175631
(cherry picked from commit 1a0a900f2d060916c9878781b82113b16a7945d9)
tegra124: enable flow control for APBDMA in SPI driver
Reviewed-on: https://chromium-review.googlesource.com/175630
(cherry picked from commit 873e6f9e95f6cb0162fa06216682fbc71ab0202d)
nyan: move clock setup for the display out of dca_init
Reviewed-on: https://chromium-review.googlesource.com/175656
(cherry picked from commit 32dd9947a60298ff9488c911629802c257ed6afc)
tegra124: more display PLL setup and clock hardcode removal.
Reviewed-on: https://chromium-review.googlesource.com/175732
(cherry picked from commit 80402876b5daa9e9389fd4fab5f539d89c37fa7f)
tegra124: move dp.c from tegra to tegra124
Reviewed-on: https://chromium-review.googlesource.com/175830
(cherry picked from commit e98be569b0ba7f4d565ce677343a317db08344e0)
tegra124: clean up tabbing; nyan: add a comment and setting to devicetree.cb
Reviewed-on: https://chromium-review.googlesource.com/175889
(cherry picked from commit 4e513196b0014c5a82079f3aa87c2efbeb645484)
tegra: get rid of struct members that are not used
Reviewed-on: https://chromium-review.googlesource.com/176023
(cherry picked from commit 032b8a0c9fe0152ebc27344e93128865ecb918a6)
tegra124: Increase SCLK (AVP) to 300MHz
Reviewed-on: https://chromium-review.googlesource.com/175489
(cherry picked from commit 7e082f2c2f030950d652f1f87f637e15dee38552)
tegra124: Address old main CPU starting review feedback.
Reviewed-on: https://chromium-review.googlesource.com/175933
(cherry picked from commit 1d76ac71bd839dff9198e65132ec25212dd55ffd)
tegra124: Revise clock source configuration for irregular peripherals.
Reviewed-on: https://chromium-review.googlesource.com/176109
(cherry picked from commit 1021c215190602a2b8c1ab97d6c8313d89597d99)
nyan: add timestamps in romstage
Reviewed-on: https://chromium-review.googlesource.com/176172
(cherry picked from commit cd626aa10b56cd4da6ebda36fe487e44b08f3935)
tegra124: Allow enabling clock output for external peripherals.
Reviewed-on: https://chromium-review.googlesource.com/176108
(cherry picked from commit ea9fb6393ee80da77c9fbc30f605859c7009c9ed)
nyan: Enable and configure clocks for I2S and audio codec.
Reviewed-on: https://chromium-review.googlesource.com/176104
(cherry picked from commit 1fb659b3e73285ff8218c0f229734edd3b979ca4)
tegra124: Fix typo in pinmux name.
Reviewed-on: https://chromium-review.googlesource.com/176215
(cherry picked from commit c7915ad41a3f1d1452aa6d6d287aaa8eb9e85c34)
nyan: Add pinmux settings for audio peripherals.
Reviewed-on: https://chromium-review.googlesource.com/176212
(cherry picked from commit 37412f3201590e47a06d4678fa833164d370b41c)
nyan: De-array-ify the PMIC setup code.
Reviewed-on: https://chromium-review.googlesource.com/176903
(cherry picked from commit 86ab1ce9fbf6d5362af1ee37de1394412366f247)
nyan: Add a kconfig for building for the original nyans in pixel cases.
Reviewed-on: https://chromium-review.googlesource.com/176904
(cherry picked from commit 1d05fd5bc40d727826510ec81496ce4a49e257ed)
nyan: Set the CPU voltage differently depending on which PMIC is in use.
Reviewed-on: https://chromium-review.googlesource.com/176905
(cherry picked from commit 31507f6a575220737ee5683b312cd162600f89cc)
nyan: Increase the CPU voltage to 1.2V.
Reviewed-on: https://chromium-review.googlesource.com/176906
(cherry picked from commit fe4795e66b515c2523df09a8800ecac9a3f63557)
tegra124: Flesh out/tidy up the flow controller constants.
Reviewed-on: https://chromium-review.googlesource.com/177085
(cherry picked from commit b50d315506a5ab9c81b6bbaf8cf580dbb3e78794)
tegra124: When leaving the bootblock/AVP, really stop the AVP.
Reviewed-on: https://chromium-review.googlesource.com/177086
(cherry picked from commit 06c10df889d4d935bc99792df860d93766ae44dd)
nyan: Set SPI4 speed to 33MHz
Reviewed-on: https://chromium-review.googlesource.com/177038
(cherry picked from commit c98de65482fabdb5c76944fe3bf762191b3a0a55)
nyan: Do console_init() in romstage
Reviewed-on: https://chromium-review.googlesource.com/176763
(cherry picked from commit 0bec32e09eab28bc5ea49b7896a8b6f489143b03)
nyan: Add a prompt to the CONFIG_NYAN_IN_A_PIXEL option.
Reviewed-on: https://chromium-review.googlesource.com/177486
(cherry picked from commit 7cbb801d000dac4b39f76266ebef2585fe48faba)
nyan: Separate the SDRAM BCT config for the two nyans, and turn down norrin.
Reviewed-on: https://chromium-review.googlesource.com/177487
(cherry picked from commit 6b119685f6626d79d924af9f856ebb90af45a73f)
tegra124: Bump up HCLK and PCLK
Reviewed-on: https://chromium-review.googlesource.com/177563
(cherry picked from commit c25337dac8c3ecdd8ffe5b4d11acebb216132405)
nyan: Add some code for reading the board ID.
Reviewed-on: https://chromium-review.googlesource.com/177488
(cherry picked from commit 5fccbce99e7db312e2e3caf806c438c9b04c0a8f)
nyan: Use the board ID to decide how to initialize the PMIC.
Reviewed-on: https://chromium-review.googlesource.com/177489
(cherry picked from commit 677bdb9df55248da3a0c6be0089098f6d6807d3c)
nyan: Create kconfig variables for each SDRAM config.
Reviewed-on: https://chromium-review.googlesource.com/177580
(cherry picked from commit d7ddcf262a321f06289c4f2b2a6b43982dd96377)
tegra124: Mux some unused pins away from UARTA, and pull up the serial RX line.
Reviewed-on: https://chromium-review.googlesource.com/177637
(cherry picked from commit bd533cc109b0acf3495b04fa6622e250ba454fe9)
tegra124: Initialize the MCR when setting up the UART.
Reviewed-on: https://chromium-review.googlesource.com/177638
(cherry picked from commit 38c84786fc3e8fab913aebca176ac7b038cb0be6)
tegra124: fix SPI AHB burst length
Reviewed-on: https://chromium-review.googlesource.com/177564
(cherry picked from commit f29235263202c9b4a3dbb65da5727c8eefe44315)
tegra124: remove unneeded debug print in SPI code
Reviewed-on: https://chromium-review.googlesource.com/177833
(cherry picked from commit 34a50040268dbde1c326d315f8042a3905ddfb06)
nyan: Set up the SOC and TPM reset pin.
Reviewed-on: https://chromium-review.googlesource.com/177965
(cherry picked from commit b81a5bd15a2979ee009b9f7bc4a39a304e6a759a)
tegra124: Allow some time for packets to appear in Rx FIFO
Reviewed-on: https://chromium-review.googlesource.com/177832
(cherry picked from commit 8f70a25b1eea865a448525749ac18393f5b9ad84)
nyan: PMIC: Slam default init values for SDOs/LDOs in AS3722
Reviewed-on: https://chromium-review.googlesource.com/178226
(cherry picked from commit c536b0d82fd6fffbc0e2448e0d19d3f06df5d86a)
nyan: change devicetree for the new display settings.
Reviewed-on: https://chromium-review.googlesource.com/177958
(cherry picked from commit 43abed730f222c8a685c250a58c981268994a65d)
nyan: Switch USB VBUS GPIOs from outputs to pulled-up inputs
Reviewed-on: https://chromium-review.googlesource.com/178914
(cherry picked from commit e47b6a609b9d23694a466b56960d9d14ca5d6242)
Tegra124: nyan: Disable VPR
Reviewed-on: https://chromium-review.googlesource.com/179327
(cherry picked from commit 441aa276446141f1b92ed8fb98c9578597487f4d)
tegra124: norrin: fix display issue
Reviewed-on: https://chromium-review.googlesource.com/179745
(cherry picked from commit c1c1ae69f6058ed901f532e2c532d1e6ba1f81fb)
tegra124: Add iRAM layout information.
Reviewed-on: https://chromium-review.googlesource.com/179814
(cherry picked from commit d00f135c93a52ad4dced2edecb74e2dfc54bb2fa)
tegra124: Run bootblock and ROM stage out of DRAM.
Reviewed-on: https://chromium-review.googlesource.com/179822
(cherry picked from commit 2d3ec06ec39a489d02e798bb22bce4d7465b20ce)
nyan: clean up a comment regarding video
Reviewed-on: https://chromium-review.googlesource.com/180161
(cherry picked from commit 03b5e88a66b9c96df2ef3d9ce5ba4a62a8bb2447)
tegra124: norrin: the first step to clean up display code
Reviewed-on: https://chromium-review.googlesource.com/180135
(cherry picked from commit 9d0c12dfef28a1161604df9b3fcc113049b2747d)
Squashed 49 commits for tegra124/nyan.
Change-Id: Id67bfee725e703d3e2d8ac17f40844dc193e901d
Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
Reviewed-on: http://review.coreboot.org/6883
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Tegra124: SDMMC: Configure base clock frequency.
Reviewed-on: https://chromium-review.googlesource.com/173841
(cherry picked from commit d3157e9a380cfb018cc69a1f23f277c3c5b680a6)
Tegra124: SDMMC: Configure pinmux for MMC 3/4.
Reviewed-on: https://chromium-review.googlesource.com/174011
(cherry picked from commit 55af9a86a56d6bc0ce9bcff4fd5226a60ae2033b)
tegra124: Move DMA-related #defines and definitions to header
Reviewed-on: https://chromium-review.googlesource.com/174444
(cherry picked from commit 9d917927a5b7151958289469b9049ac91efa41e3)
tegra124: Assign console address for kernel.
Reviewed-on: https://chromium-review.googlesource.com/174486
(cherry picked from commit 36e9370f30bd173879958d164156997841ec4e9c)
nyan: Fix up the gpio indices in chromeos.c.
Reviewed-on: https://chromium-review.googlesource.com/174418
(cherry picked from commit fba4ae1080c19f11abe1205b871ada14db996c61)
Nyan: turn on the backlight.
Reviewed-on: https://chromium-review.googlesource.com/174533
(cherry picked from commit 12649c9611981dd8d6567ba0238c8b8247c52215)
tegra124: Fix the disp1 source field.
Reviewed-on: https://chromium-review.googlesource.com/174701
(cherry picked from commit eed380e09075e1eef0bde7d1bb15c4343f30bfe0)
nyan: set up the aux channel i2c interface
Reviewed-on: https://chromium-review.googlesource.com/174620
(cherry picked from commit ea81cb44a1c11cd78643c69ac818304cd393749e)
tegra124: fix typos in the clock code.
Reviewed-on: https://chromium-review.googlesource.com/174684
(cherry picked from commit 72365c33693db4eb6e01032938221f592b7e5a02)
tegra124: Revamp clock source/divisor configuration
Reviewed-on: https://chromium-review.googlesource.com/174804
(cherry picked from commit 3f31a634f69595bcc6a473301d1492c97a767809)
tegra: Add gpio_output_open_drain() function
Reviewed-on: https://chromium-review.googlesource.com/174650
(cherry picked from commit bc1c28926810e722e9b82339ea0585d083e3fa8c)
tegra124: add nvidia-generated files
Reviewed-on: https://chromium-review.googlesource.com/174610
(cherry picked from commit 7706f3200f7fc11b7a443f336bff6a37afa94652)
nyan: Ignore the dev mode GPIO.
Reviewed-on: https://chromium-review.googlesource.com/174837
(cherry picked from commit 9513e608f3063fdb3e9d8bd04e6e5fe35a5bfcee)
Tegra124: Add support for the ARM architectural timer.
Reviewed-on: https://chromium-review.googlesource.com/174835
(cherry picked from commit 25a91fcf7e79cc450caa59bc6b65f954bb96ac6c)
nyan: Initialize the ARM architectural timer in the RAM stage.
Reviewed-on: https://chromium-review.googlesource.com/174836
(cherry picked from commit 581f592c12de91c0cf8279ede2850e38dd0cd2e8)
tegra124: nyan: Move mainboard level clock stuff into the mainboard source.
Reviewed-on: https://chromium-review.googlesource.com/174843
(cherry picked from commit 5ab100b0bad22814261f9b755b59394562c9145a)
tegra124: add some explanatory text about U7.1 computations.
Reviewed-on: https://chromium-review.googlesource.com/173910
(cherry picked from commit 822cad0ceeceeb5160c8216e05eec13fd04a6413)
Set the EC SPI clock source to PLLP and divide down to around 5MHz
Reviewed-on: https://chromium-review.googlesource.com/173954
(cherry picked from commit c0e22d76d3887ca1f727443a47db38dec12c0b74)
nyan: Move non-essential configuration out of bootblock and into ram stage.
Reviewed-on: https://chromium-review.googlesource.com/174844
(cherry picked from commit dad7f68c76f7b83edacd8b22c9dbd3f0ff027397)
tegra124: clocks: Save some IOs in clock_enable_clear_reset.
Reviewed-on: https://chromium-review.googlesource.com/174845
(cherry picked from commit 81b977a2758d42471667e2cbe31f160dfda5bca4)
tegra124: re-write SPI driver w/ full duplex support
Reviewed-on: https://chromium-review.googlesource.com/174446
(cherry picked from commit 51c9a34240d6a068780a7d1c27b032b56b2d3e54)
tegra124: move SPI-related structures from .c to .h
Reviewed-on: https://chromium-review.googlesource.com/174637
(cherry picked from commit 36760a4463c2c33f494ca7ea5a36810fa4502058)
tegra124: add frame header info to SPI channel struct
Reviewed-on: https://chromium-review.googlesource.com/174638
(cherry picked from commit e24773eb946e2c4cb5e828f055d45d92bd1a4f9f)
tegra124: re-factor tegra_spi_init()
Reviewed-on: https://chromium-review.googlesource.com/174639
(cherry picked from commit 88354b996459a702c36604f5f92c24e63df8de7e)
nyan: Set CrOS EC frame header parameters for SPI
Reviewed-on: https://chromium-review.googlesource.com/174710
(cherry picked from commit 29173ba5863eebb2864a8384435cde2f0d5ca233)
tegra124: Add Rx frame header support to SPI code
Reviewed-on: https://chromium-review.googlesource.com/174711
(cherry picked from commit 1d1630e770804649ef74d31db194d3bde9968832)
tegra124: add support for the Serial Output Resource (sor)
Reviewed-on: https://chromium-review.googlesource.com/174612
(cherry picked from commit 3eebd10afea4498380582e04560af89126911ed9)
nyan: tegra124: Enable I, D and L2 caches in romstage.
Reviewed-on: https://chromium-review.googlesource.com/173777
(cherry picked from commit 74512b7ecfbd50f01a25677307084699ee8c6007)
tegra and tegra124: Bring up graphics
Reviewed-on: https://chromium-review.googlesource.com/174613
(cherry picked from commit 7e944208a176cdac44a31e2a9961c8bd5dc4ece8)
nyan: Move the DMA memory region.
Reviewed-on: https://chromium-review.googlesource.com/174953
(cherry picked from commit c66e22859252eaebceb07a3118ac61f4cf6289eb)
tegra124: Increase CBFS cache buffer size
Reviewed-on: https://chromium-review.googlesource.com/174950
(cherry picked from commit 6dbb4e5f0d66c68df45ac73e3f223b856b715026)
tegra124: Add USB PLL, PHY and EHCI setup code
Reviewed-on: https://chromium-review.googlesource.com/174651
(cherry picked from commit ecd5c398ff6748a7d40089019471357b58d3a6ea)
tegra124: add in some undocument clock source and PLL registers
Reviewed-on: https://chromium-review.googlesource.com/174948
(cherry picked from commit 73fcc4981da6e4415b514eaafb42bc265ab0cd9a)
tegra124: small cleanups of the code
Reviewed-on: https://chromium-review.googlesource.com/174995
(cherry picked from commit 7256aba07e9567ef8d73f05e1f80c4d45fd57bda)
Squashed 34 commits for tegra124 / nyan support.
Change-Id: I050c7ad962e0d24550b0b33c9318e89c80d01f00
Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
Reviewed-on: http://review.coreboot.org/6870
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Tested-by: build bot (Jenkins)
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nyan: Clock setup.
Reviewed-on: https://chromium-review.googlesource.com/172106
(cherry picked from commit 3697b6454c0aceebcf735436de90ba2441c9b7b1)
tegra124: Call into the mainboard bootblock init if one exists.
Reviewed-on: https://chromium-review.googlesource.com/172581
(cherry picked from commit 3a0cd48a0d1a9ce6b32ed614cd81fb81f5f82aec)
nyan: Add a mainboard specific bootblock.
Reviewed-on: https://chromium-review.googlesource.com/172582
(cherry picked from commit a83d065d660a26fe71ed79879c25f84a1b669f69)
nyan: tegra124: Redestribute the clock code between the mainboard and soc.
Reviewed-on: https://chromium-review.googlesource.com/172583
(cherry picked from commit ea703137fc37befa7d5a65afc982e298a0daca1b)
nyan: Initialize the i2c pins and controllers.
Reviewed-on: https://chromium-review.googlesource.com/172584
(cherry picked from commit 9c10a3074ef834688fea46c03551c2e3e54e44a8)
nyan: Initialize the PMIC.
Reviewed-on: https://chromium-review.googlesource.com/172585
(cherry picked from commit f6be8b0e607e05b73b5e4a84afcf04c879eee88a)
tegra124: add a chip.h and use it in NYAN
Reviewed-on: https://chromium-review.googlesource.com/172773
(cherry picked from commit 4dd5f1f091f2dcae5ce38203bb86c62994609f8f)
tegra: Reorder GPIO register accesses to avoid glitching
Reviewed-on: https://chromium-review.googlesource.com/172730
(cherry picked from commit 61bedbf0f839e19b284d21af2ad10f2ff15e17d5)
tegra: Turn GPIO wrappers into macros to make them easier to write
Reviewed-on: https://chromium-review.googlesource.com/172731
(cherry picked from commit 94550fdfa5a8005d2e6a313041de212ab7ac470c)
tegra: Change GPIO functions to allow variable arguments
Reviewed-on: https://chromium-review.googlesource.com/172916
(cherry picked from commit e95ccd984f718a04b6067ff6ad5049a2cd74466d)
tegra124: Implement starting up the main CPUs.
Reviewed-on: https://chromium-review.googlesource.com/172917
(cherry picked from commit 7c5169a197310e18a3df0f176c499669e3c2bda3)
tegra: Simplify the I2C constants.
Reviewed-on: https://chromium-review.googlesource.com/172953
(cherry picked from commit 130a07c86dfa5ba5ac4580f29db927c91f045c76)
tegra124: Fix SPI base addresses
Reviewed-on: https://chromium-review.googlesource.com/173322
(cherry picked from commit da808e46919ebd3b9f2377a5889f0d5f10b92357)
tegra124: Scrub the clock constants.
Reviewed-on: https://chromium-review.googlesource.com/172954
(cherry picked from commit 9305ff0696a6d556a97f928b8683770833a309a4)
tegra124: add DMA support
Reviewed-on: https://chromium-review.googlesource.com/172951
(cherry picked from commit 4d2a5a56b922ac37d2326d7b139697567aac37b8)
tegra124: add basic SPI driver
Reviewed-on: https://chromium-review.googlesource.com/172952
(cherry picked from commit 5f861f13c7fd2dd881f3cbd0f1b4d4a9994ce429)
tegra124: Add an assembly stub which is run first on the main CPUs.
Reviewed-on: https://chromium-review.googlesource.com/173541
(cherry picked from commit e142b9572a89f43fe984c4fc87e3203f380ff4de)
nyan: tegra124: Set up dynamic cbmem.
Reviewed-on: https://chromium-review.googlesource.com/173542
(cherry picked from commit b6e1a70103446abb5c3440f145617e6566879c6f)
tegra124: Add an soc.c which sets up the chip operations and memory resource.
Reviewed-on: https://chromium-review.googlesource.com/173543
(cherry picked from commit af49a5bd1f589cf053c4808510138aae26e20db4)
tegra124: extend chip.h to include video settings
Reviewed-on: https://chromium-review.googlesource.com/173600
(cherry picked from commit 87687633a2116f58fad7333b3b639cee9089ad29)
tegra124 and nyan: fill in the devicetree a bit more, add defines
Reviewed-on: https://chromium-review.googlesource.com/173684
(cherry picked from commit c107eaca3dea42be89f61690d0d6cb2181acb147)
tegra124: clean-ups for SPI driver
Reviewed-on: https://chromium-review.googlesource.com/173599
(cherry picked from commit 1e2f9fd442ea336bf0663c3c8ea51f771e21beb7)
tegra124: add a #define for DMA alignment size
Reviewed-on: https://chromium-review.googlesource.com/173638
(cherry picked from commit f9dc2a8d8016fa7db974fb6cb01c3275e26832af)
tegra124: Add FIFO transmit functions to SPI driver
Reviewed-on: https://chromium-review.googlesource.com/173639
(cherry picked from commit 97e61f36ad96ce2f9b12a7ef765ee73d3f4285f7)
tegra124: clean-ups for DMA driver
Reviewed-on: https://chromium-review.googlesource.com/173598
(cherry picked from commit 750c0a5d6942748dd21f3a3f884ad94a561e86e0)
tegra124: early display and display code.
Reviewed-on: https://chromium-review.googlesource.com/173622
(cherry picked from commit 651c7ab96b1f136865e4673a120de7afc1218558)
tegra124: Move transfer size handling to spi_xfer()
Reviewed-on: https://chromium-review.googlesource.com/173680
(cherry picked from commit 4a9b7b47b3c09d70063ea843054ffef98f554621)
tegra124: strict error detection and reporting for SPI
Reviewed-on: https://chromium-review.googlesource.com/173681
(cherry picked from commit c056fa954e1dab40a56faec6c50385763a2eb010)
tegra124: add thread-friendly delays to SPI driver
Reviewed-on: https://chromium-review.googlesource.com/173648
(cherry picked from commit c1a321c8f61942801627f895c5db74c518e2aa8e)
Tegra124: Take the SPI1 controller out of reset and enable its clock.
Reviewed-on: https://chromium-review.googlesource.com/173787
(cherry picked from commit c026a3fb861e157f1e17a121fc2ef70b903f36f2)
tegra124: add two more clock setting values
Reviewed-on: https://chromium-review.googlesource.com/173772
(cherry picked from commit 7d79d7dd9f0c1fd7127a7ba41652d809ccff7a57)
nyan: Set up the ChromeOS related GPIOs and SPI bus 1 which goes to the EC.
Reviewed-on: https://chromium-review.googlesource.com/173788
(cherry picked from commit ff172bfe30f75983a1e8efa2ead0a4519583d0a8)
tegra124: Add some stub functions to the Tegra SPI driver.
Reviewed-on: https://chromium-review.googlesource.com/173789
(cherry picked from commit 8bc527aa4afd301c046b0e844c7fa400630af0d2)
tegra124: Build source files into the various stges needed by CONFIG_CHROMEOS.
Reviewed-on: https://chromium-review.googlesource.com/173790
(cherry picked from commit 86a6423b668ca912295c47d8c6e3ef6c6f8c6084)
nyan: Implement the code which reads GPIOs for ChromeOS.
Reviewed-on: https://chromium-review.googlesource.com/173791
(cherry picked from commit 4c394dfbce762574fc79edcb6e4ac6bf346e48a3)
nyan: Enable the CHROMEOS and ChromeOS EC related kconfig options.
Reviewed-on: https://chromium-review.googlesource.com/173792
(cherry picked from commit 2845a4487159aa4b1dba58d977f52c449574fc8e)
Tegra124: SDMMC: Take the SDMMC 3 and 4 out of reset and ungate their clocks.
Reviewed-on: https://chromium-review.googlesource.com/173793
(cherry picked from commit c238b87bcd9d35afd828476d6ee88322ac5d0f88)
tegra124: fix clear_fifo_status() in SPI driver
Reviewed-on: https://chromium-review.googlesource.com/173738
(cherry picked from commit f415d2c0aaffc0f1a3592551a2db782d538f8f4f)
ARM: Include stdint.h in cpu.h.
Reviewed-on: https://chromium-review.googlesource.com/173774
(cherry picked from commit f1930faea3f14b2a2560a6c4058ef38532b6f1a6)
tegra124: When setting up the main CPU, set its CPSR appropriately.
Reviewed-on: https://chromium-review.googlesource.com/173775
(cherry picked from commit bc2ba9c15cfd22aeaca4f80b1d13a8b5e0178ead)
tegra124: fix wrong names in clk_rst.h
Reviewed-on: https://chromium-review.googlesource.com/173955
(cherry picked from commit 19dd9c85e4a3d1f77b23828bcbdd4bd8c2688b8d)
tegra124: Fix up the PLLX divider table.
Reviewed-on: https://chromium-review.googlesource.com/173778
(cherry picked from commit 3362cf3a7d6f5eaec879dda42323345922f6df17)
tegra124: clock: Get rid of cpcon and dccon.
Reviewed-on: https://chromium-review.googlesource.com/173779
(cherry picked from commit 08626ffac4a7e9ea3d4738af87e9e4cced7be2c7)
Tegra124: SPI: Set and unset CS in spi_claim_bus and spi_release_bus.
Reviewed-on: https://chromium-review.googlesource.com/173953
(cherry picked from commit a2df8f3a9c9c54c62d6ff37d3baff1d30ee6d355)
armv7: expose dcache_line_bytes() in cache API
Reviewed-on: https://chromium-review.googlesource.com/173975
(cherry picked from commit 6727f65702c7668fcb33848b4113bc3d3cc04e12)
libpayload: expose dcache_line_bytes() in ARM cache API
Reviewed-on: https://chromium-review.googlesource.com/174099
(cherry picked from commit 9387b02dff85b42944d95c3bccf59059c93fb4a9)
armv4: add a stub for dcache_line_bytes()
Reviewed-on: https://chromium-review.googlesource.com/173976
(cherry picked from commit 924f61ea895b9268c716791466637009bbac6469)
tegra124: Base early UART on CLK_M to enable debugging of PLL init code
Reviewed-on: https://chromium-review.googlesource.com/174339
(cherry picked from commit 8d9387432f0a0d9b257b040304238e543cced1aa)
tegra124: Add additional PLLs and redesign the divisor table
Reviewed-on: https://chromium-review.googlesource.com/174380
(cherry picked from commit f6a5f5c4562f1ca733505717c175be00413f2384)
Squashed 49 commits for tegra124/nyan that included a lot of churn on
different pieces.
Change-Id: I00e8f5b74e835e01b28ca2e9c4af3709c9363d56
Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
Reviewed-on: http://review.coreboot.org/6869
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
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Old-Change-Id: Icdde4cf5e1abb3ae1ad14279ebc129919ba30074
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://chromium-review.googlesource.com/170837
Reviewed-by: Gabe Black <gabeblack@chromium.org>
Commit-Queue: Gabe Black <gabeblack@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
(cherry picked from commit e9d87534ccacb42d508f1902786470798a2dbaea)
nyan: Add a "special-class" for aggregating BCT files into bct.cfg.
The config file which cbootimage processes to create a BCT could come from
multiple different files, individually selected based on config options,
and/or split up into different files for organizational purposes. This change
adds a special-class which collects those files and concatenates them all
together in a bct.cfg which can be processed more easily by other parts of the
build.
While the BCT files themselves are potentially very board specific, for
instance ones that hold memory timing information, this bit of code which
collects them is not. It has to be in each board file instead of alongside the
CPU, however, to ensure that the special class is set up before another
Makefile tries to use it. If we end up with lots of Tegra based boards which
duplicate this code over and over, we might want to revisit how this works.
Old-Change-Id: I58e1373434f89e69298990ea4643a19d8afdc309
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://chromium-review.googlesource.com/170922
Reviewed-by: Gabe Black <gabeblack@chromium.org>
Commit-Queue: Gabe Black <gabeblack@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
(cherry picked from commit 3ae44178b7084037a75e16ce161b1432abf4246a)
nyan: Add bct files for nyan.
There's a config option which selects between the emmc and spi config files
depending on what the firmware is intended to boot from. These are copied from
the files installed by the tegra-bct-nyan ebuild, except that the spi config
file has been modified so that there's only one copy of the BCT and so that it
only has one configuration. This is to save space in the final image.
Old-Change-Id: Ibf1b895bb3ed060d394fc6ffcec67b6972bb21e3
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://chromium-review.googlesource.com/170923
Reviewed-by: Gabe Black <gabeblack@chromium.org>
Commit-Queue: Gabe Black <gabeblack@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
(cherry picked from commit 6bbcffe04e8ae73c86bc05c577a67f909857e1c0)
Squashed three commits required to get nyan building since some patches
were out of order. Added a select to the nyan mainboard Kconfig to have
a rom size of 1024K to match the saved config on the chromium side.
Change-Id: I346dbb02d216adfea9707e40adf0a4d1e0fabf36
Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
Reviewed-on: http://review.coreboot.org/6669
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
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