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Generate the RAM Strap IDs based on the initial memory configuration.
BUG=b:272746814
TEST=Build Myst BIOS image.
Change-Id: I8a4fe9a41f101ac10391756f1b815220c8b98612
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74745
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Jon Murphy <jpmurphy@google.com>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
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This will fix:
> [INFO ] Probing TPM I2C: tis_plat_irq_status() not implemented,
wasting 20ms to wait on Cr50!
BUG=b:277297687
TEST=builds
Change-Id: I611a2855d94167748d0f82a478687fe2cdf5846a
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74286
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Tim Van Patten <timvp@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Configure PCIe Clk Source and Clk Request mapping. Configure GPIOs used
for WLAN. Mapping derived from myst schematic.
BUG=b:275965982
TEST=Builds
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Change-Id: I5059be0bc011978e74ab4245e6ae037aa177ef9b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74113
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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Ensure that DXIO descriptors are updated using info from AMD and Myst
board schematics.
BUG=b:275960920,b:276744321
TEST=builds
Change-Id: Icdad785bcb90de036095bcc4219c15f55f4277fe
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74112
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Van Patten <timvp@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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Enable gfx_hda to allow for audio over hdmi.
BUG=b:277219546
TEST=builds
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Change-Id: I58096f1408f66f968af1494e487cf2bfc43b9a0f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74278
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add the crypto device to the devicetree.
BUG=b:277214359
TEST=builds
Change-Id: I5394c5f9df64642d8633af84cf662652bd1a5cb2
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74275
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The mp2 PCI device is still present when no mp2 firmware is loaded. When
this device isn't explicitly enabled in the mainboard's devicetree, the
chipset devicetree default of the device being disabled is used. This
results in coreboot's resource allocator not allocating resources to
the device and since the bridge doesn't have enough MMIO space reserved,
the Linux kernel can't assign resources to it. Enable the mp2 device in
the mainboard's devicetree so that it gets its resources assigned by
coreboot.
BUG=b:277217097
TEST=builds
Change-Id: I21885c51ff08846b456675090946f381843ef5e6
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74277
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Enable the audio co-processor in the device tree.
BUG=b:277214614
TEST=builds
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Change-Id: I1e1749359804960bbd75d869385b9071e7f33be7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74276
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Configure GSC I2C and Interrupt GPIOs during the early initialization.
Add devicetree configuration for GSC device and enable the required
config items.
BUG=b:275959717
TEST=builds
Change-Id: I6e235356b252a7b68a42da128ffd3189a829f117
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74111
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add eSPI configuration for myst. Ensure the additional windows are used
and remove unnecessary addresses from the range used on skyrim.
BUG=b:275953893
TEST=builds
Change-Id: I7b40adec78d4e0b596596fa6e2951c79bd3bd8c7
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74110
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add I2C peripheral reset configuration required during early init.
Enabled I2C generic and HID drivers.
BUG=b:275939564
TEST=builds
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Change-Id: I44668295fb6ed03992df9d9fc075792e181d1a8a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74108
Reviewed-by: Tim Van Patten <timvp@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The USB port configuration was derived from the PPR and schematics.
Primary functions are:
2 USB-C ports
1 USB SS+ type A port
2 Cameras (World/User facing)
1 Bluetooth transceiver
1 WWAN
BUG=b:275905635
TEST=builds
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Change-Id: Iecb256cad7b2daea1fddfc8323e88ff5c38d1e51
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74106
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Van Patten <timvp@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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Enable the XHCI controllers in the devicetree for myst project.
BUG=b:275905635
TEST=builds
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Change-Id: I05dc5bb157f0ef955e4b37e34d7b32678e42ebc8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74105
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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Enable internal graphics on the phoenix soc for myst projects.
BUG=b:275900162
TEST=builds
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Change-Id: Ia6ef1ca07b9af491c7d937be5cef4f051852e486
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74104
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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Enable iommu in devicetree for myst in order to allow kernel to load and
initialize IOMMU.
Bug=b:276805280
TEST=builds
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Change-Id: I94e93afe775b070253464a9d187ad6c028d1b811
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74177
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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Enable the console UART for myst devices.
Bug=b:275900837
TEST=builds
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Change-Id: I52c1b86c46907216d88f98917968b833af0d5d41
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74103
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Tim Van Patten <timvp@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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Add initial FW_CONFIG for the myst program.
BUG=b:
TEST=builds
Cq-Depend: chrome-internal:5674351
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Change-Id: If74c3649d4e8d174d9fe00a4b896c2351ee3ab19
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74102
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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Add SMI handler code for Myst platform.
BUG=b:275858191
TEST=builds
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Change-Id: I92e5e6aef7ab0b84a96d976e29ebf96b56f6f1a1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74100
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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BUG=b:270624655
TEST=builds
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Change-Id: Id18a311097d575973087eb92fd446a5c511f570e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74099
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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BUG=b:270618107
TEST=builds
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Change-Id: I688e9c2fdf203cecfd5f200dec6cde9dbc0a9aa7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74098
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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Declare CrOS GPIOs for Myst, add relevant defines needed by chromeOS for
additional control GPIOs.
BUG=b:270616013
TEST=builds
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Change-Id: Ie876883d6ee2e3bc6324c038cefee12d99702dc9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74096
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Initial GPIO configuration for Myst.
BUG=b:270596581
TEST=builds
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Change-Id: Ia019704c7b027f14d46281e0de0ffdbc4906a20b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74095
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add configuration stubs for GPIOs to be implemented later.
BUG=b:270596581
TEST=builds
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Change-Id: I3228f857da7c8c76cf32faf4a23418aedaf40875
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74094
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
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Myst is a new Google mainboard with an AMD Phoenix SOC.
BUG=b:270596106
TEST=util/abuild/abuild -t GOOGLE_MYST --clean
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Change-Id: Id7d731ce4d6cb6d4e9041f46eb5a799865bb0b9a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74093
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
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