summaryrefslogtreecommitdiff
path: root/src/mainboard/google/mancomb
AgeCommit message (Collapse)Author
2021-04-16mb/google/{guybrush,mancomb}: Add VBOOT_VBNV_OFFSETRaul E Rangel
This is the same as zork. BUG=b:184126844 TEST=Boot guybrush in developer mode and switch to normal mode. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ib11c255ab7e937de334ecd18dc030006f7724275 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52354 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-04-15mb/google/guybrush,mancomb: include soc/gpio.h in baseboard/gpio.hFelix Held
This include provides the GPIO_x definitions. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I12a0d95f79658f3852132876e92c389b715f3001 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52358 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-15mb/google/guybrush,mancomb: use EC_SCI_GPI in espi_sci_sources structFelix Held
The board's ec.h file defined EC_SCI_GPI as GEVENT_24, so use that definition in all places in the mainboard code instead of a mix of the board specific define and the SoC's GEVENT number define. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I46525ed24e9993acd3d850959dd63761a690d5df Reviewed-on: https://review.coreboot.org/c/coreboot/+/52309 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-04-12mb/google/mancomb: Temporary fix to set eSPI muxEric Lai
BUG=b:182211161 TEST=builds Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: Ief59bdea392ab3f141ccf7444c608aef99701d2e Reviewed-on: https://review.coreboot.org/c/coreboot/+/52176 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2021-04-12mb/google/mancomb: add DXIO and DDI descriptorsEric Lai
Sync from guybrush. BUG=b:182211161 TEST=builds Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: Ica4e6511a5106a958567565b96d5888b8c829ff2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52180 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-04-09mb/google/mancomb: Add Codec configrationEric Lai
Enable I2C2 in devicetree and fill ACPI information for Codec. BUG=b:182211161 TEST=builds Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: Ib75ef99cbca8b2f38268705704e7616b456f19d9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52179 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mathew King <mathewk@chromium.org>
2021-04-09mb/google/mancomb: Add Bluetooth configurationEric Lai
Configure the BT disable GPIO to logic low in order to enable Bluetooth. BUG=b:182211161 TEST=builds Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I7661dea682cbe0ae5e169d87e794ed6ed3c83b5e Reviewed-on: https://review.coreboot.org/c/coreboot/+/52178 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mathew King <mathewk@chromium.org>
2021-04-09mb/google/mancomb: Update GPIO configurationEric Lai
BUG=b:182211161 TEST=builds Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: Ie3917c10ecf37c914dbadce5949b8f4f772abd5c Reviewed-on: https://review.coreboot.org/c/coreboot/+/52177 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mathew King <mathewk@chromium.org>
2021-04-09mb/google/mancomb: Enable AP <-> H1 communicationEric Lai
BUG=b:182211161 TEST=builds Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I29be8572bc7bb366347eabe553be49775dec46a8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52175 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mathew King <mathewk@chromium.org>
2021-04-09mb/google/mancomb: Add initial I2C configurationEric Lai
BUG=b:182211161 TEST=builds Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I483c2e77eedcb434709b67bf9b3fbca636499508 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52174 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mathew King <mathewk@chromium.org>
2021-04-08mb/amd,google: use PAD_NF_SCI for GPIO_2 config in soc/amd based boardsFelix Held
When GPIO_2 was configured as PAD_NF with the WAKE_L function selected the GPIO_2 override in soc_gpio_hook called soc_route_sci that wrote the corresponding SCI mapping register, but didn't set up the SCI level and trigger type, so that couldn't have worked on most of the boards. The only boards where I think this was actually tested are the google/zork ones and they configured GPIO_2 as PAD_SCI where the GPIO mux setting is GPIO mode instead of the WAKE_L mode, but at least the SCI was configured correctly. The new PAD_NF_SCI macro can configure both the right GPIO mux setting and set up the SCI configuration correctly, so use this new macro for the GPIO_2 pin. For test purposes I also added the corresponding GPIO_2 configuration to amd/mandolin to see if the affected registers end up having the expected value using the HDT debugger to look at the registers, but didn't test the wake-up functionality, since S3 resume isn't working on amd/mandolin yet. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Suggested-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Change-Id: Ic069e46b759fb6746645faccd254263c49a892d4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51756 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-07soc/amd/cezanne: Pass DXIO and DDI Descriptors to FSPMatt Papageorge
This patch adds the functionality to write the DXIO and DDI descriptors to the UPD data structure to the SoC code and adds the mainboard_get_dxio_ddi_descriptors function to each mainboard using the Cezanne SoC that gets called to get the descriptors from the board code. Change-Id: I1cb36addcf0202cd56ce99e610a13d6d230bc981 Signed-off-by: Matt Papageorge <matthewpapa07@gmail.com> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51948 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-04-07mb/google/mancomb: Enable USB ports in devicetreeEric Lai
BUG=b:182211161 TEST=builds Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I375ad38da14189de2ae2713082a80e8cdb2fe5f3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52119 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2021-04-07mb/google/mancomb: Enable PCIe devices in devicetreeEric Lai
BUG=b:182211161 TEST=builds Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: Id6c20b32ddafe415132ce70abf5381ff3aad13f7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52118 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-04-07mb/google/mancomb: Add initial fch irq routingEric Lai
BUG=b:182211161 TEST=builds Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I850a3ecc8776593d97f4162e812a39991caa30ef Reviewed-on: https://review.coreboot.org/c/coreboot/+/52117 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-04-07mb/google/mancomb: Add eSPI GPIO back to init tableEric Lai
GPIOs should be configured in ramstage even if they are configured in an earlier stage. BUG=b:182211161 TEST=builds Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I07d5c46d6ea6dc2bc9ab265d0c01772d653884cc Reviewed-on: https://review.coreboot.org/c/coreboot/+/52123 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-04-07mb/google/mancomb: Configure UART0 gpio in early stageEric Lai
BUG=b:182211161 TEST=builds Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I2d4ec1556ac7136c454eb025ff99aafbf49b8982 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52122 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-04-07mb/google/mancomb: Enable DISABLE_SPI_FLASH_ROM_SHARINGEric Lai
BUG=b:182211161 TEST=builds Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I1d28c2335b095a77285dcb261a0dffe96d129c46 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52125 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-04-07mb/google/mancomb: Enable early EC Software SyncEric Lai
BUG=b:182211161 TEST=builds Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I9768feaadf2423acd50a71e9a2310b4ab2d1a2a8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52124 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-04-05mb/google/mancomb: Add ACPI support for Chrome ECEric Lai
BUG=b:182211161 TEST=builds Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: Ibce15d2e4340515353a33c593d065df50a15286a Reviewed-on: https://review.coreboot.org/c/coreboot/+/51628 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mathew King <mathewk@chromium.org>
2021-04-05mb/google/mancomb: Enable eSPI VW SCI eventsEric Lai
Mancomb does not have a dedicated SCI pin so it uses VW. BUG=b:182211161 TEST=builds Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: Id315ab448209d9c93494f7689361e45f8a6ed001 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51627 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mathew King <mathewk@chromium.org>
2021-04-05mb/google/mancomb: Enable Chrome EC SKUID and BOARDIDEric Lai
BUG=b:182211161 TEST=builds Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I70283c8d93b5cbabdaf5a8ab947d5f8444940dff Reviewed-on: https://review.coreboot.org/c/coreboot/+/51626 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mathew King <mathewk@chromium.org>
2021-04-05mb/google/mancomb: Add smihandlerEric Lai
BUG=b:182211161 TEST=builds Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I52411917d9e7e8f8d9ac5d1c9b426a58ba09f5ae Reviewed-on: https://review.coreboot.org/c/coreboot/+/51625 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mathew King <mathewk@chromium.org>
2021-04-05mb/google/mancomb: Enable Chrome ECEric Lai
BUG=b:182211161 TEST=builds Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: Id1617be67bfc5d2f142358ae8a70c3e575a94c6d Reviewed-on: https://review.coreboot.org/c/coreboot/+/51489 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mathew King <mathewk@chromium.org>
2021-03-18mb/google/mancomb: Configure eSPI GPIOs in early stageEric Lai
BUG=b:182211161 TEST=builds Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: Ifa51705b3b5aab16f9cd2c11084220aafacd2774 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51494 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Mathew King <mathewk@chromium.org>
2021-03-18mb/google/mancomb: Configure early GPIOs in earliest stageEric Lai
Configure early GPIOs in verstage if it is run in PSP otherwise configure them in bootblock. BUG=b:182211161 TEST=builds Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: Ic1faeea59462319c1652c69034b4dde01669e13b Reviewed-on: https://review.coreboot.org/c/coreboot/+/51493 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Mathew King <mathewk@chromium.org>
2021-03-18mb/google/mancomb: Enable internal graphics deviceEric Lai
BUG=b:182211161 TEST=builds Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I0f5026b77513118a6c21eca78c9788c0bdc7ec6d Reviewed-on: https://review.coreboot.org/c/coreboot/+/51488 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Mathew King <mathewk@chromium.org>
2021-03-18mb/google/mancomb: Enable verstageEric Lai
BUG=b:182211161 TEST=builds Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: Ic07a3ac556637919742fcbe899ee3fdfac38bb94 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51492 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Mathew King <mathewk@chromium.org>
2021-03-15mb/google/mancomb: Configure non-native function GPIOsEric Lai
Follow 20210308 schematic. BUG=b:182211161 TEST=builds Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: Ib259f3defc606c373f5ccac5f022d93e9a5c1469 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51373 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mathew King <mathewk@chromium.org>
2021-03-15mb/google/mancomb: First pass GPIO configurationEric Lai
Follow 20210308 schematic. BUG=b:182211161 TEST=builds Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I1720ea8fec004d3ed3b3faaffa3b37dfcd710241 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51372 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mathew King <mathewk@chromium.org>
2021-03-13mb/amd/majolica,google/guybrush,google/mancomb: select HAVE_ACPI_RESUMERaul E Rangel
Since not all mainboards based on the Cezanne SoC have to support ACPI resume, select this option in the mainboard's Kconfig and not in the SoC's Kconfig. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I988276ccb5b61837d7f3f015d1d1aba783324b02 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51305 Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-11mb/google/mancomb: Add eSPI configurationEric Lai
BUG=b:182211161 TEST=builds Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: Ie3a3bb7526d734ae1936b8c4db43543b1174829d Reviewed-on: https://review.coreboot.org/c/coreboot/+/51370 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mathew King <mathewk@chromium.org>
2021-03-11mb/google/mancomb: Enable mancomb variantEric Lai
BUG=b:182211161 TEST=builds Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I554e7193494a4bbf005aaf2fb4efd6ded383fe07 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51369 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mathew King <mathewk@chromium.org>
2021-03-11mb/google/mancomb: Enable console UARTEric Lai
BUG=b:182211161 TEST=builds Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: Ia03169c524dd12b8e7803ea8039c0e98a2b069e9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51368 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mathew King <mathewk@chromium.org>
2021-03-11mb/google/mancomb: Enable ACPI tablesEric Lai
BUG=b:182211161 TEST=builds Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I623fd052404a08cf0adb471bb654622960f1aa62 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51367 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mathew King <mathewk@chromium.org>
2021-03-11mb/google/mancomb: Enable CONFIG_CHROMEOSEric Lai
BUG=b:182211161 TEST=builds Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I45dcaa8b430721f864d4e5d78ae60883175085c3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51366 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mathew King <mathewk@chromium.org>
2021-03-11mb/google/mancomb: Add stubs to configure GPIOsEric Lai
BUG=b:182211161 TEST=builds Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I7de5e4a4d2273d0ea5a84210ea0ce28d312eaa95 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51365 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mathew King <mathewk@chromium.org>
2021-02-19mb/google/mancomb: Add new mainboardMathew King
Mancomb is a new Google mainboard with an AMD Cezanne SOC. BUG=b:175143925 TEST=builds Change-Id: I1264f44a0b986f7f7c89ac7b42f1e4e4119a35e6 Signed-off-by: Mathew King <mathewk@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50007 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-14 17:43:23 +0000