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Convert lars to a variant of glados Skylake reference board:
- add lars-specific DPTF, EC config, GPIO config, Kconfig,
NHLT config, PEI data, VBT, SPD data, and devicetree
- add conditional generation of NHLT ACPI data for Maxim codec,
including override of OEM ID and OEM table ID
- remove existing lars board/directory
Test: build/boot google/lars, verify functionality unchanged
from pre-variant configuration
Change-Id: Iab37f1b92b0f3a5d99796f916a6fdcc14ce4eef4
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/27413
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Youness Alaoui <snifikino@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Combination of several commits from Chromium tree:
949037c [Lars: coreboot GPIO changes for EVT]
c286789 [Lars: Set USB Type A current limit to 2A]
0f1b26d [lars: set BOOT BEEP GPIO GPP_F_23 to output and Low]
4a0650d [Lili: Support touchscreen]
Disable unused GPIOs based on schematic and
adds GPIO mappings for HSJ_MIC_DET, PCH_BUZZER and AUDIO_INT_WAK.
Set GPIOs USB_A0_ILIM_SEL & USB_A1_ILIM_SEL low to enable 2A
charging from the USB Type-A port.
GPP_F_23 is set to NC currently and is floating, causing the on-board
speaker to have no audio or the audio has noise; set to output/low.
These commits bring lars' GPIO mapping in line with the Chromium tree.
Original-Change-Id: I3bf4aa8599255e5382d99810b4c83b4c97c648b6
Original-Change-Id: I328a8be22dc59492477cbe362a5d5b94aa80a397
Original-Change-Id: I253e55bf2b423363a00347778cabaa4184d85aec
Original-Change-Id: I761f7c5ea5fc7a173c07a8c37da1338a1b2cd269
Original-Signed-off-by: David Wu <David_Wu@quantatw.com>
Original-Signed-off-by: Naresh G Solanki <Naresh.Solanki@intel.com>
Original-Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Original-Reviewed-by: Shobhit Srivastava <shobhit.srivastava@intel.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: David Wu <david_wu@quantatw.com>
Original-Tested-by: Balaji Manigandan <balaji.manigandan@intel.com>
Original-Tested-by: Kuen Liu <kuen.liu@quantatw.com>
Change-Id: Ic2d188fbf913a11fbf6ad1f0eb3a5e72ba4cb1cf
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/23571
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Change 1760cd3e (soc/intel/skylake: Use common/block/gpio) updated all
skylake boards to use common gpio driver. Common gpio code
defines PAD_CFG_GPI without GPIO_DRIVER ownership. However, for
skylake PAD_CFG_GPI set GPIO_DRIVER ownership by default. This
resulted in Linux kernel failing to configure all GPIO IRQs since the
ownership was not set correctly. (Observed error in dmesg: "genirq:
Setting trigger mode 3 for irq 201
failed (intel_gpio_irq_type+0x0/0x110)")
This change fixes the above issue by replacing all uses of PAD_CFG_GPI
in skylake mainboards to PAD_CFG_GPI_GPIO_DRIVER.
BUG=b:67507004
TEST=Verified on soraka that the genirq error is no longer observed in
dmesg. Also, cat /proc/interrupts has the interrupts configured
correctly.
Change-Id: I7dab302f372e56864432100a56462b92d43060ee
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/21912
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Add the voltage tolerance GPIO attribute for configuring I2C/I2S buses
that are at 1.8V. This is currently done by passing in a value to FSP
but it is needed earlier than FSP if the I2C bus is used in verstage.
This does not remove the need for the FSP input parameter, that is
still required so FSP doesn't disable what has been set in coreboot.
The mainboards that are affected are updated in this commit.
This was tested by exercising I2C transactions to the 1.8V codec while
in verstage on the google/chell mainboard.
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Change-Id: I93d22c2e3bc0617c87f03c37a8746e22a112cc9c
Reviewed-on: https://review.coreboot.org/15103
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
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With gpio PADRSTCFG set to DEEP & GPIROUTIOXAPIC=1 & PADRSTCFG, causes
IRQ storm after S3 resume. GPIOs that fire IRQs via IOAPIC need to get
their logic reset over pltrst and hence configuring PADRSTCFG to
PLTRST to prevent IRQ strom after S3 resume.
BRANCH=glados
BUG=chrome-os-partner:50536
TEST=Build for kunimitsu and Boot on FAB4, no irq storm observed
after S3 resume.
Change-Id: I7f1ae90aed03778e7d6cb2d79de0efe9a6d9e20d
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: aff91da4feaf8f7e42cfeee756cf468288cbfd68
Original-Change-Id: I7cac60fb0144e090b8decb05d948b2d8d2f8deac
Original-Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/329453
Original-Commit-Ready: Naresh Solanki <naresh.solanki@intel.com>
Original-Tested-by: Naresh Solanki <naresh.solanki@intel.com>
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/331174
Original-Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Original-Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/13992
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Some trivial cleanup.
Change-Id: I866efc4939b5e036ef02d1acb7b8bb8335671914
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/13427
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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The write protect GPIO is not being configured early enough.
This is leading to coreboot reading incorrect value, and
writing the incorrect value in vboot shared file.
This is leading to "crossystem wpsw_boot" always returning 0
even with the write protect screw in place during boot.
BRANCH=none
BUG=chrome-os-partner:48292
TEST=Build and boot on lars
Change-Id: I28fbbd690ca6efb539422e9ba02f10e07cd35346
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: d229ba9d8934dcb5f22b27ce0ad27601ec87d6ff
Original-Change-Id: I64f2497a6bb3a50b0f58c67e2ab6751c4836fd89
Original-Signed-off-by: David Wu <David_Wu@quantatw.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/317130
Original-Commit-Ready: David Wu <david_wu@quantatw.com>
Original-Tested-by: David Wu <david_wu@quantatw.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/12966
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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At S0, S0ix and S3 LPC LAD signals are
floated at 400~500mV.
BRANCH=none
BUG=chrome-os-partner:48331
TEST=Build and boot on lars
Change-Id: I5582007e5caaf444740fa71c9761c27614aafee2
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: b855fd5834056a3f7d4aef91d634066006990a38
Original-Change-Id: I3a54f9f83f055e433cc1fea38169437ee7f9188f
Original-Signed-off-by: David Wu <David_Wu@quantatw.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/317071
Original-Commit-Ready: David Wu <david_wu@quantatw.com>
Original-Tested-by: David Wu <david_wu@quantatw.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/12965
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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Disable kepler device, it is removed and was not used on proto anyway.
BUG=none
BRANCH=none
TEST=build and boot on lars proto
Change-Id: I137b82b8dca23f5b40adcc6a056e77a4ff54d4d5
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 44d63453a9b31331d13d05f8f86d4218af0f0aa1
Original-Change-Id: Ib0892bf93b1d0cda1c0143d2b16cd58aeda83131
Original-Signed-off-by: David Wu <David_Wu@quantatw.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/315950
Original-Commit-Ready: David Wu <david_wu@quantatw.com>
Original-Tested-by: David Wu <david_wu@quantatw.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/12950
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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Adding support for Maxim 98357A audio amplifier.
Removed SSM4567 support from LARs.
BUG=chrome-os-partner:44481
BRANCH=None
TEST=Build & boot on LARs.
Verify audio playback works using MAXIM amplifiers.
Change-Id: I2cd8b20e936319b434017b6dd73d4739684d21d3
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 76cbc20826c884194a144f6b6bc644900e5d475d
Original-Change-Id: I1156096b6aa367c0b8d8e3952d92f0eb5cf2820f
Original-Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/314543
Original-Commit-Ready: Nicolas Boichat <drinkcat@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/12960
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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This patch enables GPP_B5 as ACPI_SCI for wake.
It also defines touchpad wake device in ACPI with GPE0_DW0_05 for _PRW.
BUG=none
BRANCH=none
TEST=emerge-lars coreboot
Change-Id: I2b65f6a37783ecdbdbc32ebe613243e042c865e9
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: ec5b629f920984564f12f2c09458ed300d031f69
Original-Change-Id: I9bd2b3595ae833fa5d07d97a7cda4a29041be837
Original-Signed-off-by: David Wu <David_Wu@quantatw.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/311890
Original-Commit-Ready: David Wu <david_wu@quantatw.com>
Original-Tested-by: David Wu <david_wu@quantatw.com>
Original-Reviewed-by: Shawn N <shawnn@chromium.org>
Reviewed-on: http://review.coreboot.org/12449
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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It encourages users from writing to the FSF without giving an address.
Linux also prefers to drop that and their checkpatch.pl (that we
imported) looks out for that.
This is the result of util/scripts/no-fsf-addresses.sh with no further
editing.
Change-Id: Ie96faea295fe001911d77dbc51e9a6789558fbd6
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/11888
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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This is based on kunimitsu with minor changes:
- update GPIOs based on schematic
- update SPD data for memory config
- disable ALS
BUG=None
TEST=emerge-lars coreboot
Change-Id: Id1c9edfe3cc665e90683344f1662de2e65caf766
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 3201aa573a77fcad3b6b1335d23eb4c2a09c1708
Original-Change-Id: Ifae446e4668569b6100b29bc1f52b0fea1df2952
Original-Signed-off-by: David Wu <David_Wu@quantatw.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/308283
Original-Commit-Ready: David Wu <david_wu@quantatw.com>
Original-Tested-by: David Wu <david_wu@quantatw.com>
Original-Reviewed-by: Bernie Thompson <bhthompson@chromium.org>
Original-Reviewed-by: Shawn N <shawnn@chromium.org>
Reviewed-on: http://review.coreboot.org/12201
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Change-Id: I95129e6f519735e236c9c13b16e21df25b9ea607
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/12200
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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