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path: root/src/mainboard/google/lars/devicetree.cb
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2017-08-25soc/intel/skylake: Add LPC and SPI lock down config optionSubrata Banik
This patch to provide new config options to perform LPC and SPI lock down either by FSP or coreboot. Remove EISS bit programming as well. TEST=Build and boot Eve and Poppy. Change-Id: If174915b4d0c581f36b54b2b8cd970a93c6454bc Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/21068 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-04-13soc/intel/skylake: Split AC/DC settings for Deep Sx configDuncan Laurie
Currently when enabling Deep S3 or Deep S5 it unconditionally gets enabled in both DC and AC states. However since using Deep S3 disables some expected features like wake-on-USB it is not always desired to enable the same state in both modes. To address this split the setting and add a separate config for Deep Sx in AC and DC states. All motherboards that set this config were updated, but there is no actual change in behavior in this commit. BUG=b:36723679 BRANCH=none TEST=This commit has no runtime visible changes, I verified on Eve that the Deep SX config registers are unchanged, and it compiles for all affected boards. Change-Id: I590f145847785b5a7687f235304e988888fcea8a Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/19239 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-02-22acpi: Add ACPI_ prefix to IRQ enum and struct namesFurquan Shaikh
This is done to avoid any conflicts with same IRQ enums defined by other drivers. BUG=None BRANCH=None TEST=Compiles successfully Change-Id: I539831d853286ca45f6c36c3812a6fa9602df24c Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/18444 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-28soc/intel/skylake: Add USB Port Over Current (OC) Pin programmingSubrata Banik
Program USB Overcurrent pins as per board schematics definition. BUG=none BRANCH=none TEST=Build and boot kunimitsu from USB device. Change-Id: I6aeb65953c753e09ad639469de7d866a54f42f11 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/17570 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-11-11soc/intel/skylake: move i2c voltage config to own variableAaron Durbin
In preparation of merging the lpss i2c config structures on apollolake and skylake move the i2c voltage variable to its own field. It makes refactoring things easier, and then there's no reason for a separate SoC specific i2c config structure. BUG=chrome-os-partner:58889 Change-Id: Ibcc3cba9bac3b5779351b673bc0cc7671d127f24 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/17347 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-10-07x86/acpi_device: Add support for GPIO output polarityFurquan Shaikh
Instead of hard-coding the polarity of the GPIO to active high/low, accept it as a parameter in devicetree. This polarity can then be used while calling into acpi_dp_add_gpio to determine the active low status correctly. BUG=chrome-os-partner:55988 BRANCH=None TEST=Verified that correct polarity is set for reset-gpio on reef. Change-Id: I4aba4bb8bd61799962deaaa11307c0c5be112919 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/16877 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-08-08skylake/devicetree: Add PIRQ Routing programmingBarnali Sarkar
Program PIRQ Routing with correct values, as done by FSP, and also in 'soc/intel/skylake/romstage/pch.c' file. If not done, these values get overridden by "0" during PxRC -> PIRQ programming in ramstage, in 'soc/intel/skylake/lpc.c' file pch_pirq_init()function. BUG=none BRANCH=none TEST=Build and boot kunimitsu Change-Id: Ibeb9a64824a71c253e45d6a1c6088abd737cf046 Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Reviewed-on: https://review.coreboot.org/16044 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2016-07-28skylake/devicetree: Add LPC EC decode rangeSubrata Banik
Define LPC decode ranges for EC communication. BUG=chrome-os-partner:55357 BRANCH=none TEST=Built and boot kunimitsu to ensure no EC timeout error Change-Id: Idefdd79e67e89a794195c6821fee16550d1eda53 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/15898 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-24google/lars: Move devices from mainboard.asl to devicetreeDuncan Laurie
Declare the mainboard attached devices in the devicetree and enable the provided device drivers by default to generate the ACPI objects for these devices. Then remove the static ACPI objects from the DSDT in mainboard.asl. This was tested on a Chell mainboard since I lack a lars device. Change-Id: Ifba6fc6589ddd54f4c85e8858f17997fbb4b6176 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/15316 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-06-09skylake: Move I2C bus configuration to separate structureDuncan Laurie
Move the existing I2C voltage configuration variable into a new structure that is equivalent, similar to how USB ports are configured. This is to make room for additional I2C configuration options like bus speed and whether to enable the bus in early boot which are coming in a subsequent commit. The affected mainboards are updated in this commit so it will build. Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Change-Id: Id2dea3df93e49000d60ddc66eb35d06cca6dd47e Reviewed-on: https://review.coreboot.org/15104 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-05-09soc/intel/skylake: Enable another VR mailbox command for certain boardsSubrata Banik
Command List: Send command for PS4 exit fails BUG=chrome-os-partner:52355 BRANCH=glados TEST=Build and boot lars and verify no hang during active idle CQ-DEPEND=CL:*257305 Change-Id: I9ffae71b1a38433ffc48ee7be7e2a13e69ad5b87 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 96f00e2d153f92339c378ce256eb7ce6824e3368 Original-Change-Id: I320ae154f3f7145811b57258ddb61b3beb584273 Original-Signed-off-by: Subrata Banik <subrata.banik@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/341330 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/14688 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-03-01Skylake boards: Enabling HWP (hardware P state control)Subrata Banik
This patch provides config options to enable/disable Intel SST (Speed Shift Technology). BUG=chrome-os-partner:47517 BRANCH=None TEST=Booted kunimitsu/lars, verified HWP driver load successfully. CQ-DEPEND=CL:313107 Change-Id: I9419a754384f96d308a5ac2ad90bbb519edc296e Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Commit-Id: 5efb7978e9d3ca9a709a4793ad213423a1c3c45d Original-Change-Id: I328b074b4f56ebe3caa8952ce3df7f834c1cf40f Original-Signed-off-by: Robbie Zhang <robbie.zhang@intel.com> Original-Signed-off-by: Subrata Banik <subrata.banik@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/326650 Original-Tested-by: Wenkai Du <wenkai.du@intel.com> Original-Reviewed-by: Benson Leung <bleung@chromium.org> Reviewed-on: https://review.coreboot.org/13843 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-02-09google/lars: Set I2C[4] port voltage to 1.8vdavid
As the audio card needs 1.8V I2C operation. This patch adds entry into devicetree.cb to set I2C port 4 operate at 1.8V. TEST=Built & booted lars board. Verified that I2C port 4 is operating at 1.8V level Change-Id: Ia77841a26d024785d53251ca4b17afcf77f36a5b Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: e431e7acd85f6d7bf9d47f54ed41c48b8276071c Original-Change-Id: Iccc85a5e3bbf2b5362665036e1294a6635e38fbe Original-Signed-off-by: David Wu <David_Wu@quantatw.com> Original-Reviewed-on: https://chromium-review.googlesource.com/321000 Original-Commit-Ready: David Wu <david_wu@quantatw.com> Original-Tested-by: David Wu <david_wu@quantatw.com> Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/13627 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-04skylake boards: disable ACPI PM TimerArchana Patni
These devicetree patches set the ACPI PM Disabled variable to 1. This will disable the ACPI PM timer and remove from FADT table. BRANCH=none BUG=chrome-os-partner:48646 TEST=Build for skylake board with the PmTimerDisabled policy in devicetree set to 1. iotools mmio_read32 0xfe0000fc should return 0x2. cat /sys/devices/system/clocksource/clocksource0/available_clocksource should list only "tsc hpet". acpi_pm should be removed from this list. Change-Id: Ia66f37e13f0f2f527651418b8b5c337b56c25c7f Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: db3e8130495038850c7034b89701b4a5fcf88dce Original-Change-Id: Ib1b876cfa361b8cbdde2f9e212e3da4fd724e498 Original-Signed-off-by: Archana Patni <archana.patni@intel.com> Original-Signed-off-by: Subramony Sesha <subramony.sesha@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/319362 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/13589 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-01-22intel/skylake: PL2 override changespchandri
Override the default PL2 values with ones recommended by Intel. BUG=chrome-os-partner:49292 BRANCH=glados TEST=MMIO 0x59A0[14-0] to find PL1 value (0x78) / 8 Watts = 15W MMIO 0x59A0[15] to find PL1 enable/disable = Disable MMIO 0x59A0[46-32] to find PL2 Value (0xC8) / 8 Watts = 25W Here PL2 is set to 25W and PL1 is disabled. CQ-DEPEND=CL:321392 Change-Id: I338b1d4879ae1b5f760e3c1d16e379a2baa1c965 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: fa6a115227385bef44abfacf58af306c16ed478a Original-Change-Id: I3bfc50256c9bdd522c984b11faf2903d7c44c81f Original-Signed-off-by: pchandri <preetham.chandrian@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/322454 Original-Commit-Ready: Venkateswarlu V Vinjamuri <venkateswarlu.v.vinjamuri@intel.com> Original-Tested-by: Venkateswarlu V Vinjamuri <venkateswarlu.v.vinjamuri@intel.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Preetham Chandrian <preetham.chandrian@intel.com> Original-Reviewed-by: Venkateswarlu V Vinjamuri <venkateswarlu.v.vinjamuri@intel.com> Reviewed-on: https://review.coreboot.org/13071 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-19google/lars: Enable eMMC HS400 modedavid
Kingston eMMC can now run under HS400 mode. BUG=chrome-os-partner:48017 BRANCH=none TEST=run consecutive boot 100 times on Lars proto Kingston SKU, and MMC errors didn't happen. Change-Id: I3c16db6111273fbbabbfba1c315edc780fe23525 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: ac474bd7bd33f11904a27691e9eb61bdaf212c6b Original-Change-Id: I9e47b6ba64ac94acff7673fca86fa62bfb30edd9 Original-Signed-off-by: David Wu <David_Wu@quantatw.com> Original-Reviewed-on: https://chromium-review.googlesource.com/320194 Original-Commit-Ready: David Wu <david_wu@quantatw.com> Original-Tested-by: David Wu <david_wu@quantatw.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/13004 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-01-19google/lars: Enable SaGv featuredavid
This change enables SaGv feature for skylake platform. As a result of this patch the skylake platform will train memory at both low & high frequency points. This will be used to dynamically scale the work point (voltage/frequencies). The value "3" here means enable. Following is the table for same. 0=Disabled (SaGv disabled) 1=FixedLow (Fixed to low frequency) 2=FixedHigh (Fixed to High frequency) 3=Enabled( SaGv Enabled.Dynamically changes) BRANCH=None BUG=chrome-os-partner:48534 TEST=Build and boot lars Change-Id: I82b1a428d2d3dce47f46de576f677cf2249b6b5d Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 8e252123cc73543d0f1b320af9d8873f99a45ab1 Original-Change-Id: I1a545ff2f38df23964378c0d833e29006b2c5557 Original-Signed-off-by: David Wu <David_Wu@quantatw.com> Original-Reviewed-on: https://chromium-review.googlesource.com/320022 Original-Commit-Ready: David Wu <david_wu@quantatw.com> Original-Tested-by: David Wu <david_wu@quantatw.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Subrata Banik <subrata.banik@intel.com> Original-Reviewed-by: Haridhar Kalvala <haridhar.kalvala@intel.com> Reviewed-on: https://review.coreboot.org/13002 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-19google/lars: Enable FspSkipMpInit tokenBarnali Sarkar
MP init is already handled in coreboot, but it is also part of FSP FSP has a implemented a provision to allow FSP to skip MP init and let coreboot handle it. BRANCH=none BUG=chrome-os-partner:44805 TEST=Build and booted in Lars with SkipMpInit enabled from CB CQ-DEPEND=CL:319353 Change-Id: Ib35d9072b883592d22466dfeb1fd45403c0479d4 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 91cf59ea7865568eca2ce242d81c4c486076d5ac Original-Change-Id: Ibb46fc6bc7e862c9ea8bc9f9b0d508c3707282a2 Original-Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/319257 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/12999 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-18google/lars: Add VrConfig UPD parametersdavid
Follow kunimitsu setting of https://chromium-review.googlesource.com/#/c/313068/ BRANCH=none BUG=chrome-os-partner:48459 TEST=Build and boot in lars Change-Id: Iffa9e1307f478b1d72befd3e5af71e7d40bb55ef Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 6c669014d0773d6790656dd6f957d2c860d00781 Original-Change-Id: I615d53a33ad8e750d4382e2a9ec397c5b6ff55e1 Original-Signed-off-by: David Wu <David_Wu@quantatw.com> Original-Reviewed-on: https://chromium-review.googlesource.com/317222 Original-Commit-Ready: David Wu <david_wu@quantatw.com> Original-Tested-by: David Wu <david_wu@quantatw.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/12978 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-18skylake boards: csme: add p2sb device and hecienabled devicetree variableArchana Patni
The HeciEnabled decides the state of Heci1 at end of boot. Setting to 0 (default) disables Heci1 and hides the device from OS. It internally uses the FSP Psf Unlock policy to disable the Heci1. It also adds the p2sb device in the devicetree which is necessary for hiding and unhiding the device. BRANCH=none BUG=chrome-os-partner:45618 TEST=build for kunimitsu. CQ-DEPEND=CL:*238451 Change-Id: Ieba2ab3b4ac518cce8371069028170ba99aaf079 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: cbefe9d6e9a981594534d346be67a5cd94483d05 Original-Change-Id: I8c95b5b9b28ba8441ca031f4e9ec523d913990d6 Original-Signed-off-by: Archana Patni <archana.patni@intel.com> Original-Signed-off-by: Subramony Sesha <subramony.sesha@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/311913 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/12977 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-17google/lars: Remove/Disable Wake on landavid
Remove the WakeConfigWolEnableOverride to disable WOL override configuration in the General PM Configuration B (GEN_PMCON_B) register BRANCH=none BUG=none TEST=Build and boot on lars Change-Id: I48d3b706517b6ea6bda44800f61bb11da64503fb Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: eab69f2d725df739e5e0e5901a581ad58732cdf9 Original-Change-Id: I42c5a87150638171526ee67f194c1cd9d155203b Original-Signed-off-by: David Wu <David_Wu@quantatw.com> Original-Reviewed-on: https://chromium-review.googlesource.com/317080 Original-Commit-Ready: Nicolas Boichat <drinkcat@chromium.org> Original-Tested-by: David Wu <david_wu@quantatw.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/12962 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-16google/lars: Add new configuration parametersdavid
Follow kunimitsu setting of https://chromium-review.googlesource.com/#/c/313309/ BRANCH=none BUG=none TEST=Build and boot on lars. Change-Id: I77a4454b3702dc58dc70a7b981b25a656e97f534 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 9c390322b4c770a0206549257dd34d1ef1242cc3 Original-Change-Id: I612e799433a396a6cce5742adb6de72a305b5df1 Original-Signed-off-by: David Wu <David_Wu@quantatw.com> Original-Reviewed-on: https://chromium-review.googlesource.com/316270 Original-Commit-Ready: David Wu <david_wu@quantatw.com> Original-Tested-by: David Wu <david_wu@quantatw.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/12954 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-16google/lars: Disable SD 3.0 Controller [D30:F6]Subrata Banik
LARs design don't have SD Connector over native SD Controller. BUG=chrome-os-partner:48190 BRANCH=None TEST=Build & boot LARs. Use "lspci" doesn't list 0x1E:06 device in list. CQ-DEPEND=CL:315420 Change-Id: Idff7243a6aaf4b8d5f49e4bf215a77131f716485 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: ca769138b97b404598c4a6bfa6c2ff5c1c3ec896 Original-Change-Id: I71416ac89a8c91ab272d6737d1b46c8045567e17 Original-Signed-off-by: Subrata Banik <subrata.banik@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/315423 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/12947 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-15google/lars: Disable kepler devicedavid
Disable kepler device, it is removed and was not used on proto anyway. BUG=none BRANCH=none TEST=build and boot on lars proto Change-Id: I137b82b8dca23f5b40adcc6a056e77a4ff54d4d5 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 44d63453a9b31331d13d05f8f86d4218af0f0aa1 Original-Change-Id: Ib0892bf93b1d0cda1c0143d2b16cd58aeda83131 Original-Signed-off-by: David Wu <David_Wu@quantatw.com> Original-Reviewed-on: https://chromium-review.googlesource.com/315950 Original-Commit-Ready: David Wu <david_wu@quantatw.com> Original-Tested-by: David Wu <david_wu@quantatw.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/12950 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-15google/lars: Disable eMMC HS400 capabilitydavid
BUG=chrome-os-partner:48017 BRANCH=none TEST=Verify eMMC is working fine. Change-Id: If02d969029a9eb8d05148ee958fd34225c8a88fe Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: dca385c2bbf11c9eb79fd0761b2b335f8fdff491 Original-Change-Id: I371036426f17530409b46af285b18f4522739ee7 Original-Signed-off-by: David Wu <David_Wu@quantatw.com> Original-Reviewed-on: https://chromium-review.googlesource.com/313912 Original-Commit-Ready: David Wu <david_wu@quantatw.com> Original-Tested-by: David Wu <david_wu@quantatw.com> Original-Reviewed-by: David Wu <david_wu@quantatw.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/12618 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2015-10-28google/lars: Add new mainboarddavid
This is based on kunimitsu with minor changes: - update GPIOs based on schematic - update SPD data for memory config - disable ALS BUG=None TEST=emerge-lars coreboot Change-Id: Id1c9edfe3cc665e90683344f1662de2e65caf766 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 3201aa573a77fcad3b6b1335d23eb4c2a09c1708 Original-Change-Id: Ifae446e4668569b6100b29bc1f52b0fea1df2952 Original-Signed-off-by: David Wu <David_Wu@quantatw.com> Original-Reviewed-on: https://chromium-review.googlesource.com/308283 Original-Commit-Ready: David Wu <david_wu@quantatw.com> Original-Tested-by: David Wu <david_wu@quantatw.com> Original-Reviewed-by: Bernie Thompson <bhthompson@chromium.org> Original-Reviewed-by: Shawn N <shawnn@chromium.org> Reviewed-on: http://review.coreboot.org/12201 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-10-28google/lars: Copy from intel/kunimitsudavid
Change-Id: I95129e6f519735e236c9c13b16e21df25b9ea607 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/12200 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-02 04:21:54 +0000