| Age | Commit message (Collapse) | Author |
|---|
|
Done with sed and God Lines. Only done for C-like code for now.
Change-Id: I377ee2c9dfa3113f88237bd6ea79031a79f18ad5
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40180
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
They're listed in AUTHORS and often incorrect anyway, for example:
- What's a "Copyright $year-present"?
- Which incarnation of Google (Inc, LLC, ...) is the current
copyright holder?
- People sometimes have their editor auto-add themselves to files even
though they only deleted stuff
- Or they let the editor automatically update the copyright year,
because why not?
- Who is the copyright holder "The coreboot project Authors"?
- Or "Generated Code"?
Sidestep all these issues by simply not putting these notices in
individual files, let's list all copyright holders in AUTHORS instead
and use the git history to deal with the rest.
Change-Id: I09cc279b1f75952bb397de2c3f2b299255163685
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39607
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
|
|
Configure and enable GPIO for speaker amp max98357a.
BUG=b:117254418
TEST=Build pass and verified on kukui p1 board
BRANCH=None
Change-Id: I97655702dff402245326d2eff71fae0e336df9f5
Signed-off-by: Jiaxin Yu <jiaxin.yu@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32459
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
|
|
Write protection (get_write_protect_state) was hard-coded to 0 and
should be fixed to read from correct GPIO (PERIPHERAL_EN0 from
schematics).
BUG=b:130681408
TEST=make -j; boots on Kukui Rev2.
BRANCH=None
Change-Id: I75b98b1d587abe5e8cdf3df28ea661bc1ffa19f9
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32336
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: You-Cheng Syu <youcheng@google.com>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-by: Joel Kitching <kitching@google.com>
|
|
Asserting GPIO PERIPHERAL_EN8 will send a signal to EC to trigger a HW
reset for SoC and H1.
BUG=b:80501386
BRANCH=none
TEST=emerge-kukui coreboot; manually verified the do_board_reset() on
Kukui P1
Change-Id: I9afad84af2031a766bc08fc76c8b5f55588c453a
Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/31118
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Init SPI bus 0 to connect TPM, configure interrupt type of GPIO CR50_IRQ,
implement tis_plat_irq_status(), and set up chromeos GPIO table for TPM
interrupt.
BUG=b:80501386
BRANCH=none
Test=Boots correctly on Kukui.
Change-Id: Ieaa6ae65fbfb5ab6323e226e8171dd7a992c3a39
Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/29192
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
|
|
Set up EC_IN_RW GPIO to boot depthcharge. Without this patch,
depthcharge will fail to tell if the EC firmware is RW.
BUG=b:80501386
BRANCH=none
TEST=Boots correctly on Kukui and see in logs, that depthcharge detects
EC_IN_RW GPIO.
Change-Id: Icb39d663f65b72e0ad54059c9590d9693106ee25
Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com>
Reviewed-on: https://review.coreboot.org/28670
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Set up EC interrupt GPIO to boot depthcharge. Without this patch,
depthcharge will fail to detect EC interrupt GPIO.
BUG=b:80501386
BRANCH=none
TEST=Boots correctly on Kukui and see in logs, that depthcharge detects
EC interrupt GPIO.
Change-Id: I0ec2c70c189a059219954e0384aaf98995285728
Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com>
Reviewed-on: https://review.coreboot.org/28250
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Julius Werner <jwerner@chromium.org>
|
