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Write protection (get_write_protect_state) was hard-coded to 0 and
should be fixed to read from correct GPIO (PERIPHERAL_EN0 from
schematics).
BUG=b:130681408
TEST=make -j; boots on Kukui Rev2.
BRANCH=None
Change-Id: I75b98b1d587abe5e8cdf3df28ea661bc1ffa19f9
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32336
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: You-Cheng Syu <youcheng@google.com>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-by: Joel Kitching <kitching@google.com>
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For Kukui CR50_IRQ pin, we're going to replace external pull-up with
internal pull-up. This change won't break older boards, so we can just
always do that when setting up GPIOs.
BUG=b:124821269
BRANCH=none
TEST=Waveform looks correct.
Change-Id: Ib1a90dce583a6aa0cec8ac8ba96d1362f50c16a8
Signed-off-by: You-Cheng Syu <youcheng@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32116
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
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In payloads, we didn't set GPIO modes. We have to set up GPIO mode in
coreboot for payloads.
BUG=b:80501386
BRANCH=none
TEST=HW reboot works in depthcharge
Change-Id: Ibd2c6c071871edc59497fbb245cdbec6a814f621
Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/31148
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Init SPI bus 0 to connect TPM, configure interrupt type of GPIO CR50_IRQ,
implement tis_plat_irq_status(), and set up chromeos GPIO table for TPM
interrupt.
BUG=b:80501386
BRANCH=none
Test=Boots correctly on Kukui.
Change-Id: Ieaa6ae65fbfb5ab6323e226e8171dd7a992c3a39
Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/29192
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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Get recovery mode switch from EC and pass it to payload.
BUG=b:80501386
BRANCH=none
Test: Boots correctly on Kukui.
Change-Id: Ib92afca885e5a97ec4646f55f2279ef56a61af5a
Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com>
Reviewed-on: https://review.coreboot.org/29190
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
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Set up EC_IN_RW GPIO to boot depthcharge. Without this patch,
depthcharge will fail to tell if the EC firmware is RW.
BUG=b:80501386
BRANCH=none
TEST=Boots correctly on Kukui and see in logs, that depthcharge detects
EC_IN_RW GPIO.
Change-Id: Icb39d663f65b72e0ad54059c9590d9693106ee25
Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com>
Reviewed-on: https://review.coreboot.org/28670
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Set up EC interrupt GPIO to boot depthcharge. Without this patch,
depthcharge will fail to detect EC interrupt GPIO.
BUG=b:80501386
BRANCH=none
TEST=Boots correctly on Kukui and see in logs, that depthcharge detects
EC interrupt GPIO.
Change-Id: I0ec2c70c189a059219954e0384aaf98995285728
Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com>
Reviewed-on: https://review.coreboot.org/28250
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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BUG=b:80501386
BRANCH=none
TEST=timer and uart work fine
Change-Id: I08644892d34925574f791b000b0035d5afad7022
Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com>
Reviewed-on: https://review.coreboot.org/26722
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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