| Age | Commit message (Collapse) | Author |
|---|
|
MT8183 only allows booting from eMMC, so we have to do eMMC emulation
from an external source, for example EC, which makes the size of
bootblock very important.
This CL moves some initialization steps from bootblock to verstage. This
will save us about 2700 bytes (before compression) / 1024 bytes (after
LZ4 compression) in bootblock. In case of CONFIG_VBOOT is disabled,
these initialization steps will be done in romstage.
BRANCH=none
BUG=b:120588396
TEST=manually boot into kernel
Change-Id: I9968d88c54283ef334d1ab975086d4adb3363bd6
Signed-off-by: You-Cheng Syu <youcheng@google.com>
Reviewed-on: https://review.coreboot.org/c/30331
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
|
|
MT8183 only allows booting from eMMC, so we have to do eMMC emulation
from an external source, for example EC, which makes the size of
bootblock very important.
This CL adds a new function mt8183_early_init, which includes all
initializations that should be done in early stages. All mainboards
using MT8183 should manually call it in either bootblock or verstage.
BRANCH=none
BUG=b:120588396
TEST=manually boot into kernel
Change-Id: I35d7ab875395da913b967ae1f7b72359be3e744a
Signed-off-by: You-Cheng Syu <youcheng@google.com>
Reviewed-on: https://review.coreboot.org/c/31024
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
|
|
We have a pin from AP to EC, called AP_IN_SLEEP_L (SRCLKENA0 on AP side,
pad R23) that is supposed to be high in S0, and low in S3 (and X/don't
care in S5).
This should be set as early as possible in bootblock.
BUG=b:113367227
TEST=make; boots and verified AP_IN_SLEEP_L GPIO is high.
BRANCH=None
Change-Id: Icd59fa366c162e7443b8932a851e65f110f551ab
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://review.coreboot.org/28585
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@google.com>
|
|
Set EC SPI bus config and init SPI bus according to the config.
BUG=b:80501386
BRANCH=none
TEST=EC is not working yet. This makes depthcharge go forward a little.
Change-Id: Id9209b6429417430cfcf7f5a5a1659e7e4bc7866
Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com>
Reviewed-on: https://review.coreboot.org/28251
Reviewed-by: Joel Kitching <kitching@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Set up EC interrupt GPIO to boot depthcharge. Without this patch,
depthcharge will fail to detect EC interrupt GPIO.
BUG=b:80501386
BRANCH=none
TEST=Boots correctly on Kukui and see in logs, that depthcharge detects
EC interrupt GPIO.
Change-Id: I0ec2c70c189a059219954e0384aaf98995285728
Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com>
Reviewed-on: https://review.coreboot.org/28250
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Julius Werner <jwerner@chromium.org>
|
|
On kukui board, the eMMC is routed to EC for boot ROM emulation when
loading bootblock, and should be set back to real eMMC as early as
possible after bootblock is loaded.
BUG=b:80501386
TEST=make; boots and verified BOOTBLOCK_EN_L GPIO is enabled.
BRANCH=None
Change-Id: Ifefb2e26ed048c38595907cc0875757410129828
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://review.coreboot.org/27601
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
This patch sets SPI flash related configs and inits SPI bus 1 to
support SPI NOR flash.
BUG=b:80501386
BRANCH=none
TEST=Boots correctly on Kukui
Change-Id: I1a18a456f41a7c7daec954e961c9fbee3650493d
Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com>
Reviewed-on: https://review.coreboot.org/27499
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
|
