coreboot.git - my copy of coreboot

Age	Commit message (Collapse)	Author
2018-08-28	google/kukui: Init SPI bus for EC	Tristan Shieh
	Set EC SPI bus config and init SPI bus according to the config. BUG=b:80501386 BRANCH=none TEST=EC is not working yet. This makes depthcharge go forward a little. Change-Id: Id9209b6429417430cfcf7f5a5a1659e7e4bc7866 Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com> Reviewed-on: https://review.coreboot.org/28251 Reviewed-by: Joel Kitching <kitching@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-27	google/kukui: Add SPI NOR support	Tristan Shieh
	This patch sets SPI flash related configs and inits SPI bus 1 to support SPI NOR flash. BUG=b:80501386 BRANCH=none TEST=Boots correctly on Kukui Change-Id: I1a18a456f41a7c7daec954e961c9fbee3650493d Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com> Reviewed-on: https://review.coreboot.org/27499 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-06-11	google/kukui: Add MediaTek MT8183 reference board	Tristan Shieh
	BUG=b:80501386 BRANCH=none TEST=timer and uart work fine Change-Id: I08644892d34925574f791b000b0035d5afad7022 Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com> Reviewed-on: https://review.coreboot.org/26722 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>