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Add Careena variant, based on the grunt board.
BUG=b:80106042
TEST=Build Careena
Change-Id: I87a24f6d8115aacf5b21181f3820cf2718ad252a
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/26524
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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The chrmoeos.fmd file will be common across variants, so move it out of
of grunt directory and into the variants/baseboard directory.
BUG=b:80106042
TEST=Build grunt
Change-Id: I259d85f60c5e19e00f7d9149542bcfdcc6dfaf4f
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/26656
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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The SPD files will be common to many of the mainboards, so move them out
of grunt and into the variants/baseboard directory.
BUG=b:80106042
TEST=Build grunt, make sure spd.bin is the same.
Change-Id: I53975a46a8c7d7e519bb6f7ef6ccd0b817ac4c92
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/26523
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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This won't actually get called yet since the GPIO pin has not been
configured as SMI.
BUG=b:80295434
TEST=grunt: Made sure events could be processed.
Change-Id: I189e26196e4543b3e34bff5d9df8566eff07d585
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/26546
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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The default interrupt control for GPIO pins within stoneyridge is for
edge triggered, high. However, sometimes these need to change, or maybe
the interrupt needs to be reported or delivered. This was the case of
platform grunt, where the interrupt related bits were being changed
afterwards. Ideally all the bits should be programmed through the same
procedure. Create several PAD_INT definitions (for general configuration,
for trigger configuration and for interrupt type configuration) and change
function sb_program_gpios() to accept the output from PAD_INT_XX and
program all the necessary bits while keeping compatibility with other
PAD_XX definitions.
BUG=b:72875858
TEST=Add code to report GPIO and interrupt configuration, build grunt and
record a baseline. Add new code, rebuild grunt and record a test output.
Compare baseline against test, there should be no change in GPIO or
interrupt programming.
Remove code that reports GPIO/interrupt configuration.
Change-Id: I3457543bdf64ec757fd82df53c83fdc1d03c1f22
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/25758
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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GPIO APU_BIOS_FLASH_WP_L is first read in ROM stage to determine the
state of the BIOS FLASH Write Protect signal at boot.
The result of this read accumulated in the vboot state that's passed on
to the upper layers of the stack.
Therefore this GPIO must be configured as a "reset stage" GPIO, not
a "RAM" stage GPIO.
BUG=b:79866233
TEST=firmware_WriteProtect
Change-Id: I1d96ab4bbfeaf9db9f74cf0c58cbab2104079bf7
Signed-off-by: Daniel Kurtz <djkurtz@chromium.org>
Reviewed-on: https://review.coreboot.org/26498
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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_SWS is the recommended method of wake source retrieval. Now that PM1I and
GPEI are available at NVS, add the method _SWS to kahlee/grunt ACPI code.
BUG=b:76020953
TEST=Build grunt
Change-Id: I5930438af40e6f9177462582cafb65401d9c60f4
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/26217
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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Add the unused space to the RW_LEGACY area.
BUG=b:79433466
TEST=None
Change-Id: I897d1dcf75466fe9bdb814c8a9db0fecb5c42af6
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/26221
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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The firmware_Mosys FAFT test does not allow RW_SECTION_A, RW_SECTION_B or
RW_SHARED to be 0-sized, nor located at offset 0x00000000.
Swap UNIFIED_MRC_CACHE and RW_SECTION_A to pass this test.
BUG=b:79865447
TEST=test_that -b grunt ${IP} firmware_Mosys
Change-Id: If60919fd998ac786d58a5a258d7b5ded727db64b
Signed-off-by: Daniel Kurtz <djkurtz@chromium.org>
Reviewed-on: https://review.coreboot.org/26356
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Lower the amount of UMA memory to 32MB at AMD's request.
TEST=none
BUG=b:79906569
Change-Id: Ib1365dc38850b4b92c944ff95534573addbe4362
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/26383
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Lower the amount of UMA memory to 32MB at AMD's request.
TEST=boot Grunt, try S3
BUG=b:79906569
Change-Id: I5af038688b38b53c94b8265823eeee0f37980522
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/26382
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Use of device_t has been abandoned in ramstage.
Change-Id: I8e549e4222ae2ed6b9c46f81c5b5253e8b227ee8
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26086
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Change OEM ID values to 6 characters to fix error compiling with IASL
version 20180427.
Also update table creator to 8 characters from 7.
Change-Id: Id6c9a7b08dc4a9efeb69011393e29aa5a6bc54c4
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/26047
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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Using da7219 mclk-name property, oscout system clock is linked
to da7219 mclk. da7219 then handles enabling/disabling of the clk.
BUG=b:74570989
TEST=Tested clock enable/disable in kernel driver
Change-Id: I298b0ce5d2c40daadeb5d68f9cb595a965272021
Signed-off-by: Akshu Agrawal <akshu.agrawal@amd.com>
Reviewed-on: https://review.coreboot.org/25920
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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This reverts commit edf2f59b1d93a1bc9161a67d3c00a9a05fa8519a.
(google/kahlee: Resume on AC insertion)
The requirement to wake on AC insert is just to wake enough to charge,
not to wake the entire system.
BUG=b:77602394
TEST=None
Change-Id: I0ee709183b1605c1efc0fce673db512fac66adfa
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/26014
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Daniel Kurtz <djkurtz@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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It's very confusing trying to find the google platform names, because
they seem all unsorted in Kconfig. They're actually sorted according
to the variant name, but previously, that was impossible to tell.
- Add a comment to the top of variants in Kconfig.name
- Inset each variant name. If you start a prompt with whitespace,
it gets ignored, so after trying various ways to indent, the arrow
was the option I thought looked the best.
It now looks like this:
*** Beltino ***
-> Mccloud (Acer Chromebox CXI)
-> Monroe (LG Chromebase 22CV241 & 22CB25S)
-> Panther (ASUS Chromebox CN60)
-> Tricky (Dell Chromebox 3010)
-> Zako (HP Chromebox G1)
Butterfly (HP Pavilion Chromebook 14)
Chell (HP Chromebook 13 G1)
Cheza
*** Cyan ***
Change-Id: I35cb16b040651cd1bd0c4aef98494368ef5ca512
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/26020
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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- Add raydium controller
- Update elan controller with reset and enable GPIOs.
- Enable 'probed' so Linux will check which controller is being used.
BUG=b:78929054
TEST=Both elan and raydium touchscreen controllers work
Change-Id: I3bd9912a4b1edc7bf1075cb649afa3eab5dca458
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://review.coreboot.org/25998
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Set SPI Fast Read to 100MHz and Dual Read IO mode to speed up
the boot process by over a half second. Also, increase the Normal
Read speed to 33MHz as supported by the W25Q128FW.
BUG=b:70558952
TEST=Run cbmem -t to get boot times.
Change-Id: I616a96526ed90bb4ab0c9c6b78787799faa02633
Signed-off-by: Marc Jones <marc.jones@scarletltd.com>
Reviewed-on: https://review.coreboot.org/25970
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Martin Roth <martinroth@google.com>
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Enable this driver along with power saving.
BUG=b:73726008
BRANCH=none
TEST=boot and see this message:
BayHub BH720: Power-saving enabled 110103
From linux:
$ iotools pci_read32 2 0 0 0x90
0x00110103
Change-Id: I850e923f73e01fe629d66ad61b65afa58035845c
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-on: https://review.coreboot.org/25967
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Remove VBOOT_VBNV_CMOS from the mainboard. It is selected in the
stoneyridge Kconfig.
BUG=b:77347873
TEST=Manually clear CMOS and check coreboot restores VBNV from flash.
Change-Id: I30e517e06ab9d8f7d4a93bf82f12726756c44966
Signed-off-by: Marc Jones <marc.jones@scarletltd.com>
Reviewed-on: https://review.coreboot.org/25844
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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Add RW_NVRAM area to FMAP for VBOOT_VBNV_CMOS_BACKUP_TO_FLASH support.
BUG=b:77347873
TEST=Manually clear CMOS and check coreboot restores VBNV from flash.
Change-Id: Id8c6f54634b94bf6ae3755a827e80d0862a42dd2
Signed-off-by: Marc Jones <marc.jones@scarletltd.com>
Reviewed-on: https://review.coreboot.org/25843
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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Set the SPI speed for Normal, Fast, AltIO, and TPM in bootblock.
This setup is needed when moving AGESA out of the bootblock. It sets the
SPI bus speed of the TPM access in verstage.
BUG=b:70558952
TEST=Boot with AGESA moved out of the bootblock.
Change-Id: Ida77d78eb1f290e46b57a46298400ed6c8015e2c
Signed-off-by: Marc Jones <marc.jones@scarletltd.com>
Reviewed-on: https://review.coreboot.org/25756
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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The grunt touchpad interrupt can be used as a wake source. For grunt,
the touchpad interrupt uses GPIO5 which corresponds to GEVENT7.
BUG=b:77602771
TEST=In OS: # cat /proc/acpi/wakeup
=> D015 S3 *enabled i2c:i2c-ELAN0000:00
TEST=powerd_dbus_suspend, touching touchpad (> 1 sec) wakes from S3.
Change-Id: I510642108a1257f6601f18c77cf3107573427f39
Signed-off-by: Daniel Kurtz <djkurtz@chromium.org>
Reviewed-on: https://review.coreboot.org/25827
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The grunt EC uses GPIO24 (EC_PCH_WAKE_L) to signal wake-up events to the AP.
On Stoney, GPIO24 maps to GEVENT (GPE) 15.
The kahlee EC uses GPIO2 (EC_PCH_WAKE_L) to signal wake-up events to the AP.
On Stoney, GPIO2 maps to GEVENT (GPE) 8.
BUG=b:78461678
TEST=powerd_dbus_suspend, tap any key on keyboard wakes from S3.
TEST=sign in, EC: lidclose, EC: lidopen => system wakes from S3.
Change-Id: Ib1809740837e686992ff70b81933159a5dff7595
Signed-off-by: Daniel Kurtz <djkurtz@chromium.org>
Reviewed-on: https://review.coreboot.org/25816
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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On the kahlee variant, EC_SMI_ODL is connected to GPIO6, which uses
GEVENT 10 (GPE10). Fix this up, and also clean up the EC_*_GPI
definition format a bit to match the format in the baseboard/gpio.h.
BUG=b:78461678
TEST=build coreboot for kahlee
Change-Id: I9445efbc02559c2a7c90f67bcb0154b04b03a1aa
Signed-off-by: Daniel Kurtz <djkurtz@chromium.org>
Reviewed-on: https://review.coreboot.org/25826
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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When GPIO tables were created, there was no study on which pins had to be
programmed ASAP and which could be programmed later. Execute such study and
move all non-critical gpios from reset to late.
BUG=b:76097508
TEST=Build and boot grunt to OS, test OS for lost functionality (WIFI, video
playback, track pad, keyboard).
Change-Id: Icbc9370050d619800026035caaac3e89536a460a
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/25395
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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Instead of writing out '__attribute__((weak))' use a shorter form.
Change-Id: If418a1d55052780077febd2d8f2089021f414b91
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/25767
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
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The GPIO definition structure has evolved to a point where it's no longer
specific to stoneyridge, though probably still specific to AMD. Therefore,
rename the GPIO declaration structure removing stoneyridge from it.
BUG=b:72875858
TEST=Build kahlee, grunt, gardenia.
Change-Id: Ib034d3f7840c36ee8f5c5384241d7326d3fe5543
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/25726
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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With the exception of code that deals directly or indirectly with AGESA,
all other code should be independent of vendor code reference. Therefore,
remove vendor code reference from any GPIO code.
BUG=b:77999987
TEST=Build and boot grunt.
Change-Id: I9ba78767a269ad6b9b06fa11993d8a12350e4bad
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/25695
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Reviewed-by: Garrett Kirkendall <garrett.kirkendall@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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As part of preparing to make GPIO code independent of vendor code references,
convert GPIO table format using newly defined macros.
BUG=b:77999987
TEST=Build and boot kahlee.
Change-Id: I0af768bb4dbcbfef0d2d08ffe869c1dfb6827974
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/25694
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Garrett Kirkendall <garrett.kirkendall@amd.corp-partner.google.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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The EC code should not have been removed from devicetree when moving
over from grunt. This was causing various bewildering issues that
would happen on the first boot but not on subsequent reboots.
BUG=b:73235377
TEST=Grunt powers off and stays powered off at dev screen.
Change-Id: I225138fede66c6e189e0e79d1261d0d579f7cbdc
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://review.coreboot.org/25690
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
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The EC pin definitions are GPEs, not the GPIO numbers.
BUG=b:74022675
TEST=Power status updates immediately when power is inserted.
Change-Id: Icc8330a606f7a85e72b65094462a684927986829
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://review.coreboot.org/25689
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Daniel Kurtz <djkurtz@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The EC should wake the system from S3 when the AC connector is plugged.
BUG=b:77602394
TEST=verify resume on insert with Grunt
Change-Id: I4bcaef2fe75283aaa6260b5b9efd408ff4b05f4c
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/25647
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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bt-pad-enable property is used by kernel driver to set
BT I2S PAD on ACP_BT_UART_PAD_SEL mux, for those platforms which
use these pins for BT I2S. By default the pins are set for UART.
BUG=b:72360151
TEST=Tested playback and capture on audio device connected to BT I2S
Change-Id: Id76bfa1fa1dde904f02a03b0c15986ecb1bbcc97
Signed-off-by: Akshu Agrawal <akshu.agrawal@amd.com>
Reviewed-on: https://review.coreboot.org/25653
Reviewed-by: Daniel Kurtz <djkurtz@google.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Turn on keyboard backlight in romstage to indicate that the system is
booting.
BUG=b:77921345
TEST=Boot grunt, keyboard backlight comes on.
Change-Id: Ib215b19ebdee2f8c4f431af775905eca42436d1c
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://review.coreboot.org/25636
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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ACPI interrupt routing file routing.asl is not reflecting AGESA settings to
the NB Interrupt Routing Registers. The AGESA settings are:
Device self INTA INTB INTC INTD
GPP 0 23 0 1 2 3
GPP 1 24 8 9 10 11
GPP 2 25 16 17 18 19
GPP 3 26 24 25 26 27
GPP 4 23 3 0 1 2
HDA none 22 23 20 21
GBIF none 6 7 4 5
Fix the routing table, considering that NB IOAPIC starts at interrupt 24.
BUG=b:74104946
TEST=Build and boot to a modified grunt board to enable the emmc. Then used
"cat /proc/interrupts" to get active interrupts. Also checked IOAPIC
redirection registers, which are now being programmed.
Change-Id: I60847c46f3f938f9e97d7b323b27d20e36aa2d02
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/25510
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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Fixes: 2269a3c328 ("soc/amd/stoneyridge: Add functions for GPIO interrupts")
Change-Id: I5730259bc6819defc482d31644e1f476679257b2
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/25588
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Chris Ching <chingcodes@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Grunt supports a keyboard backlight, so enable the ASL code.
BUG=b:77455525
Test=Boot Grunt, verify that the string 'KBLT' is in the DSDT.
Change-Id: Idf0f23581bcba0b035c126c68fb167274d7c698a
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/25470
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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As part of moving AGESA calls from bootblock to romstage, OemCustomize.c
of all boards using stoneyridge must be available at romstage.
BUG=b:74236170
TEST=Build grunt and kahlee, actual test will be performed at a later patch.
Change-Id: Ide9efdbff6a07c670034391c0d62e8b74fa5c02b
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/25528
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
The WP signal to the AP isn't inverted as it is on other platforms, so
it was reporting incorrectly. Change the ACPI table to be active low,
and invert the signal when reporting it to everything else.
BUG=b:74946358
TEST=Boot grunt with battery inserted, WP signals both report 1. Remove
battery, WP_CUR reports 0, WP_BOOT still reports 1.
Change-Id: Ic1369dbda609e34b308af308880449643be6af39
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/25469
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
BUG=b:73078053
TEST=build & boot Grunt
Change-Id: I2d4ba197b19c4948b867a61575e858b2a826a286
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://review.coreboot.org/25287
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
Audio machine driver will enable/disable clock by making it as
a CCF clock in kernel.
BUG=b:74570989
TEST=cherry-picked https://patchwork.kernel.org/patch/10291875/
on 4.14 kernel
aplay -vv <file>
check register to see clock enabled
kill aplay
check register to see clock disabled
Change-Id: Ia553e55ffb358415067000d2d2d2744322d1c4db
Signed-off-by: Akshu Agrawal <akshu.agrawal@amd.com>
Reviewed-on: https://review.coreboot.org/25263
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
Set up the EC communication a little earlier so we can read the board
ID before programming GPIOS.
BUG=b:73078053
TEST=Build & Boot grunt, board_id() now gets ID correctly
Change-Id: Icf3f598824cfed69fa03ba2bb86503bb3c3699a5
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://review.coreboot.org/25286
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
The GPIO programming of configure_stoneyridge_UART() can be done by the early
GPIO table, AOAC enabling was already removed. So configure_stoneyridge_uart()
became redundant. Remove procedure configure_stoneyridge_uart().
BUG=b:74258015
TEST=Build and boot kahlee, observing serial output does not changes from
previous serial output.
Change-Id: Ie67051d7b90fa294090f6bfc518c6c074d98cc98
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/25192
Reviewed-by: Garrett Kirkendall <garrett.kirkendall@amd.corp-partner.google.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
GPIO 40 isn't currently being used, so set it to be an input.
BUG=b:73387647
TEST=Build & boot grunt
Change-Id: I5a04cbab1276cd20e7f9c7576e8111089dd2b155
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://review.coreboot.org/25016
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
The Bayhub part is not used on proto with board_id 0, so disable it.
BUG=b:74248569
TEST=Build & boot Grunt. Bayhub part is disabled.
Change-Id: I635356d41bab637726594d403d66dde730f12256
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://review.coreboot.org/25015
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
|
|
This #define tells superio.asl to add a "PNP0501" "Plug and Play
16550A-compatible COM port" entry to kahlee's ACPI tables.
The EC on kahlee boards do not provide a "Serial Port 1" that should
be exposed via ACPI to the OS. In fact, this entry confuses the
kernel and in some cases can cause it to try to redirect output to a
non existing port.
BUG=b:74200887
TEST=Deploy to grunt. Boot kernel with SERIAL_PORT_DFNS undefined and
"earlycon=uart,mmio32,0xfedc6000,115200,48000000" on the kernel
command line, and with an image with serial console enabled.
=> System boots with (kernel) serial console enabled, starting from
0.00 (earlycon), with no gaps in its output, and serial console
also allows logging in.
Change-Id: I0eaed9b4461bb6a6c1aa4ce97752f588d4322b35
Signed-off-by: Daniel Kurtz <djkurtz@chromium.org>
Reviewed-on: https://review.coreboot.org/25021
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
We want to report the board SKU via the SMBIOS tables. Add support for
this, obtaining the ID itself from the EC.
BUG=b:74175244
BRANCH=none
TEST=manually on grunt with another CL:
mosys platform sku
0
Change-Id: I9e08d64df3f89d3703de047dd9ec8e1717e6b212
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-on: https://review.coreboot.org/25011
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
|
|
The GPIOs for PCIe reset and power enable for WLAN must be set up before
amdinitearly for wlan to function.
BUG=b:73898539
TEST=Boot, see WLAN controller in lspci
Change-Id: I568a3240a54817ab6dcf15fe39f7f1336943852b
Signed-off-by: Justin TerAvest <teravest@chromium.org>
Reviewed-on: https://review.coreboot.org/24916
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
While programming interrupts, a message "perhaps this device was defined
wrong?" shows up twice. This is caused because some devices have
interrupt programmed for APIC mode, but not for non-APIC mode. Fix
mainboard_picr_data table by identifying devices programmed with value
0x1F while programmed differently on mainboard_intr_data table. Do so
only for devices that are used by kahlee or interrupt required by old OS.
BUG=b:70788755
TEST=Build and run kahlee, Verify that message disappears from serial
output.
Change-Id: Ic285036290519ed3ee617dffa616bd26c61575c5
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/23716
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
This commit uses newly defined macros to make it easier to read which
iomux function pads are being configured to use.
TEST=Booted grunt, confirmed display backlight came on.
BUG=b:72875858
Change-Id: I24e5091fc7ef696f8e9c932ce04664e6cc3ccb90
Signed-off-by: Justin TerAvest <teravest@chromium.org>
Reviewed-on: https://review.coreboot.org/23830
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
There's no need to set the output enable here; this is already handled
by the native function. I'm making this correction in this change to
prevent the GPIO pin descriptions from getting confusing.
BUG=b:72875858
TEST=Booted, confirmed S5_MUX_CTRL high with and without this change.
Change-Id: I9e047be7169586c59892ef2bdab915683feeebda
Signed-off-by: Justin TerAvest <teravest@chromium.org>
Reviewed-on: https://review.coreboot.org/23829
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
For variants that have a cr50 tpm, this enables faster polling when
interacting with the tpm.
BUG=b:72838769
BRANCH=none
TEST=verified on grunt that irq is used and not timeouts for tpm
Change-Id: I5786d334b6c1cc70f4c7107c75b07a7e27ac4428
Signed-off-by: Chris Ching <chingcodes@chromium.org>
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/23626
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
AmdInitPost returns AGESA_WARNING. This is because AGESA by default
enables bank interleaving, while the HW does not meet the requirements
for it. Disable bank interleaving, thus clearing AGESA_WARNING.
BUG=b:73118857
TEST= Build and run kahlee. Search for "agesawrapper_amdinitpost()
returned AGESA_SUCCESS".
Change-Id: Ice9270f9b10051dbb622344919223cf5439f5d7b
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/23763
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
This makes the flow for GPIO initialization more closely follow that
what is performed for other boards so that it's easier to read the flow
(and stops relying on BS_WRITE_TABLES).
BUG=b:72875858
TEST=Built and booted grunt, built gardenia.
Change-Id: Ic97db96581a69798b193a6bdeb93644f6a74fc9d
Signed-off-by: Justin TerAvest <teravest@chromium.org>
Reviewed-on: https://review.coreboot.org/23679
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
This format (one hex digit, followed by 'b', followed by binary digits)
is arguably useful, but also confusing. Use the more common format
instead.
Change-Id: Ide7b0a999483a2dd863a70f8aa42cd0865e2babf
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/23715
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
TEST=Run powerd_dbus_suspend and resume with button press
BUG=b:69614064
Change-Id: I0a5a610590b599b96dd0def211c4aa31c7a538ea
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/22732
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
Add an entry to the grunt devicetree defining the ADAU7002 PDM-to-I2S
converter.
BUG=b:72121803
TEST=With grunt audio kernel patches, "aplay -l" shows playback devices:
**** List of PLAYBACK Hardware Devices ****
card 0: acpd7219m98357 [acpd7219m98357], device 0: Playback da7219-hifi-0 []
Subdevices: 1/1
Subdevice #0: subdevice #0
card 0: acpd7219m98357 [acpd7219m98357], device 2: HiFi Playback HiFi-2 []
Subdevices: 1/1
Subdevice #0: subdevice #0
Change-Id: I90b59ec64f4b841932db42b8a8970ed924283613
Signed-off-by: Daniel Kurtz <djkurtz@chromium.org>
Reviewed-on: https://review.coreboot.org/23660
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
|
|
Remove manually written asl entries for grunt's DA7219 and MAX98357A
audio codecs, and replace them with equivalent devicetree entries.
BUG=b:72121803
TEST=With grunt audio kernel patches, "aplay -l" shows playback devices:
**** List of PLAYBACK Hardware Devices ****
card 0: acpd7219m98357 [acpd7219m98357], device 0: Playback da7219-hifi-0 []
Subdevices: 1/1
Subdevice #0: subdevice #0
card 0: acpd7219m98357 [acpd7219m98357], device 2: HiFi Playback HiFi-2 []
Subdevices: 1/1
Subdevice #0: subdevice #0
Change-Id: Ia658c54a28a5363aabb4c50478adaca1f46d166a
Signed-off-by: Daniel Kurtz <djkurtz@chromium.org>
Reviewed-on: https://review.coreboot.org/23658
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
|
|
* micbias_lvl -> micbias-lvl
* mic_amp_in_sel -> mic-amp-in-sel
BUG=b:71875600
TEST=Checked in kernel the values are set
Change-Id: Ife7e8cdd835cc256cd8265593a94df84a510cebb
Signed-off-by: Akshu Agrawal <akshu.agrawal@amd.com>
Reviewed-on: https://review.coreboot.org/23603
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
I2C bus rise/fall times were measured as follows. Signals were generated
with:
- bus 0: manual i2c driver in depthcharge
- bus 2,3: i2cdetect -r <bus_number>
and then measured manually with an oscilloscope.
BUG=b:72442912
Change-Id: I291e144249271ec34a93417398e54e68b8e21e23
Signed-off-by: Justin TerAvest <teravest@chromium.org>
Reviewed-on: https://review.coreboot.org/23520
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
|
|
CMOS layout is not used and can be removed. A change to Kconfig is needed in
order not to break the build.
BUG=b:64207749
TEST=Build kahlee.
Change-Id: Ib5d18e80a56111d96c730420db865194c71de1b3
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/23596
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
Initialize non-early i2c buses in ramstage.
BUG=b:69407112
TEST=Boot depthcharge w/ CLI enabled on grunt.
devbeep
=> plays beep
BRANCH=None
Change-Id: I634a7a823cc393243841dbd55e52abe3f0e72c5a
Signed-off-by: Daniel Kurtz <djkurtz@chromium.org>
Reviewed-on: https://review.coreboot.org/23554
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
|
|
The wifi card was not being powered, and was being held in reset during
PCI enumeration, so it was not being brought up.
BUG=b:72738963
TEST=Verify wlan card shows up in lspci
Change-Id: I5a1e83298af35aa80c67c75cd6ec0a2c3213891e
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/23552
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
When booting kahlee, there's an error message: "Warning: Can't write PCI
IRQ assignments because 'mainboard_pirq_data' structure does not exist".
This is generated by write_pci_cfg_irqs due to missing mainboard_pirq_data.
BUG=b:70788755
TEST=Build and boot kahlee. Warning message must be gone.
Change-Id: If07d2f54f06f6cf77566c43eddc8ee8a314e7a3a
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/22940
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
The kernel requires the display oprom is loaded *and* ran
in order for the kernel to not panic. Therefore, select the
correct settings such that normal mode works for Chrome OS.
BUG=b:72400950
Change-Id: Ibae5bc6b382cbe71a55c2386a24bb420cb8f313f
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/23506
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
This commit adds an entry for H1/Cr50 into the devicetree for setting up
ACPI entries for H1 communication.
BUG=b:69250772
TEST=See probe messages in dmesg
Change-Id: Id55ce3364ea4acdb62782758e5bcb2a167286cb9
Signed-off-by: Justin TerAvest <teravest@chromium.org>
Reviewed-on: https://review.coreboot.org/23514
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
This commit removes a manually written asl file in favor of configuring
the trackpad through devicetree.
BUG=b:72121803
TEST=cat /proc/interrupts with trackpad connected
Change-Id: I38afcf89ea64ffaf6a10bb317c41154feda57e50
Signed-off-by: Justin TerAvest <teravest@chromium.org>
Reviewed-on: https://review.coreboot.org/23508
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
The gpios for 147 and 148 are connected to PCH_I2C_HUB_SCL and
PCH_I2C_H1_TPM_SDA, respectively. Fix the comment.
BUG=b:64140392
Change-Id: Ibebf6ce7d9fb26276b12b9c9844c260413f0337e
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/23499
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
|
|
Since the h1 i2c bus is required for verstage mark the bus
as needing to be initialized early. That way, the bus is initialized
in bootblock prior to verstage.
BUG=b:70232394,b:69250772
Change-Id: Ice8525e08ccb438bc468d4c8bd311f72eddc7eb6
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/23498
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
|
|
I measured the rise and fall times for I2C bus 1 from userspace
manually, using "i2cdetect 1" called from userspace and an oscilloscope.
This commit fixes the values there to reflect reality.
BUG=b:72442912,b:70232394
Change-Id: I4f593cb2674006060cad9a77753c23f7d9828c9b
Signed-off-by: Justin TerAvest <teravest@chromium.org>
Reviewed-on: https://review.coreboot.org/23459
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Chris Ching <chingcodes@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Fix the values that were off by one.
This was discovered when using postcar stage that prints with
debuglevel BIOS_NEVER.
Change-Id: I73a077950ed0dc735d89c9747a8da0a25f30822d
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/23186
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
This commit adds support for an Elan touchscreen device connected over
I2C via devicetree.
BUG=b:72121803
TEST=Confirm the device is probed for.
Change-Id: Ia9e427dbeab9088f77e3cd751b561f7b9a8cb400
Signed-off-by: Justin TerAvest <teravest@chromium.org>
Reviewed-on: https://review.coreboot.org/23408
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
|
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I2C bus configuration is generally set up in devicetree.cb. This change
establishes listings for the buses so that they can be used (though
followup changes should update the buses to have correct timings).
BUG=b:72121803
Change-Id: I2b12c82d2bab42ab470aa207880be8876e7cb75f
Signed-off-by: Justin TerAvest <teravest@chromium.org>
Reviewed-on: https://review.coreboot.org/23407
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
This is required to add support for I2C devices on Kahlee to ACPI tables
via devicetree.cb. Without this, operations are not emitted for I2C
devices and the proper ACPI table entries are not generated.
BUG=b:72121803
Change-Id: I1cfe12f3cc23e90ec74b739678f5a5a73257c2c2
Signed-off-by: Justin TerAvest <teravest@chromium.org>
Reviewed-on: https://review.coreboot.org/23406
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
|
|
Chrome OS reports that "GRUNT TEST XXXX" is an invalid hwid. The 8296
comes from the lower four numbers from running:
$ printf "%d\n" 0x$(crc32 <(echo -n 'GRUNT TEST'))
BUG=b:72436450
Change-Id: Ib0044442396cad65c25c107feb35a30a2f70b769
Signed-off-by: Justin TerAvest <teravest@chromium.org>
Reviewed-on: https://review.coreboot.org/23411
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
|
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Kahlee uses LPC TPM while grunt is using Cr50 connected to I2C. Create
the appropriate selection based on selected board, and if grunt then
define the I2C address.
BUG=b:69416132
BRANCH=none
TEST=make all
Change-Id: Ia866f80de0164d8cec84e204a5fe93bb53df547f
Signed-off-by: Chris Ching <chingcodes@chromium.org>
Reviewed-on: https://review.coreboot.org/22960
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Function platform_FchParams_reset() is now an empty function, remove it,
its header declaration and its use.
BUG=b:64140392
TEST=Build kahlee.
Change-Id: I3f3efc072a2e198433d0e261dacbbd4a8ff327d7
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/22989
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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Fill up the dummy gpio_set_stage_reset[] and gpio_set_stage_ram[]
with data from agesa_board_gpios[], wrap format and delete
agesa_board_gpios[] and get_gpio_table(). Then remove the
get_gpio_table() call from BiosCallOuts.c. Finally, remove
get_gpio_table() from
google/kahlee/variants/baseboard/include/baseboard/variants.h.
BUG=b:64140392
TEST=Build grunt. Build and boot kahlee, recording serial output. Search
for "stage bootblock" and "stage ramstage", indicating GPIO being
programmed.
Change-Id: I88bf2c855105a6bc458aedfc6da7725662695667
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/22988
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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Create a GPIO programming function that can be called from multiple
stages (bootblock, romstage and ramstage) that will program only the
GPIO specific to the particular stage.
Add dummy table to kahlee, grunt and gardenia to be able to test a build.
BUG=b:64140392
TEST=Build kahlee, grunt and gardenia with GPIO programming call at
bootblock. This call is removed before commit, so bootblock.c is not
committed.
Change-Id: I88d65c78a186bed9739bc208d5711a31aa3c3bb6
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/22986
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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GPIO 90 is being used as a GPIO. The IOMUX register is set correctly,
but these additional registers need to be set to use it as a GPIO.
- Split structures into variant specific versions. These will be
moved into the variant tree in a follow-on patch
- Set GENINT_DISABLE bit
- Disable interrupts for this GPIO.
BUG=b:71867096
TEST=Build and boot grunt. Verify registers are set correctly.
Change-Id: I4b8d12720167b298ee6e0acf80edf414539975b0
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/23228
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The GPIOs that are being set low had the wrong value getting set.
FCH_GPIO_OUTPUT_VALUE was being set instead of FCH_GPIO_OUTPUT_ENABLE.
BUG=b:70234300
TEST=Build and boot Grunt
Change-Id: I16792b76252506a43aac92738b04096ae3fde01c
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/23224
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
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Grunt and Kahlee touchpads are on different i2c busses; I2CC and I2CD,
respectively.
Since grunt is the 'baseboard', put its configuration under baseboard, and
include it from the grunt variant.
BUG=b:71820409
TEST=Boot grunt to kernel, use evtest to test trackpad.
TEST=Boot kahlee to kernel, use evtest to test trackpad.
Change-Id: I1aeacf9a840342e73c1e219a825b39a124b4dd57
Signed-off-by: Daniel Kurtz <djkurtz@chromium.org>
Reviewed-on: https://review.coreboot.org/23232
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Grunt and Kahlee have different audio codecs.
Create a new audio .asl for the baseboard for grunt's codec, link
to it from the grunt mainboard, and move the kahlee codec table
from the baseboard mainboard to its own .asl in variant/kahlee.
Note, we can't use the generic drivers due to the PCI scope
expectation. The AMD I2C are not PCI devices.
BUG=b:69397774
TEST=Codec driver loads. Check dmesg.
Change-Id: I1cc245357d1f3d444e5a5012466eaa5d75d637eb
Signed-off-by: Akshu Agrawal <akshu.agrawal@amd.com>
Signed-off-by: Marc Jones <marcj303@gmail.com>
Signed-off-by: Daniel Kurtz <djkurtz@chromium.org>
Reviewed-on: https://review.coreboot.org/23226
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Move the apci/ to the baseboard and move mainboard.asl to
each variant.
BUG=b:71873651
TEST=build
BRANCH=none
Change-Id: I8a829f2946e4b280cd78574eb8dbda6c2a9a1028
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/23229
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
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The Port initializer had been changed from PortDisabled to PortEnabled,
but engine inializer hadn't been updated from PcieUnusedEngine to
PciePortEngine. Update this so the port works.
Also change disabled port to PcieUnusedEngine.
BUG=b:71818026
TEST=PCIe device now shows up on D2F4
Change-Id: I11eb8c1fbad12fa9cf34d758a4ef3c22ef8ba4f7
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/23210
Reviewed-by: Daniel Kurtz <djkurtz@google.com>
Reviewed-by: Chris Ching <chingcodes@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The .spd.hex text is added to the name by the build process. This
was causing a failure because we were trying to add the files:
'file.spd.hex.spd.hex' to the build.
Remove the additional .spd.hex text.
BUG=b:71535311
TEST=Build
Change-Id: I11df7a90c979503676a66c6502900a13f1a8e359
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/23189
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Chris Ching <chingcodes@chromium.org>
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Grunt's devicetree dropped some entries when it was split from the
kahlee variant. This commit restores:
spd_addr_lookup - memory information for AGESA
dram_clear_on_reset - keeps DRAM contents on reset
uma_mode - needed for vbios
uma_size - needed for vbios
Change-Id: I1d8cdc97594867f1d706318370055087976a5104
Signed-off-by: Justin TerAvest <teravest@chromium.org>
Reviewed-on: https://review.coreboot.org/23099
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-by: Martin Roth <martinroth@google.com>
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Don't rely on the cascading default values. Ensure Kahlee uses the fanless
versions of the SMU fimware by selecting it.
Change-Id: I0761266f2a4026ebc251b64074c10481118734a2
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/22251
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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The overcurrent pins on kahlee weren't mapped correctly, causing
the USB-A port to stop working.
None of the EHCI only ports are used for external connectors, so all
of the overcurrent pins should go to the XHCI connections. This is
also true of the Grunt board.
On Grunt, this also means that we don't need OC3, as it doesn't map
to anything in the XHCI controller, as it's coming from an internal
hub.
BUG=b:70636233
TEST=Build & boot Kahlee, verify USB-A port is working again.
Change-Id: I53336a18a26bd9be27c7265fddbcd780632656bf
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/22860
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Reviewed-by: Daniel Kurtz <djkurtz@google.com>
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MEM_ID SPD
0000 hynix-H5AN8G6NAFR-UHC
0001 hynix-H5ANAG6NAMR-UHC
0010 micron-MT40A51216JY-083E
0011 micron-MT40A1G16KNR-075E
0100 samsung-K4A8G165WB-BCRC
0101 samsung-K4AAG165WB-MCRC
BUG=b:69268926
TEST=build test
Change-Id: I1fd6335b3f8842252c42009a0a91a5b6ed3ea238
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/22748
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Move AGESA related headers in soc/amd/common to
soc/amd/common/block/include/amdblocks.
BUG=b:69262110
TEST=Build with no error gardenia and kahlee (no code change, headers moved).
Change-Id: I5d3064625ddf8caaf370aabaf93165c6817f1ca0
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/22772
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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The following files need to be moved: amd_pci_util.c, amd_pci_util.h and
spi.c. The remaining files are AGESA related and will be part of a separate
issue/commit.
BUG=b:62240201
TEST=Build with no error gardenia and kahlee (no code change, just folder
reorg).
Change-Id: I3f965afa21124d4874d3b7bfe0f404a58b070e23
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/22765
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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- The touchscreen interrupt was moved from the GPIO 3, as originally
suggested to GPIO 11. This changes the gevent from 2 to 18.
- Add EMMC reset on GPIO 93.
- Add EMMC bridge PCIe reset on GPIO 40.
- Set device enables to high.
- Remove extra SCI comment from GPIO 130.
- Set individual device PCIe reset pins to high.
- Enable global PCIe reset on GPIO 26.
- Mark LPC_CLK1 as unused.
- Update net names based on latest schematics.
- Set Direction and level/edge correctly for SCIs/SMIs.
- Remove SCI for pen detect.
- Add comments.
BUG=b:70234300, b:69681660, b:69305596
TEST=build grunt
Change-Id: Ib591e4278ed23d0963ecb19ad9c326498b4c7796
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/22751
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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- Grunt moved the EMMC chip to port 2, where Kahlee had the SD reader on
PCIe port 1, so move the OemCustomize file into the variant directory.
- Add comments in baseboard version so it's easier to understand.
- Update reset pins, put the definitions in gpio.h
BUG=b:70255003
TEST=Build and boot Kahlee. Build Grunt.
Change-Id: I78ec72e9d6fd52b8ac75e7187bd01ee7ddc3ba2a
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/22750
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
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In preparation to deleting early_setup,c, change early_ec_init() to use new
southbridge.c function sb_set_wideio_range and remove <#ifdef __PRE_RAM__>.
BUG=b:64033893
TEST=Build, boot and check serial output, search for "Covered by wideIO xx",
which should match earlier message "Range assigned to wide IO xx" generated
within modified early_ec_init().
Change-Id: Iaea17f4f636aab6bd8b05b1b3bed53a677164e74
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/22591
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Set the USB over current pins for the Grunt baseboard and
Kahlee mainboard. Removes the ACPI ASL OC code, which is not
used on Stoney Ridge SOC.
BUG=b:69229635
TEST=Build and boot Kahlee. Not tested with OC test fixture.
Change-Id: I5a9b3409d9c91b89fd02f8eecf9e04c435f14342
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/22679
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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These files aren't needed for the overcurrent functionality.
BUG=b:69305596, b:69229635
TEST=Build Grunt & Kahlee. Overcurrent wasn't yet enabled so no other
testing was needed.
Change-Id: I8dcd50a249e387ccf1142949b359cee09942460a
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/22659
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
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Add initial baseboard GPIOs based on grunt schematics.
BUG=b:69305596
TEST=Build grunt
Change-Id: I4efcee7dbf54fb9ea82e5e9394db805bb69203c8
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/22546
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
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Update the variable ${CONFIG_VARIANT_DIR} to use parens instead. Either
is valid, but since we use parentheses everywhere else, it's better to
be consistent.
BUG=b:69691210
TEST=Build grunt & kahlee
Change-Id: Ieffabaae5516a893f1dc1f7195a17c4cdeae8853
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/22656
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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