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2018-08-06mainboard/google/kahlee: Add PSPP override settingMarc Jones
Add default PSPP AGESA setting for Kahlee/Grunt mainboards. BUG=b:112020107 TEST= build test Change-Id: I8a8605402379de88a04f3a16553c308513fa1531 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/27784 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-08-06google/grunt: Move PSP_SELECTABLE_SMU_FW to socRichard Spiegel
Now that an updated bootloader with important fixes is available at coreboot repository, all stoneyridge boards should use it. Move the selection of SOC_AMD_PSP_SELECTABLE_SMU_FW from mb/google/kahlee to soc/amd/stoneyridge. BUG=b:111428800 TEST=Build and boot grunt. Change-Id: Idf8e348efbc85569aa1163125f412c5242c46eb4 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/27844 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-06mb/google/kahlee: Disable SATA in all boardsRichard Spiegel
Kahlee based boards don't use SATA, so disable SATA on all boards to save power. BUG=b:112139043 TEST=Build and boot grunt, checked the absence of SATA PCI. Change-Id: I6a12c03a5a95b1c8b40609a3fe656df92548b80b Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/27849 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-07-31mainboard/google/kahlee: Update VBIOS imageRichard Spiegel
The careena board requires a different setting within VBIOS in order to pass the eDP eye diagram test. Update all kahlee boards to use the new vBIOS. CQ-DEPEND=CL:1153080 BUG=b:111673328 TEST=Verify, via SOME unspecified method, that the new vBIOS is built into the Grunt/Careena ROM files. Change-Id: I268cd3dbce6ba1f7bd781d768f470463846a4e10 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/27643 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-30mb/google/kahlee/OemCustomize.c: Enable eDP HIGH_VDIFFRichard Spiegel
The careena board needs different video settings to pass eye diagram test, which does not affect negatively the grunt board. In preparation for new VBIOS, AGESA environment needs eDP high vdiff enabled. BUG=b:111673328 TEST=Add debug code to AGESA to display set eDP. Build AGESA. Build and boot grunt. Add new code to grunt, build and boot, verify eDP changed. Change-Id: I3e6b409699e8192eb39cc189628ff95b9f985e54 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/27670 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-07-30mainboard/google/kahlee: Pad SPD serial Number with spacesMartin Roth
All of the other SPDs are padded with spaces to make them use the full size of the serial number field. The hynix-H5AN8G6NCJR-VKC SPD was not, and that seems to be causing problems with some tools. BUG=b:111903749 TEST=Mosys correctly identifies memory on board using that SPD. Change-Id: I0e831873acab2f6fc7d76e85647198d3b7af4b12 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/27676 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Daniel Kurtz <djkurtz@google.com> Reviewed-by: Kevin Chiu <Kevin.Chiu@quantatw.com>
2018-07-28mainboard/google/kahlee: Fix Micron MT40A512M16LY-075:E POST CRC errorKevin Chiu
Fix Micron MT40A512M16LY-075:E DRAM SPD CRC error in AGESA MemSPDChecking: ERROR Event: 04011200 Data: 0, 0, 0, 0 BUG=b:111901461 BRANCH=master TEST=emerge-grunt coreboot Change-Id: I85c82fd9294f9146fc23e649436cbcc337c4c961 Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/27657 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-25mb/google/x86-boards: Get rid of power button device in corebootFurquan Shaikh
As per the ACPI specification, there are two types of power button devices: 1. Fixed hardware power button 2. Generic hardware power button Fixed hardware power button is added by the OSPM if POWER_BUTTON flag is not set in FADT by the BIOS. This device has its programming model in PM1x_EVT_BLK. All ACPI compliant OSes are expected to add this power button device by default if the power button FADT flag is not set. On the other hand, generic hardware power button can be used by platforms if fixed register space cannot be used for the power button device. In order to support this, power button device object with HID PNP0C0C is expected to be added to ACPI tables. Additionally, POWER_BUTTON flag should be set to indicate the presence of control method for power button. Chrome EC mainboards implemented the generic hardware power button in a broken manner i.e. power button object with HID PNP0C0C is added to ACPI however none of the boards set POWER_BUTTON flag in FADT. This results in Linux kernel adding both fixed hardware power button as well as generic hardware power button to the list of devices present on the system. Though this is mostly harmless, it is logically incorrect and can confuse any userspace utilities scanning the ACPI devices. This change gets rid of the generic hardware power button from all google mainboards and relies completely on the fixed hardware power button. BUG=b:110913245 TEST=Verified that fixed hardware power button still works correctly on nautilus. Change-Id: I733e69affc82ed77aa79c5eca6654aaa531476ca Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/27272 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-07-23mb/google/kahlee: Update i2c timingsMatt Wells
Change the I2c timings to the latest measurements. BUG=b:72442912 TEST=Boot grunt Change-Id: I6f9538d26b77ae952ad585e569b3a836e1a09da2 Signed-off-by: Matt Wells <dawells@google.com> Reviewed-on: https://review.coreboot.org/27553 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-07-20mainboard/google/kahlee: Create Liara variantMartin Roth
This is based on the Grunt variant. BUG=b:111607004 TEST=Build Liara Change-Id: I8f23e972be0d1665c736d61621a0caaa4c4c5551 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/27539 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2018-07-20mainboard/google/kahlee: Create Aleena variantMartin Roth
This is based on the Grunt variant. BUG=b:111606874 TEST=Build Aleena Change-Id: I6fd42db6f9f309c3c375b670cd22f818555e4195 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/27538 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2018-07-18mainboard/google/Kahlee: Select low-power mode for WiFiSimon Glass
Put the PCIe clock pins in power-saving mode for the WiFi module to save power. Note: This currently does not appear to have any effect on grunt. BUG=b:110041917 BRANCH=none TEST=boot without this patch: $ iotools mem_read32 0xfed80e00 0x0046f3ff With this patch: $ iotools mem_read32 0xfed80e00 0x0046f3f1 Change-Id: I389815bc36b8610a30b0cbb9d73262ad392e0181 Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-on: https://review.coreboot.org/27465 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-07-18mainboard/google/kahlee: Enable ASPM on PCI expressSimon Glass
We should use active-state power management where possible to reduce power consumption during normal operation. Enable these options. Linux does not seem to enable this for AMD, and the Intel code in coreboot does enable these options. PCIEXP_COMMON_CLOCK is enabled also, to follow how Intel does it. BUG=b:110041917 TEST=boot on grunt, see that WiFi and eMMC still run OK Change-Id: Ia7c711304ffe460a9fb0d4f654a51485958239ea Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-on: https://review.coreboot.org/27464 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-17mainboard/google/kahlee: Don't default backlight onMarc Jones
Keep the backlight off until it is needed. BUG=b:72694972 TEST=Backlight turns on at ChromeOS splash screen, not prior. Change-Id: Ia1aba787734e2976146ecd305dd821f0b326f0db Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/27489 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-07-17mainboard/google/kahlee: Enable backlight on resumeMarc Jones
BUG=b:72694972 TEST=Backlight turns on ChromeOS resume Change-Id: I452e2ea94b508b137cf52301df5d2d1ad5c9ab70 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/27488 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-07-17mainboard/google/kahlee: Enable backlight in SMI APMCMarc Jones
Enable the backlight in the OS callback to SMI for APMC. This keeps the backlight off until the OS is ready to display something. BUG=b:72694972 TEST=Backlight turns on at ChromeOS splash screen Change-Id: Idf32b1a3d45971883571a829a5c0c1f8563bb1f7 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/27487 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-07-17mainboard/google/kahlee: Add mainboard resume functionMarc Jones
Add the mainboard resume function and __weak variant override. Change-Id: I808734208bd1ce81428771ea203709b53db56cd3 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/27486 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-07-16google/grunt: fix thermal zone CPU temperature reportKevin Chiu
there are 3 thermal sensors and index is: 0: 1 Charger 1: 1 SOC 2: 0 CPU it needs to adjust sensor to index 2 to have correct CPU temperature. BUG=b:111284412 BRANCH=master TEST=emerge-grunt coreboot Change-Id: I27afb6c5b64b0c39d6db15e6c61ea16a1fda1ca3 Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/27469 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2018-07-16mainboard/google/kahlee: Add support for Dediprog em100Simon Glass
This device claims to run at 75MHz with dual read, but it is not always reliable. Add an option to change the SPI flash speed to 16MHz, to avoid any problems. BUG=b:111363976 TEST=manually try to get my em100 running (it doesn't yet) Change-Id: I78d3d32c467aac82c72d31c773bfb0f69808aed4 Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-on: https://review.coreboot.org/27466 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-07-16Kconfig: Make the EM100 config option commonSimon Glass
This applied to AMD devices as well as Intel, although the mechanism is different. Move the option to a common place. BUG=b:111363976 TEST=USE=em100-mode emerge-reef coreboot See that a message appears: * Enabling em100 mode (slow SPI flash) Change-Id: Iea437bdf42e7bc49b1d28c812bfc6128e3eb68bd Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-on: https://review.coreboot.org/27467 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-07-13mainboard/google/kahlee: Add more 3 SPD filesMartin Roth
BUG=b:111195311 TEST=Build grunt, verify SPDs are present Change-Id: Ief5ed5c3ca1d96b36926f1fc84c344a8d66dcda5 Signed-off-by: Martin Roth <martinroth@chromium.org> Reviewed-on: https://review.coreboot.org/27437 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-11mainboard/google/kahlee: Update existing SPD filesMartin Roth
Add an extra space after 8th value on each line to make it easier to count the values. Update the empty spd to remove two random 0x80 values. BUG=None TEST=None Change-Id: If330dbf0c133f65aedddc58ecb351a80b0e45a05 Signed-off-by: Martin Roth <martinroth@chromium.org> Reviewed-on: https://review.coreboot.org/27423 Reviewed-by: Daniel Kurtz <djkurtz@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-11mainboard/google/kahlee: Add additional SPDs for variantsMartin Roth
BUG=b:111079089, b:80375243 TEST=Build grunt, verify that SPDs are included. Change-Id: Idb03a3fa0842f7f89bb8c66dedbb8a0b293569be Signed-off-by: Martin Roth <martinroth@chromium.org> Reviewed-on: https://review.coreboot.org/27422 Reviewed-by: Daniel Kurtz <djkurtz@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-06google/grunt: Update Raydium TS device ACPI nodesKevin Chiu
change I2C irq to EDGE trigger BUG=b:110962003 BRANCH=master TEST=emerge-grunt coreboot Raydium TS is working. Change-Id: Iff3acf4199d23b29dff209ec1c03a731679c6cbe Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/27327 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-03mb/google/*: Remove selection of DRIVERS_PS2_KEYBOARDFurquan Shaikh
Until now, chromeec was doing keyboard initialization for the boards that have DRIVERS_PS2_KEYBOARD selected. However, coreboot does not leave the keyboard controller in a default reset state. This could result in payloads or OS failing to probe the controller as there could be stale data buffered in the controller during the handoff. Since the boards using chromeec already perform keyboard initialization in payload, there is no need to initialize the keyboard in coreboot too. This change gets rid of DRIVERS_PS2_KEYBOARD selection from all google mainboards using chromeec. BUG=b:110024487 TEST=Keyboard works fine after booting to OS even if user hits keys during BIOS to OS handoff. Change-Id: I1f49b060eb005c0f2b86f9d68d6758954eeb3cf0 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/27291 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-25mb/google/kahlee/variants/grunt: Select low-power mode for BayHub720Simon Glass
Put the PCIe clock pins in power-saving mode for the BayHub eMMC bridge to save power. This requires use of an additional register (Misc control register 2) and another bit in the existing 'protect' register. The naming of bit 0 of that register is incorrect, based on the latest datasheet (14 June 2018) so fix that too. BUG=b:73726008 BRANCH=none TEST=boot without this patch: iotools mem_read32 0xfed80e00 0x0046ffff With this patch: $ iotools mem_read32 0xfed80e00 0x00463fff Also see that the PCIe clock stops when eMMC is idle and can be started by starting disk activity. Change-Id: I5ad1467b2e2e151215d2dfd2ce48cd4a451fe480 Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-on: https://review.coreboot.org/26515 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-06-15mainboard/google/Kahlee: All variants identify as Grunt in SMBIOSMartin Roth
All Grunt variants should identify as grunt in SMBIOS so that they're recognized correctly as a unibuild Grunt variant. BUG=b:110244268 TEST=Careena identifies as grunt Change-Id: Iaf254149fbec9551d9220018d6d6a0a1be741538 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/27117 Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-15mainboard/google/kahlee: Enable keyboard backlight for careena specific SKUKevin Chiu
Enable keyboard backlight by Careena SKUID Set to 10% as the same as google/snappy project BUG=b:110065836 BRANCH=master TEST=emerge-grunt coreboot Change-Id: I7d302c4f50528b0e6b7ef4d990f342a69cff34f5 Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/27021 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-06-11mainboard/google/kahlee: Remove unused baseboard codeMartin Roth
This code is no longer needed. BUG=b:107537694 TEST=Build & boot on grunt Change-Id: I71ad01f0d4c69a618d564e514ed99550b72a6b44 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/26778 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-06-11mainboard/google/kahlee: Remove Kahlee variantMartin Roth
This code is no longer needed. Removing Kahlee options allows some Kconfig options to be optimized. BUG=b:77693343 TEST=Build Grunt, verify that nothing's changed. Change-Id: I4eeeee7f35381bba8760c8a530251c475d0ee29b Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/26777 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-06-08mainboard/google/kahlee: Turn on backlight for all SKUsMartin Roth
Careena uses a different keyboard backlight method, so let the EC handle the different SKUs and backlight methods. BUG=b:80106042 TEST=None Change-Id: I47f7a9ac13538f0216fbb0f64fdd22f66097820c Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/26969 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2018-06-08src/mainboard/kahlee: Use common mainboard and romstage filesMartin Roth
Until these need to be separated out, use a common file for mainboard and romstage to make upkeep easier. BUG=b:80106042 TEST=Build Grunt and Careena Change-Id: I65188bee1958d442bfe64637c3b93dc05583a686 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/26968 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2018-06-08mainboard/google/kahlee: Use 66MHz SPI clock for fast readMartin Roth
Looking at the 100MHz signal, we were violating the timing requirements. 66MHz still isn't great, but it's a good tradeoff between improving the signal and losing boot speed time. This slows down the boot time by about 20mS. BUG=b:109583457 TEST=Boot grunt, look at signal on scope Change-Id: I7ce70c992822dd17c5877226e74c1890660768c6 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/26950 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2018-06-08mb/google/kahlee: Configure EC_PCH_WAKE_L as an SCI sourceDaniel Kurtz
Configuring EC_PCH_WAKE_L as an SCI enabled GPIO allows the EC to wake the AP from S3 on keyboard presses. BUG=b:109759838 TEST=(1) powerd_dbus_suspend (2) press a key on the internal keyboard => system resumes from S3 Change-Id: I30f72460fd588706f91f4fc3ea4ff007c96e9ebe Signed-off-by: Daniel Kurtz <djkurtz@chromium.org> Reviewed-on: https://review.coreboot.org/26931 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-07mainboard/google/kahlee: Remove colon from filenamesMartin Roth
Change-Id: I3e0ca62ad88aea5c99f9f0902ad8553656469a1c Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: https://review.coreboot.org/26936 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-04security/tpm: Unify the coreboot TPM software stackPhilipp Deppenwiese
* Remove 2nd software stack in pc80 drivers directory. * Create TSPI interface for common usage. * Refactor TSS / TIS code base. * Add vendor tss (Cr50) directory. * Change kconfig options for TPM to TPM1. * Add user / board configuration with: * MAINBOARD_HAS_*_TPM # * BUS driver * MAINBOARD_HAS_TPM1 or MAINBOARD_HAS_TPM2 * Add kconfig TPM user selection (e.g. pluggable TPMs) * Fix existing headers and function calls. * Fix vboot for interface usage and antirollback mode. Change-Id: I7ec277e82a3c20c62a0548a1a2b013e6ce8f5b3f Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org> Reviewed-on: https://review.coreboot.org/24903 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-06-03mb/google/kahlee: Remove #include <soc/smi.h>Richard Spiegel
Because of struct sci_source table of events that have to generate SCI or SMI, <soc/smi.h> was included to kahlee/grunt gpio.c files. However, new code transfered most of SCI/SMI/interrupt programming (with exception of events not associated to a GPIO pin), and therefore smi.h is now included by gpio.h. It was also added to some other files where they are not needed. Only smihandler.c truly needs it. Remove the includes. BUG=b:78139413 TEST=build and boot grunt. Change-Id: I64cf0796103a5226ddace03d05d94160bf93aa69 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/26721 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-31mainboard/google/kahlee: Add careena variantMartin Roth
Add Careena variant, based on the grunt board. BUG=b:80106042 TEST=Build Careena Change-Id: I87a24f6d8115aacf5b21181f3820cf2718ad252a Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/26524 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-05-30mainboard/google/kahlee: move grunt's chromeos.fmd to baseboardMartin Roth
The chrmoeos.fmd file will be common across variants, so move it out of of grunt directory and into the variants/baseboard directory. BUG=b:80106042 TEST=Build grunt Change-Id: I259d85f60c5e19e00f7d9149542bcfdcc6dfaf4f Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/26656 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-05-30mainboard/google/kahlee: move SPDs to variants/baseboard/spdMartin Roth
The SPD files will be common to many of the mainboards, so move them out of grunt and into the variants/baseboard directory. BUG=b:80106042 TEST=Build grunt, make sure spd.bin is the same. Change-Id: I53975a46a8c7d7e519bb6f7ef6ccd0b817ac4c92 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/26523 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-05-27grunt: Wire up the EC SMI handlerRaul E Rangel
This won't actually get called yet since the GPIO pin has not been configured as SMI. BUG=b:80295434 TEST=grunt: Made sure events could be processed. Change-Id: I189e26196e4543b3e34bff5d9df8566eff07d585 Signed-off-by: Raul E Rangel <rrangel@chromium.org> Reviewed-on: https://review.coreboot.org/26546 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-05-27stoneyridge GPIO: Create and use PAD_INT for interrupt pinsRichard Spiegel
The default interrupt control for GPIO pins within stoneyridge is for edge triggered, high. However, sometimes these need to change, or maybe the interrupt needs to be reported or delivered. This was the case of platform grunt, where the interrupt related bits were being changed afterwards. Ideally all the bits should be programmed through the same procedure. Create several PAD_INT definitions (for general configuration, for trigger configuration and for interrupt type configuration) and change function sb_program_gpios() to accept the output from PAD_INT_XX and program all the necessary bits while keeping compatibility with other PAD_XX definitions. BUG=b:72875858 TEST=Add code to report GPIO and interrupt configuration, build grunt and record a baseline. Add new code, rebuild grunt and record a test output. Compare baseline against test, there should be no change in GPIO or interrupt programming. Remove code that reports GPIO/interrupt configuration. Change-Id: I3457543bdf64ec757fd82df53c83fdc1d03c1f22 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/25758 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-05-25mb/google/kahlee: Init APU_BIOS_FLASH_WP_L GPIO to reset stageDaniel Kurtz
GPIO APU_BIOS_FLASH_WP_L is first read in ROM stage to determine the state of the BIOS FLASH Write Protect signal at boot. The result of this read accumulated in the vboot state that's passed on to the upper layers of the stack. Therefore this GPIO must be configured as a "reset stage" GPIO, not a "RAM" stage GPIO. BUG=b:79866233 TEST=firmware_WriteProtect Change-Id: I1d96ab4bbfeaf9db9f74cf0c58cbab2104079bf7 Signed-off-by: Daniel Kurtz <djkurtz@chromium.org> Reviewed-on: https://review.coreboot.org/26498 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-23mb/google/kahlee/dsdt.asl: Add method _SWSRichard Spiegel
_SWS is the recommended method of wake source retrieval. Now that PM1I and GPEI are available at NVS, add the method _SWS to kahlee/grunt ACPI code. BUG=b:76020953 TEST=Build grunt Change-Id: I5930438af40e6f9177462582cafb65401d9c60f4 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/26217 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-05-22mainboard/google/kahlee: Update RW_LEGACY size in fmapMartin Roth
Add the unused space to the RW_LEGACY area. BUG=b:79433466 TEST=None Change-Id: I897d1dcf75466fe9bdb814c8a9db0fecb5c42af6 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/26221 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-05-22google/kahlee: Swap UNIFIED_MRC_CACHE and RW_SECTION_A in fwmapDaniel Kurtz
The firmware_Mosys FAFT test does not allow RW_SECTION_A, RW_SECTION_B or RW_SHARED to be 0-sized, nor located at offset 0x00000000. Swap UNIFIED_MRC_CACHE and RW_SECTION_A to pass this test. BUG=b:79865447 TEST=test_that -b grunt ${IP} firmware_Mosys Change-Id: If60919fd998ac786d58a5a258d7b5ded727db64b Signed-off-by: Daniel Kurtz <djkurtz@chromium.org> Reviewed-on: https://review.coreboot.org/26356 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-05-21google/kahlee: Reduce UMA memory to 32MBMarshall Dawson
Lower the amount of UMA memory to 32MB at AMD's request. TEST=none BUG=b:79906569 Change-Id: Ib1365dc38850b4b92c944ff95534573addbe4362 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/26383 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-05-21google/grunt: Reduce UMA memory to 32MBMarshall Dawson
Lower the amount of UMA memory to 32MB at AMD's request. TEST=boot Grunt, try S3 BUG=b:79906569 Change-Id: I5af038688b38b53c94b8265823eeee0f37980522 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/26382 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-05-08mb/google: Get rid of device_tElyes HAOUAS
Use of device_t has been abandoned in ramstage. Change-Id: I8e549e4222ae2ed6b9c46f81c5b5253e8b227ee8 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26086 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-05-08src/mainboard: Set ACPI OEM ID values to 6 characters longMartin Roth
Change OEM ID values to 6 characters to fix error compiling with IASL version 20180427. Also update table creator to 8 characters from 7. Change-Id: Id6c9a7b08dc4a9efeb69011393e29aa5a6bc54c4 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/26047 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-05-04mainboard/google/kahlee: Pass oscout system clk to da7219Akshu Agrawal
Using da7219 mclk-name property, oscout system clock is linked to da7219 mclk. da7219 then handles enabling/disabling of the clk. BUG=b:74570989 TEST=Tested clock enable/disable in kernel driver Change-Id: I298b0ce5d2c40daadeb5d68f9cb595a965272021 Signed-off-by: Akshu Agrawal <akshu.agrawal@amd.com> Reviewed-on: https://review.coreboot.org/25920 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-05-04google/kahlee: Revert "Resume on AC insertion"Martin Roth
This reverts commit edf2f59b1d93a1bc9161a67d3c00a9a05fa8519a. (google/kahlee: Resume on AC insertion) The requirement to wake on AC insert is just to wake enough to charge, not to wake the entire system. BUG=b:77602394 TEST=None Change-Id: I0ee709183b1605c1efc0fce673db512fac66adfa Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/26014 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Daniel Kurtz <djkurtz@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-04mainboard/google: Comment variant names in KconfigMartin Roth
It's very confusing trying to find the google platform names, because they seem all unsorted in Kconfig. They're actually sorted according to the variant name, but previously, that was impossible to tell. - Add a comment to the top of variants in Kconfig.name - Inset each variant name. If you start a prompt with whitespace, it gets ignored, so after trying various ways to indent, the arrow was the option I thought looked the best. It now looks like this: *** Beltino *** -> Mccloud (Acer Chromebox CXI) -> Monroe (LG Chromebase 22CV241 & 22CB25S) -> Panther (ASUS Chromebox CN60) -> Tricky (Dell Chromebox 3010) -> Zako (HP Chromebox G1) Butterfly (HP Pavilion Chromebook 14) Chell (HP Chromebook 13 G1) Cheza *** Cyan *** Change-Id: I35cb16b040651cd1bd0c4aef98494368ef5ca512 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/26020 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-05-03mainboard/google/kahlee: Update grunt touchscreen in devicetreeMartin Roth
- Add raydium controller - Update elan controller with reset and enable GPIOs. - Enable 'probed' so Linux will check which controller is being used. BUG=b:78929054 TEST=Both elan and raydium touchscreen controllers work Change-Id: I3bd9912a4b1edc7bf1075cb649afa3eab5dca458 Signed-off-by: Martin Roth <martinroth@chromium.org> Reviewed-on: https://review.coreboot.org/25998 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-02google/kahlee: Set SPI 100 MHz and SPI Dual Read IO modeMarc Jones
Set SPI Fast Read to 100MHz and Dual Read IO mode to speed up the boot process by over a half second. Also, increase the Normal Read speed to 33MHz as supported by the W25Q128FW. BUG=b:70558952 TEST=Run cbmem -t to get boot times. Change-Id: I616a96526ed90bb4ab0c9c6b78787799faa02633 Signed-off-by: Marc Jones <marc.jones@scarletltd.com> Reviewed-on: https://review.coreboot.org/25970 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Martin Roth <martinroth@google.com>
2018-05-02mb/google/kahlee/variants/grunt: Enable BayHub720 driverSimon Glass
Enable this driver along with power saving. BUG=b:73726008 BRANCH=none TEST=boot and see this message: BayHub BH720: Power-saving enabled 110103 From linux: $ iotools pci_read32 2 0 0 0x90 0x00110103 Change-Id: I850e923f73e01fe629d66ad61b65afa58035845c Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-on: https://review.coreboot.org/25967 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-04-27google/kahlee: Remove VBOOT_VBNV_CMOSMarc Jones
Remove VBOOT_VBNV_CMOS from the mainboard. It is selected in the stoneyridge Kconfig. BUG=b:77347873 TEST=Manually clear CMOS and check coreboot restores VBNV from flash. Change-Id: I30e517e06ab9d8f7d4a93bf82f12726756c44966 Signed-off-by: Marc Jones <marc.jones@scarletltd.com> Reviewed-on: https://review.coreboot.org/25844 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-04-27google/kahlee: Add RW_NVRAM to FMAPMarc Jones
Add RW_NVRAM area to FMAP for VBOOT_VBNV_CMOS_BACKUP_TO_FLASH support. BUG=b:77347873 TEST=Manually clear CMOS and check coreboot restores VBNV from flash. Change-Id: Id8c6f54634b94bf6ae3755a827e80d0862a42dd2 Signed-off-by: Marc Jones <marc.jones@scarletltd.com> Reviewed-on: https://review.coreboot.org/25843 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-04-26mainboard/google/kahlee: Set SPI speed in bootblockMarc Jones
Set the SPI speed for Normal, Fast, AltIO, and TPM in bootblock. This setup is needed when moving AGESA out of the bootblock. It sets the SPI bus speed of the TPM access in verstage. BUG=b:70558952 TEST=Boot with AGESA moved out of the bootblock. Change-Id: Ida77d78eb1f290e46b57a46298400ed6c8015e2c Signed-off-by: Marc Jones <marc.jones@scarletltd.com> Reviewed-on: https://review.coreboot.org/25756 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-04-26mb/google/grunt: Add grunt touchpad wake GPE to devicestreeDaniel Kurtz
The grunt touchpad interrupt can be used as a wake source. For grunt, the touchpad interrupt uses GPIO5 which corresponds to GEVENT7. BUG=b:77602771 TEST=In OS: # cat /proc/acpi/wakeup => D015 S3 *enabled i2c:i2c-ELAN0000:00 TEST=powerd_dbus_suspend, touching touchpad (> 1 sec) wakes from S3. Change-Id: I510642108a1257f6601f18c77cf3107573427f39 Signed-off-by: Daniel Kurtz <djkurtz@chromium.org> Reviewed-on: https://review.coreboot.org/25827 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-26mainboard/google/kahlee: Enable EC wake on GPIO24Daniel Kurtz
The grunt EC uses GPIO24 (EC_PCH_WAKE_L) to signal wake-up events to the AP. On Stoney, GPIO24 maps to GEVENT (GPE) 15. The kahlee EC uses GPIO2 (EC_PCH_WAKE_L) to signal wake-up events to the AP. On Stoney, GPIO2 maps to GEVENT (GPE) 8. BUG=b:78461678 TEST=powerd_dbus_suspend, tap any key on keyboard wakes from S3. TEST=sign in, EC: lidclose, EC: lidopen => system wakes from S3. Change-Id: Ib1809740837e686992ff70b81933159a5dff7595 Signed-off-by: Daniel Kurtz <djkurtz@chromium.org> Reviewed-on: https://review.coreboot.org/25816 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2018-04-26mainboard/google/kahlee: Fix EC_SMI_GPIDaniel Kurtz
On the kahlee variant, EC_SMI_ODL is connected to GPIO6, which uses GEVENT 10 (GPE10). Fix this up, and also clean up the EC_*_GPI definition format a bit to match the format in the baseboard/gpio.h. BUG=b:78461678 TEST=build coreboot for kahlee Change-Id: I9445efbc02559c2a7c90f67bcb0154b04b03a1aa Signed-off-by: Daniel Kurtz <djkurtz@chromium.org> Reviewed-on: https://review.coreboot.org/25826 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2018-04-24mb/google/kahlee/variants/baseboard/gpio.c: move all non-critical gpiosRichard Spiegel
When GPIO tables were created, there was no study on which pins had to be programmed ASAP and which could be programmed later. Execute such study and move all non-critical gpios from reset to late. BUG=b:76097508 TEST=Build and boot grunt to OS, test OS for lost functionality (WIFI, video playback, track pad, keyboard). Change-Id: Icbc9370050d619800026035caaac3e89536a460a Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/25395 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-04-24compiler.h: add __weak macroAaron Durbin
Instead of writing out '__attribute__((weak))' use a shorter form. Change-Id: If418a1d55052780077febd2d8f2089021f414b91 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/25767 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Justin TerAvest <teravest@chromium.org>
2018-04-20soc/amd/stoneyridge/include/soc/southbridge.c: Rename gpio structureRichard Spiegel
The GPIO definition structure has evolved to a point where it's no longer specific to stoneyridge, though probably still specific to AMD. Therefore, rename the GPIO declaration structure removing stoneyridge from it. BUG=b:72875858 TEST=Build kahlee, grunt, gardenia. Change-Id: Ib034d3f7840c36ee8f5c5384241d7326d3fe5543 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/25726 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-18soc/amd/stoneyridge/include/soc/gpio.h: Remove vendor code referenceRichard Spiegel
With the exception of code that deals directly or indirectly with AGESA, all other code should be independent of vendor code reference. Therefore, remove vendor code reference from any GPIO code. BUG=b:77999987 TEST=Build and boot grunt. Change-Id: I9ba78767a269ad6b9b06fa11993d8a12350e4bad Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/25695 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com> Reviewed-by: Garrett Kirkendall <garrett.kirkendall@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-18mb/google/kahlee/variants/kahlee/gpio.c: Convert GPIO to new formatRichard Spiegel
As part of preparing to make GPIO code independent of vendor code references, convert GPIO table format using newly defined macros. BUG=b:77999987 TEST=Build and boot kahlee. Change-Id: I0af768bb4dbcbfef0d2d08ffe869c1dfb6827974 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/25694 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Garrett Kirkendall <garrett.kirkendall@amd.corp-partner.google.com> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-04-17mainboard/google/kahlee: Add EC back into grunt devicetreeMartin Roth
The EC code should not have been removed from devicetree when moving over from grunt. This was causing various bewildering issues that would happen on the first boot but not on subsequent reboots. BUG=b:73235377 TEST=Grunt powers off and stays powered off at dev screen. Change-Id: I225138fede66c6e189e0e79d1261d0d579f7cbdc Signed-off-by: Martin Roth <martinroth@chromium.org> Reviewed-on: https://review.coreboot.org/25690 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2018-04-17mainboard/google/kahlee: Update EC pins from GPIOs to GPEsMartin Roth
The EC pin definitions are GPEs, not the GPIO numbers. BUG=b:74022675 TEST=Power status updates immediately when power is inserted. Change-Id: Icc8330a606f7a85e72b65094462a684927986829 Signed-off-by: Martin Roth <martinroth@chromium.org> Reviewed-on: https://review.coreboot.org/25689 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Daniel Kurtz <djkurtz@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-16google/kahlee: Resume on AC insertionMarshall Dawson
The EC should wake the system from S3 when the AC connector is plugged. BUG=b:77602394 TEST=verify resume on insert with Grunt Change-Id: I4bcaef2fe75283aaa6260b5b9efd408ff4b05f4c Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/25647 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-04-16mb/google/kahlee: Select BT I2S PAD on ACP_BT_UART muxAkshu Agrawal
bt-pad-enable property is used by kernel driver to set BT I2S PAD on ACP_BT_UART_PAD_SEL mux, for those platforms which use these pins for BT I2S. By default the pins are set for UART. BUG=b:72360151 TEST=Tested playback and capture on audio device connected to BT I2S Change-Id: Id76bfa1fa1dde904f02a03b0c15986ecb1bbcc97 Signed-off-by: Akshu Agrawal <akshu.agrawal@amd.com> Reviewed-on: https://review.coreboot.org/25653 Reviewed-by: Daniel Kurtz <djkurtz@google.com> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-13src/mainboard/kahlee: Turn on keyboard backlight on gruntMartin Roth
Turn on keyboard backlight in romstage to indicate that the system is booting. BUG=b:77921345 TEST=Boot grunt, keyboard backlight comes on. Change-Id: Ib215b19ebdee2f8c4f431af775905eca42436d1c Signed-off-by: Martin Roth <martinroth@chromium.org> Reviewed-on: https://review.coreboot.org/25636 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-13mb/google/kahlee: Fix IRQ routingRichard Spiegel
ACPI interrupt routing file routing.asl is not reflecting AGESA settings to the NB Interrupt Routing Registers. The AGESA settings are: Device self INTA INTB INTC INTD GPP 0 23 0 1 2 3 GPP 1 24 8 9 10 11 GPP 2 25 16 17 18 19 GPP 3 26 24 25 26 27 GPP 4 23 3 0 1 2 HDA none 22 23 20 21 GBIF none 6 7 4 5 Fix the routing table, considering that NB IOAPIC starts at interrupt 24. BUG=b:74104946 TEST=Build and boot to a modified grunt board to enable the emmc. Then used "cat /proc/interrupts" to get active interrupts. Also checked IOAPIC redirection registers, which are now being programmed. Change-Id: I60847c46f3f938f9e97d7b323b27d20e36aa2d02 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/25510 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-04-11src/amd/stoneyridge: Fix a typo (EDGEL_TRIG -> EDGE_TRIG)Jonathan Neuschäfer
Fixes: 2269a3c328 ("soc/amd/stoneyridge: Add functions for GPIO interrupts") Change-Id: I5730259bc6819defc482d31644e1f476679257b2 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/25588 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Chris Ching <chingcodes@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Justin TerAvest <teravest@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-11mainboard/google/kahlee: Enable Keyboard backlight for GruntMartin Roth
Grunt supports a keyboard backlight, so enable the ASL code. BUG=b:77455525 Test=Boot Grunt, verify that the string 'KBLT' is in the DSDT. Change-Id: Idf0f23581bcba0b035c126c68fb167274d7c698a Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/25470 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-10mainboard: Make OemCustomize.c available at romstageRichard Spiegel
As part of moving AGESA calls from bootblock to romstage, OemCustomize.c of all boards using stoneyridge must be available at romstage. BUG=b:74236170 TEST=Build grunt and kahlee, actual test will be performed at a later patch. Change-Id: Ide9efdbff6a07c670034391c0d62e8b74fa5c02b Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/25528 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-05mainboard/google/kahlee: Update WP to active lowMartin Roth
The WP signal to the AP isn't inverted as it is on other platforms, so it was reporting incorrectly. Change the ACPI table to be active low, and invert the signal when reporting it to everything else. BUG=b:74946358 TEST=Boot grunt with battery inserted, WP signals both report 1. Remove battery, WP_CUR reports 0, WP_BOOT still reports 1. Change-Id: Ic1369dbda609e34b308af308880449643be6af39 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/25469 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-03-21mainboard/google/kahlee: Update GPIOs based on board IDMartin Roth
BUG=b:73078053 TEST=build & boot Grunt Change-Id: I2d4ba197b19c4948b867a61575e858b2a826a286 Signed-off-by: Martin Roth <martinroth@chromium.org> Reviewed-on: https://review.coreboot.org/25287 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-03-21mb/google/kahlee: Add register address mapping for FCH MISCAkshu Agrawal
Audio machine driver will enable/disable clock by making it as a CCF clock in kernel. BUG=b:74570989 TEST=cherry-picked https://patchwork.kernel.org/patch/10291875/ on 4.14 kernel aplay -vv <file> check register to see clock enabled kill aplay check register to see clock disabled Change-Id: Ia553e55ffb358415067000d2d2d2744322d1c4db Signed-off-by: Akshu Agrawal <akshu.agrawal@amd.com> Reviewed-on: https://review.coreboot.org/25263 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-03-20mainboard/google/kahlee: Initialize EC earlier in the bootblockMartin Roth
Set up the EC communication a little earlier so we can read the board ID before programming GPIOS. BUG=b:73078053 TEST=Build & Boot grunt, board_id() now gets ID correctly Change-Id: Icf3f598824cfed69fa03ba2bb86503bb3c3699a5 Signed-off-by: Martin Roth <martinroth@chromium.org> Reviewed-on: https://review.coreboot.org/25286 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-03-19soc/amd/stoneyridge/southbridge.c: Remove configure_stoneyridge_uartRichard Spiegel
The GPIO programming of configure_stoneyridge_UART() can be done by the early GPIO table, AOAC enabling was already removed. So configure_stoneyridge_uart() became redundant. Remove procedure configure_stoneyridge_uart(). BUG=b:74258015 TEST=Build and boot kahlee, observing serial output does not changes from previous serial output. Change-Id: Ie67051d7b90fa294090f6bfc518c6c074d98cc98 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/25192 Reviewed-by: Garrett Kirkendall <garrett.kirkendall@amd.corp-partner.google.com> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-03-09mainboard/google/kahlee: Set GPIO 40 to inputMartin Roth
GPIO 40 isn't currently being used, so set it to be an input. BUG=b:73387647 TEST=Build & boot grunt Change-Id: I5a04cbab1276cd20e7f9c7576e8111089dd2b155 Signed-off-by: Martin Roth <martinroth@chromium.org> Reviewed-on: https://review.coreboot.org/25016 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-03-09mainboard/google/kahlee: Disable Bayhub part on board_id 0Martin Roth
The Bayhub part is not used on proto with board_id 0, so disable it. BUG=b:74248569 TEST=Build & boot Grunt. Bayhub part is disabled. Change-Id: I635356d41bab637726594d403d66dde730f12256 Signed-off-by: Martin Roth <martinroth@chromium.org> Reviewed-on: https://review.coreboot.org/25015 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Justin TerAvest <teravest@chromium.org>
2018-03-08mb/google/kahlee: Do not define SIO_EC_ENABLE_COM1Daniel Kurtz
This #define tells superio.asl to add a "PNP0501" "Plug and Play 16550A-compatible COM port" entry to kahlee's ACPI tables. The EC on kahlee boards do not provide a "Serial Port 1" that should be exposed via ACPI to the OS. In fact, this entry confuses the kernel and in some cases can cause it to try to redirect output to a non existing port. BUG=b:74200887 TEST=Deploy to grunt. Boot kernel with SERIAL_PORT_DFNS undefined and "earlycon=uart,mmio32,0xfedc6000,115200,48000000" on the kernel command line, and with an image with serial console enabled. => System boots with (kernel) serial console enabled, starting from 0.00 (earlycon), with no gaps in its output, and serial console also allows logging in. Change-Id: I0eaed9b4461bb6a6c1aa4ce97752f588d4322b35 Signed-off-by: Daniel Kurtz <djkurtz@chromium.org> Reviewed-on: https://review.coreboot.org/25021 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-03-08mb/google/kahlee: Add SKU supportSimon Glass
We want to report the board SKU via the SMBIOS tables. Add support for this, obtaining the ID itself from the EC. BUG=b:74175244 BRANCH=none TEST=manually on grunt with another CL: mosys platform sku 0 Change-Id: I9e08d64df3f89d3703de047dd9ec8e1717e6b212 Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-on: https://review.coreboot.org/25011 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-03-01mb/{amd/gardenia,google/kahlee}: Initialize GPIOs earlierJustin TerAvest
The GPIOs for PCIe reset and power enable for WLAN must be set up before amdinitearly for wlan to function. BUG=b:73898539 TEST=Boot, see WLAN controller in lspci Change-Id: I568a3240a54817ab6dcf15fe39f7f1336943852b Signed-off-by: Justin TerAvest <teravest@chromium.org> Reviewed-on: https://review.coreboot.org/24916 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-02-22mb/google/kahlee/mainboard.c: Fix mainboard_picr_dataRichard Spiegel
While programming interrupts, a message "perhaps this device was defined wrong?" shows up twice. This is caused because some devices have interrupt programmed for APIC mode, but not for non-APIC mode. Fix mainboard_picr_data table by identifying devices programmed with value 0x1F while programmed differently on mainboard_intr_data table. Do so only for devices that are used by kahlee or interrupt required by old OS. BUG=b:70788755 TEST=Build and run kahlee, Verify that message disappears from serial output. Change-Id: Ic285036290519ed3ee617dffa616bd26c61575c5 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/23716 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-02-22mb/google/kahlee: Use GPIO macros for baseboardJustin TerAvest
This commit uses newly defined macros to make it easier to read which iomux function pads are being configured to use. TEST=Booted grunt, confirmed display backlight came on. BUG=b:72875858 Change-Id: I24e5091fc7ef696f8e9c932ce04664e6cc3ccb90 Signed-off-by: Justin TerAvest <teravest@chromium.org> Reviewed-on: https://review.coreboot.org/23830 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-02-22mb/google/kahlee: Correct bad gpio entryJustin TerAvest
There's no need to set the output enable here; this is already handled by the native function. I'm making this correction in this change to prevent the GPIO pin descriptions from getting confusing. BUG=b:72875858 TEST=Booted, confirmed S5_MUX_CTRL high with and without this change. Change-Id: I9e047be7169586c59892ef2bdab915683feeebda Signed-off-by: Justin TerAvest <teravest@chromium.org> Reviewed-on: https://review.coreboot.org/23829 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-02-21mainboard/google/kahlee: Add tis_plat_irq_statusChris Ching
For variants that have a cr50 tpm, this enables faster polling when interacting with the tpm. BUG=b:72838769 BRANCH=none TEST=verified on grunt that irq is used and not timeouts for tpm Change-Id: I5786d334b6c1cc70f4c7107c75b07a7e27ac4428 Signed-off-by: Chris Ching <chingcodes@chromium.org> Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/23626 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-02-20mb/google/kahlee/OemCustomize.c: Disable bank interleaveRichard Spiegel
AmdInitPost returns AGESA_WARNING. This is because AGESA by default enables bank interleaving, while the HW does not meet the requirements for it. Disable bank interleaving, thus clearing AGESA_WARNING. BUG=b:73118857 TEST= Build and run kahlee. Search for "agesawrapper_amdinitpost() returned AGESA_SUCCESS". Change-Id: Ice9270f9b10051dbb622344919223cf5439f5d7b Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/23763 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-02-17soc/amd/stoneyridge: Normalize GPIO initJustin TerAvest
This makes the flow for GPIO initialization more closely follow that what is performed for other boards so that it's easier to read the flow (and stops relying on BS_WRITE_TABLES). BUG=b:72875858 TEST=Built and booted grunt, built gardenia. Change-Id: Ic97db96581a69798b193a6bdeb93644f6a74fc9d Signed-off-by: Justin TerAvest <teravest@chromium.org> Reviewed-on: https://review.coreboot.org/23679 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-02-14mb/*/spd: Use normal binary numbers (0b0010) instead of special format (2b0010)Jonathan Neuschäfer
This format (one hex digit, followed by 'b', followed by binary digits) is arguably useful, but also confusing. Use the more common format instead. Change-Id: Ide7b0a999483a2dd863a70f8aa42cd0865e2babf Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/23715 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Martin Roth <martinroth@google.com>
2018-02-12google/kahlee: Select HAVE_ACPI_RESUMEMarshall Dawson
TEST=Run powerd_dbus_suspend and resume with button press BUG=b:69614064 Change-Id: I0a5a610590b599b96dd0def211c4aa31c7a538ea Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/22732 Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-02-10mb/google/grunt: Add ADAU7002 to devicetreeDaniel Kurtz
Add an entry to the grunt devicetree defining the ADAU7002 PDM-to-I2S converter. BUG=b:72121803 TEST=With grunt audio kernel patches, "aplay -l" shows playback devices: **** List of PLAYBACK Hardware Devices **** card 0: acpd7219m98357 [acpd7219m98357], device 0: Playback da7219-hifi-0 [] Subdevices: 1/1 Subdevice #0: subdevice #0 card 0: acpd7219m98357 [acpd7219m98357], device 2: HiFi Playback HiFi-2 [] Subdevices: 1/1 Subdevice #0: subdevice #0 Change-Id: I90b59ec64f4b841932db42b8a8970ed924283613 Signed-off-by: Daniel Kurtz <djkurtz@chromium.org> Reviewed-on: https://review.coreboot.org/23660 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-02-10mb/google/kahlee: Add grunt audio codecs to devicetreeDaniel Kurtz
Remove manually written asl entries for grunt's DA7219 and MAX98357A audio codecs, and replace them with equivalent devicetree entries. BUG=b:72121803 TEST=With grunt audio kernel patches, "aplay -l" shows playback devices: **** List of PLAYBACK Hardware Devices **** card 0: acpd7219m98357 [acpd7219m98357], device 0: Playback da7219-hifi-0 [] Subdevices: 1/1 Subdevice #0: subdevice #0 card 0: acpd7219m98357 [acpd7219m98357], device 2: HiFi Playback HiFi-2 [] Subdevices: 1/1 Subdevice #0: subdevice #0 Change-Id: Ia658c54a28a5363aabb4c50478adaca1f46d166a Signed-off-by: Daniel Kurtz <djkurtz@chromium.org> Reviewed-on: https://review.coreboot.org/23658 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Justin TerAvest <teravest@chromium.org>
2018-02-07google/kahlee/grunt: Fix 2 device specific variablesAkshu Agrawal
* micbias_lvl -> micbias-lvl * mic_amp_in_sel -> mic-amp-in-sel BUG=b:71875600 TEST=Checked in kernel the values are set Change-Id: Ife7e8cdd835cc256cd8265593a94df84a510cebb Signed-off-by: Akshu Agrawal <akshu.agrawal@amd.com> Reviewed-on: https://review.coreboot.org/23603 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-02-06mb/google/kahlee: Fix grunt I2C rise/fall timesJustin TerAvest
I2C bus rise/fall times were measured as follows. Signals were generated with: - bus 0: manual i2c driver in depthcharge - bus 2,3: i2cdetect -r <bus_number> and then measured manually with an oscilloscope. BUG=b:72442912 Change-Id: I291e144249271ec34a93417398e54e68b8e21e23 Signed-off-by: Justin TerAvest <teravest@chromium.org> Reviewed-on: https://review.coreboot.org/23520 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-02-06mb/google/kahlee: Remove cmos.layoutRichard Spiegel
CMOS layout is not used and can be removed. A change to Kconfig is needed in order not to break the build. BUG=b:64207749 TEST=Build kahlee. Change-Id: Ib5d18e80a56111d96c730420db865194c71de1b3 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/23596 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-02-06google/kahlee: Initialize non-early i2c buses in mainboard_initDaniel Kurtz
Initialize non-early i2c buses in ramstage. BUG=b:69407112 TEST=Boot depthcharge w/ CLI enabled on grunt. devbeep => plays beep BRANCH=None Change-Id: I634a7a823cc393243841dbd55e52abe3f0e72c5a Signed-off-by: Daniel Kurtz <djkurtz@chromium.org> Reviewed-on: https://review.coreboot.org/23554 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-27 08:11:17 +0000