summaryrefslogtreecommitdiff
path: root/src/mainboard/google/kahlee
AgeCommit message (Collapse)Author
2017-09-27google/kahlee: Fix GPIO ASLMarc Jones
Use a single define and set the CROS GPIO ASL device to match the Stoney Ridge GPIO HID. Update the GPIO number to 142. Also, add a DDN field in the GPIO ASL. This addresses the TEST indicated below. BUG=b:65597554 BRANCH=none TEST=grep ^ /sys/devices/platform/chromeos_acpi/GPIO.*/* reports AMD0030. Change-Id: I1d6c42c6c9a0eef25e0e99aed6d838c767f5e01f Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/21614 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-26binaryPI boards: Fix indirect AGESA.h includeKyösti Mälkki
Change-Id: I3f6030879da61168adf42db0a4913d70a737594e Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21649 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-09-23mb/*/*: Remove rtc nvram configurable baud rateArthur Heymans
There have been discussions about removing this since it does not seem to be used much and only creates troubles for boards without defaults, not to mention that it was configurable on many boards that do not even feature uart. It is still possible to configure the baudrate through the Kconfig option. Change-Id: I71698d9b188eeac73670b18b757dff5fcea0df41 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/19682 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-09-20google/kahlee: Prevent AGESA memory clearMarc Jones
The Linux Pstore area must not be cleared on a reboot. Set the option to not clear the memory in AGESA. BUG=b:64193190 BRANCH=none TEST=Memory clear isn't called in AGESA. Change-Id: I9b8286ade718fa80bf3badd478ab9a7df643ab98 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/21596 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-09-20google/kahee: Fix number of memory channelsMarc Jones
Kahlee has a single memory channel, not two. This corrects DMI type 17 reporting and the memory clear functions. BUG=b:65403853, b:64193190 BRANCH=none TEST=AGESA DMI reports the correct number of DIMMs. Change-Id: Ic263d2677a480448beaf3850391b1a3d4ed38657 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/21595 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-19AGESA binaryPI: Clean up amdfamXX.h includeKyösti Mälkki
Change-Id: Iba8b8d33e1f10e28745234988d97d4fafd04c798 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21583 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2017-09-11kahlee: Add RO_VPD region in FMAPMarc Jones
The RO_VPD region is required for ChromeOS. BUG=b:65408869 TEST=Build and check coreboot.rom with fmap_decode. Change-Id: I9c475acc5e34a3a41f815990fb1f363963c7b9b9 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/21473 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-23soc/amd/stoneyridge ACPI: Sync sleepstates.asl definitionsKyösti Mälkki
Sync file with southbridge/amd/common/sleepstates.asl. SSFG was meant to be used as a mask to enable sleepstates _S1 thru _S4. However as a logical instead of bitwise 'and' operation was used, all the states were enabled if only one was marked available. Change-Id: I674953f1a5add74e16ddd84c252e8d21501ffefd Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21092 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2017-08-22google/kahlee: Enable ALS connected to ECAkshu Agrawal
Kahlee has an ambient light sensor connected to the EC. TEST=Can see the device in /sys/bus/iio BUG=b:62030268 Change-Id: Id1138a0fc5270489a734bdf8b1f4ac02d358c0df Signed-off-by: Akshu Agrawal <akshu.agrawal@amd.com> Reviewed-on: https://review.coreboot.org/21146 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-14stoneyridge: Rename hudson to southbridgeMarc Jones
Simplify funciton names and remove reference to hudson in stoneyridge. The southbridge in Stoney Ridge is Kern and hudson naming is no longer accurate. BUG=b:62200157 BRANCH=none TEST=Build and booted on Kahlee. Change-Id: Ide7a72dae69b881997101f1e37a1ac739901744d Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/20912 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-08-10google/kahlee: Set eMMC slotMarc Jones
Set AGESA SD/eMMc variable to non-removable eMMc. BUG=b:63891719 BRANCH=none TEST=Boot eMMC on Kahlee. Change-Id: I76ed9cec36a9688ebe75db2077f1ece4ab750c16 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/20911 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-08-04google/kahlee: Add ChromeOS SMBIOS Board IDMarc Jones
Kahlee uses 3 GPIO(144, 140, 135) pins to identify the board revision. Change-Id: Ia9693db6d6506af7ff40db0b3ce4cc6c1469f6ef Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19837 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-04soc/amd/stoneyridge: Use generic gpio libraryMarc Jones
Use the genric GPIO library. Add the required functions. Also, update the Kahlee mainboard dependency to match. Change-Id: I2ea562b052401efff3101f736788ca77d21e6de6 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/20543 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-08-03google/kahlee: Add Realtek audio codec ASLIvy Jian
Add the RT5650 codec ASL for proper Linux driver loading. Devices visible to OS: /sys/bus/acpi/devices/AMDI1002:00 /sys/bus/acpi/devices/I2SC1002:00 Change-Id: I60b256f68372c9d17d67c9cb2accaca616a0b9a5 Signed-off-by: Ivy Jian <ivy_jian@compal.com> Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19845 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-31google/kahlee: Add mainboard GPIOs to ACPIMarc Jones
Add the Google mainboard GPIOs to the ACPI table. Change-Id: I9b5952ed3934b938cb50650890a7b434e6306fd1 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/20313 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-31google/kahlee: Fix CTRL+U USB bootMarc Jones
The EC KBC controller was not initialized, so the EC wouldn't put keys in the output buffer. With nothing in the buffer, vboot didn't try to boot the USB stick. Add the driver to setup the KBC called by EC init. BUG=b:62066405 BRANCH=none TEST=Boot Kahlee with USB stick and CTRL+U boots the stick. Change-Id: If9346fda558e802536c7de38da5b21fd25320e40 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/20480 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-07-31google/kahlee: Move mainboard_ec_init to chip init phaseMarc Jones
Move mainboard_ec_init out of mainboard enable to the more appropriate mainboard init phase. Change-Id: Ieabcecf70e4de0b42fc639d031755b6d0b66f08a Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/20312 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-31soc/amd/stoneyridge: Move ACPI MADT table to socMarc Jones
Move the mainboard MADT tables to generic soc ACPI code. Change-Id: I49fb55b1315da8fe65421b43fc4312ed588d5ecb Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/20277 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-07-31google/kahlee: Add EC and GNVS ACPIMarc Jones
Add ACPI support for the Google EC, which requires GNVS support for passing information from the EC to firmware and OS. Change-Id: I0a308bcd608a135cc9633273a05527f020b60743 Signed-off-by: Marc Jones <marc.jones@scarletltd.com> Reviewed-on: https://review.coreboot.org/20276 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-31google/kahlee: Enable TPMMarc Jones
Set up the TPM decode to SPI prior to verstage. Enable LPC TPM and remove the mock data. Note, Kahlee TPM is on SPI, but decoded by the LPC block. BRANCH=none BUG=b:62103024 TEST=coreboot and Depthcharge reports TPM found. Change-Id: Iab92259ebeaa40937309fad05cc45d9ca6d41357 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19848 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-31google/kahlee: Save VBNV data to CMOSMarc Jones
Store VBOOT NV data in CMOS. This allows VBOOT to save flags and data to be used in multiple stages and depthcharge. Fixes developer mode USB boot. Change-Id: I50b45e687a1a1c71838bcc390212b28d7e634a19 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19847 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-31google/kahlee: Set DDI port 2 to DPMarshall Dawson
Set DDI port 2 type to Display Port. Change-Id: Idc5e57e01d4f0073ac50533c1b04a95bcae67473 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19846 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-31google/kahlee: Setup the I2S audio codecMarshall Dawson
Inform AGESA to setup an I2S codec instead of an Azalia codec. This is step one for audio to work. ASL to connect the driver and the hardware is in a follow-on patch. Change-Id: I7ece5d8c317ddc76e0e6b2a005256bc384fe51e2 Signed-off-by: Marc Jones <marc.jones@scarletltd.com> Reviewed-on: https://review.coreboot.org/19841 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-07-28google/kahlee: Add ASL for Elan touchpadIvy Jian
Add ASL for the Elan touchpad driver connection in ChromeOS. This is based on the Auron and Rambi ASL. The AMD ACPI code doesn't have the auto table generation the newer Intel Chrome SOC use. Device visible to OS: /sys/bus/acpi/devices/ELAN0000 Change-Id: Id3fc8c8855b0296f43a502e81143498d663468ec Signed-off-by: Ivy Jian <ivy_jian@compal.com> Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19844 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-28google/kahlee: Fix ASL whitespace and formattingMarc Jones
Clean up the ASL whitespace and formatting to match the iasl -d style as other parts of coreboot. Change-Id: I61689cb55dc26cbad160d45aa0a36c00b386fe0c Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19843 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-28google/kahlee: Remove conflicting AAHB IRQ ASLIvy Jian
The AMD internal A-link (AAHB device) doesn't support an IRQ, so remove it. This solves a conflict with the GPIO IRQ required for touchpad operation. Change-Id: Iefaf33cfb2babc29d35b5372fc3a338a72c78a4a Signed-off-by: Ivy Jian <ivy_jian@compal.com> Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19842 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-27google/kahlee: Set SERIRQ to continuous modeMarc Jones
The Kahlee Nuvoton EC firmware doesn't support SERIRQ quiet mode, yet. Set continuous mode until the quiet mode feature is available. This allows keyboard and other EC based interrupts through. Change-Id: If77c91fde2bd0f4da85413879fefb753ae6297de Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19840 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-27google/kahlee: Pass GPIO setting in amdinitenvMarshall Dawson
GPIOs for I2C3 were being unset in amdinitmid if the GPIO enable table wasn't passed. It had been initialy set in amdinitreset. Pull the GPIO settings into their own file that can be used in bootblock and later stages. Change-Id: I41cd7873f8c8543c95ad8653e0a3887f7d0487a2 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19839 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-27google/kahlee: Update PCIe link/lane configurationMarshall Dawson
Enable: GPP0 x1 - WLan GPP1 x1 - Card Reader Change-Id: Idbfc2a3260b85949810bdd8dc904e59f8a779e48 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19838 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-27google/kahlee: Set FADT legacy and 8042 supportedMarc Jones
The EC is a legacy 8042 device. Don't set LEGACY_FREE and correctly report in the FADT. Change-Id: I041ea4b44372178f3d6073b6ebc8003abc097703 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19836 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-07-27google/kahlee: Add ChromeOS and ChromeECMarshall Dawson
Add the basics for building as a ChromeOS device. ChromeOS and ChromeEC are dependent on each other, so bring them in together. The EC is a Nuvoton and you can find additional details in the Chromium EC repo. Add the Google HWID "Kahlee TEST 6421". The chromeos.fmd for Kahlee takes advantage of the AGESA located outside cbfs and includes typical RW, VPD, and MRC areas. There are some updates required to depthcharge, vboot, GPIOs, and the ChromeEC before we have a complete-ish system. Change-Id: Ifb0a6afc01dd80ef9e7bb81039d9152936043999 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19835 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-27google/kahlee: Update GPIO tableMarshall Dawson
Update GPIO settings based on the schematic. Change-Id: Ic8a876198a3ba9029d1aabb273418923e40bfcc6 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19834 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-07-27google/kahlee: Update for single DIMMMarshall Dawson
Update for a single DIMM with an SPD at address A0. Change-Id: I646f079c99cbaffd7094773243600c3030308325 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19833 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-07-27google/kahlee: Remove AMD IMCMarshall Dawson
Kahlee does not use the AMD IMC. Remove the files and calls. Change-Id: Ia837551b592b4f473eb38c06c516586fb6c95c88 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19832 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-07-27google/kahlee: Update KconfigMarc Jones
Update for the Stoney Ridge FT4 package and the on chip UART. Change-Id: I11468834a9ef03da084c156c74d55a19416d98c4 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19831 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-07-27google/kahlee: Start Kahlee mainboardMarc Jones
Copied from amd/gardenia. Update the appropriate board name strings. Uses the soc/ structure. Change-Id: Ia68b16969518f4d63d5d2dea7658a472b2daca05 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19830 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-27 11:37:38 +0000