coreboot.git - my copy of coreboot

Age	Commit message (Expand)	Author
2018-04-11	src/amd/stoneyridge: Fix a typo (EDGEL_TRIG -> EDGE_TRIG)	Jonathan Neuschäfer
2018-03-20	mainboard/google/kahlee: Initialize EC earlier in the bootblock	Martin Roth
2018-03-01	mb/{amd/gardenia,google/kahlee}: Initialize GPIOs earlier	Justin TerAvest
2018-02-21	mainboard/google/kahlee: Add tis_plat_irq_status	Chris Ching
2018-02-17	soc/amd/stoneyridge: Normalize GPIO init	Justin TerAvest
2017-12-09	mainboard/google/kahlee: Update PCIe port map	Martin Roth
2017-11-19	mb/google/kahlee: Move ec.h into variant include directories	Martin Roth
2017-11-19	mainboard/google/kahlee: Remove direct AGESA header includes	Martin Roth
2017-11-04	mainboard/google/kahlee: remove unused FILECODE macro	Aaron Durbin
2017-10-28	mainboard/google/Kahlee: Combine BiosCallOuts files	Martin Roth
2017-10-20	Stoney Ridge Platforms: cast AGESA tables to void *	Martin Roth
2017-10-20	Stoney Ridge Platforms: Make AGESA callout tables common	Martin Roth
2017-10-13	google/kahlee: Add AGESA_DO_RESET in bootblock	Marc Jones
2017-10-02	mainboard/amd: Add required callouts to Stoney BiosCallouts.c	Martin Roth
2017-09-26	binaryPI boards: Fix indirect AGESA.h include	Kyösti Mälkki
2017-08-14	stoneyridge: Rename hudson to southbridge	Marc Jones
2017-07-31	google/kahlee: Enable TPM	Marc Jones
2017-07-31	google/kahlee: Set DDI port 2 to DP	Marshall Dawson
2017-07-31	google/kahlee: Setup the I2S audio codec	Marshall Dawson
2017-07-27	google/kahlee: Pass GPIO setting in amdinitenv	Marshall Dawson
2017-07-27	google/kahlee: Update PCIe link/lane configuration	Marshall Dawson
2017-07-27	google/kahlee: Add ChromeOS and ChromeEC	Marshall Dawson
2017-07-27	google/kahlee: Update GPIO table	Marshall Dawson
2017-07-27	google/kahlee: Start Kahlee mainboard	Marc Jones