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path: root/src/mainboard/google/kahlee/Kconfig
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2018-07-16Kconfig: Make the EM100 config option commonSimon Glass
This applied to AMD devices as well as Intel, although the mechanism is different. Move the option to a common place. BUG=b:111363976 TEST=USE=em100-mode emerge-reef coreboot See that a message appears: * Enabling em100 mode (slow SPI flash) Change-Id: Iea437bdf42e7bc49b1d28c812bfc6128e3eb68bd Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-on: https://review.coreboot.org/27467 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-07-03mb/google/*: Remove selection of DRIVERS_PS2_KEYBOARDFurquan Shaikh
Until now, chromeec was doing keyboard initialization for the boards that have DRIVERS_PS2_KEYBOARD selected. However, coreboot does not leave the keyboard controller in a default reset state. This could result in payloads or OS failing to probe the controller as there could be stale data buffered in the controller during the handoff. Since the boards using chromeec already perform keyboard initialization in payload, there is no need to initialize the keyboard in coreboot too. This change gets rid of DRIVERS_PS2_KEYBOARD selection from all google mainboards using chromeec. BUG=b:110024487 TEST=Keyboard works fine after booting to OS even if user hits keys during BIOS to OS handoff. Change-Id: I1f49b060eb005c0f2b86f9d68d6758954eeb3cf0 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/27291 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-15mainboard/google/Kahlee: All variants identify as Grunt in SMBIOSMartin Roth
All Grunt variants should identify as grunt in SMBIOS so that they're recognized correctly as a unibuild Grunt variant. BUG=b:110244268 TEST=Careena identifies as grunt Change-Id: Iaf254149fbec9551d9220018d6d6a0a1be741538 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/27117 Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-11mainboard/google/kahlee: Remove Kahlee variantMartin Roth
This code is no longer needed. Removing Kahlee options allows some Kconfig options to be optimized. BUG=b:77693343 TEST=Build Grunt, verify that nothing's changed. Change-Id: I4eeeee7f35381bba8760c8a530251c475d0ee29b Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/26777 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-06-04security/tpm: Unify the coreboot TPM software stackPhilipp Deppenwiese
* Remove 2nd software stack in pc80 drivers directory. * Create TSPI interface for common usage. * Refactor TSS / TIS code base. * Add vendor tss (Cr50) directory. * Change kconfig options for TPM to TPM1. * Add user / board configuration with: * MAINBOARD_HAS_*_TPM # * BUS driver * MAINBOARD_HAS_TPM1 or MAINBOARD_HAS_TPM2 * Add kconfig TPM user selection (e.g. pluggable TPMs) * Fix existing headers and function calls. * Fix vboot for interface usage and antirollback mode. Change-Id: I7ec277e82a3c20c62a0548a1a2b013e6ce8f5b3f Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org> Reviewed-on: https://review.coreboot.org/24903 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-05-31mainboard/google/kahlee: Add careena variantMartin Roth
Add Careena variant, based on the grunt board. BUG=b:80106042 TEST=Build Careena Change-Id: I87a24f6d8115aacf5b21181f3820cf2718ad252a Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/26524 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-05-30mainboard/google/kahlee: move grunt's chromeos.fmd to baseboardMartin Roth
The chrmoeos.fmd file will be common across variants, so move it out of of grunt directory and into the variants/baseboard directory. BUG=b:80106042 TEST=Build grunt Change-Id: I259d85f60c5e19e00f7d9149542bcfdcc6dfaf4f Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/26656 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-05-02mb/google/kahlee/variants/grunt: Enable BayHub720 driverSimon Glass
Enable this driver along with power saving. BUG=b:73726008 BRANCH=none TEST=boot and see this message: BayHub BH720: Power-saving enabled 110103 From linux: $ iotools pci_read32 2 0 0 0x90 0x00110103 Change-Id: I850e923f73e01fe629d66ad61b65afa58035845c Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-on: https://review.coreboot.org/25967 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-04-27google/kahlee: Remove VBOOT_VBNV_CMOSMarc Jones
Remove VBOOT_VBNV_CMOS from the mainboard. It is selected in the stoneyridge Kconfig. BUG=b:77347873 TEST=Manually clear CMOS and check coreboot restores VBNV from flash. Change-Id: I30e517e06ab9d8f7d4a93bf82f12726756c44966 Signed-off-by: Marc Jones <marc.jones@scarletltd.com> Reviewed-on: https://review.coreboot.org/25844 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-02-12google/kahlee: Select HAVE_ACPI_RESUMEMarshall Dawson
TEST=Run powerd_dbus_suspend and resume with button press BUG=b:69614064 Change-Id: I0a5a610590b599b96dd0def211c4aa31c7a538ea Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/22732 Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-02-10mb/google/grunt: Add ADAU7002 to devicetreeDaniel Kurtz
Add an entry to the grunt devicetree defining the ADAU7002 PDM-to-I2S converter. BUG=b:72121803 TEST=With grunt audio kernel patches, "aplay -l" shows playback devices: **** List of PLAYBACK Hardware Devices **** card 0: acpd7219m98357 [acpd7219m98357], device 0: Playback da7219-hifi-0 [] Subdevices: 1/1 Subdevice #0: subdevice #0 card 0: acpd7219m98357 [acpd7219m98357], device 2: HiFi Playback HiFi-2 [] Subdevices: 1/1 Subdevice #0: subdevice #0 Change-Id: I90b59ec64f4b841932db42b8a8970ed924283613 Signed-off-by: Daniel Kurtz <djkurtz@chromium.org> Reviewed-on: https://review.coreboot.org/23660 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-02-10mb/google/kahlee: Add grunt audio codecs to devicetreeDaniel Kurtz
Remove manually written asl entries for grunt's DA7219 and MAX98357A audio codecs, and replace them with equivalent devicetree entries. BUG=b:72121803 TEST=With grunt audio kernel patches, "aplay -l" shows playback devices: **** List of PLAYBACK Hardware Devices **** card 0: acpd7219m98357 [acpd7219m98357], device 0: Playback da7219-hifi-0 [] Subdevices: 1/1 Subdevice #0: subdevice #0 card 0: acpd7219m98357 [acpd7219m98357], device 2: HiFi Playback HiFi-2 [] Subdevices: 1/1 Subdevice #0: subdevice #0 Change-Id: Ia658c54a28a5363aabb4c50478adaca1f46d166a Signed-off-by: Daniel Kurtz <djkurtz@chromium.org> Reviewed-on: https://review.coreboot.org/23658 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Justin TerAvest <teravest@chromium.org>
2018-02-06mb/google/kahlee: Remove cmos.layoutRichard Spiegel
CMOS layout is not used and can be removed. A change to Kconfig is needed in order not to break the build. BUG=b:64207749 TEST=Build kahlee. Change-Id: Ib5d18e80a56111d96c730420db865194c71de1b3 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/23596 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-02-01mb/google/kahlee: always load and run display opromAaron Durbin
The kernel requires the display oprom is loaded *and* ran in order for the kernel to not panic. Therefore, select the correct settings such that normal mode works for Chrome OS. BUG=b:72400950 Change-Id: Ibae5bc6b382cbe71a55c2386a24bb420cb8f313f Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/23506 Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-01-25mb/google/kahlee: Select DRIVERS_I2C_GENERICJustin TerAvest
This is required to add support for I2C devices on Kahlee to ACPI tables via devicetree.cb. Without this, operations are not emitted for I2C devices and the proper ACPI table entries are not generated. BUG=b:72121803 Change-Id: I1cfe12f3cc23e90ec74b739678f5a5a73257c2c2 Signed-off-by: Justin TerAvest <teravest@chromium.org> Reviewed-on: https://review.coreboot.org/23406 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-01-25mb/google/kahlee: Correct grunt HWID in GBBJustin TerAvest
Chrome OS reports that "GRUNT TEST XXXX" is an invalid hwid. The 8296 comes from the lower four numbers from running: $ printf "%d\n" 0x$(crc32 <(echo -n 'GRUNT TEST')) BUG=b:72436450 Change-Id: Ib0044442396cad65c25c107feb35a30a2f70b769 Signed-off-by: Justin TerAvest <teravest@chromium.org> Reviewed-on: https://review.coreboot.org/23411 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2018-01-23grunt: Enable TPMChris Ching
Kahlee uses LPC TPM while grunt is using Cr50 connected to I2C. Create the appropriate selection based on selected board, and if grunt then define the I2C address. BUG=b:69416132 BRANCH=none TEST=make all Change-Id: Ia866f80de0164d8cec84e204a5fe93bb53df547f Signed-off-by: Chris Ching <chingcodes@chromium.org> Reviewed-on: https://review.coreboot.org/22960 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-12-21google/kahlee: Select fanless SMU firmwareMarshall Dawson
Don't rely on the cascading default values. Ensure Kahlee uses the fanless versions of the SMU fimware by selecting it. Change-Id: I0761266f2a4026ebc251b64074c10481118734a2 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/22251 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-12-01mainboard/google/kahlee: Update Kconfig string used in makefilesMartin Roth
Update the variable ${CONFIG_VARIANT_DIR} to use parens instead. Either is valid, but since we use parentheses everywhere else, it's better to be consistent. BUG=b:69691210 TEST=Build grunt & kahlee Change-Id: Ieffabaae5516a893f1dc1f7195a17c4cdeae8853 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/22656 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-11-29google/kahlee: Add SPD functionMarc Jones
Add the mainboard_spd_read function in romstage and call the variants function. Grunt is the baseboard and has soldered down memory, so add it for the default weak SPD functions and build the SPDs in cbfs. Kahlee overrides the weak SPD function and falls back to the soc I2C SPD functions. BUG=b:67845441 TEST=Build and boot Kahlee. Change-Id: I789002bfadc1a2b24f9046708986d29c0e2daf33 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/22486 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2017-11-29google/kahlee: Rename board_id to memory_skuMarc Jones
The GPIOs used in board_id are meant to indicate the memory configuration. Rename board_id to memory_skus. Report the board_id received from the EC. BUG=b:69649438 Change-Id: I84bacead3daf829c97f595c4c11a243953243c29 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/22561 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2017-11-28mainboard/google/kahlee: Update Grunt for 16MB ROM chipMartin Roth
- Update Grunt to 16MB chip in Kconfig. - Move chromeos.fmd into variant directory & update Kconfig with the new location. - Add Grunt specific chromeos.fmd file. BUG=b:69691210 TEST=Build grunt; Build & Boot Kahlee Change-Id: I8d2f5e3255984d0d9a18df560f84f6db03b73a78 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/22580 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2017-11-13mainboard/google/kahlee: Add Grunt variant frameworkMartin Roth
Update common files and add files for grunt to the variant directory. BUG=b:68293392 TEST=Build only Change-Id: I7b80e470058872d6613e66e64c8dd1494942e9b9 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/22186 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-07mainboard/google/kahlee: Add MAINBOARD_FAMILYLann Martin
BUG=b:68865273 Change-Id: Ia2e9b10035e9dd502a563cdf8324ea8ea1922db3 Signed-off-by: Lann Martin <lannm@chromium.org> Reviewed-on: https://review.coreboot.org/22359 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-11-03mainboard/google/kahlee: Prepare for variantsMartin Roth
Move files that are particularly specific to the mainboard into the variant directory. Files that only have small areas of mainboard specific pieces use #if to separate between the boards. Add memory.c to split out the variant board id into a weak function. Add baseboard/gpio.h to satisfy the build - this will be updated in the next commit. BUG=b:68293392 Change-Id: I7c1beb45f571f2547f3b5b0d7ec78923d0cec761 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/22185 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-16src/mainboard/google/kahlee: Remove legacy tablesRichard Spiegel
Remove IRQ and MP tables. Modern OS use ACPI instead of legacy tables. Use Kconfig for reversable configuration if using old OS. BUG=b:62241143 Change-Id: I5fc833c8af47b5f6fad757e129250e6202810dbb Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/21963 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2017-10-16src/mainboard/kahlee: Default AMD FW position to 1MBMartin Roth
For Kahlee, the AMD firmware directory should be in the 1MB location so that it's in the RO cbfs section. BUG=b:65484600 TEST=Build & boot Change-Id: I650d8bc0bfa773f5fb5dc11167fe3db3b9550b68 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/22003 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-08-04google/kahlee: Add ChromeOS SMBIOS Board IDMarc Jones
Kahlee uses 3 GPIO(144, 140, 135) pins to identify the board revision. Change-Id: Ia9693db6d6506af7ff40db0b3ce4cc6c1469f6ef Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19837 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-31google/kahlee: Fix CTRL+U USB bootMarc Jones
The EC KBC controller was not initialized, so the EC wouldn't put keys in the output buffer. With nothing in the buffer, vboot didn't try to boot the USB stick. Add the driver to setup the KBC called by EC init. BUG=b:62066405 BRANCH=none TEST=Boot Kahlee with USB stick and CTRL+U boots the stick. Change-Id: If9346fda558e802536c7de38da5b21fd25320e40 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/20480 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-07-31google/kahlee: Enable TPMMarc Jones
Set up the TPM decode to SPI prior to verstage. Enable LPC TPM and remove the mock data. Note, Kahlee TPM is on SPI, but decoded by the LPC block. BRANCH=none BUG=b:62103024 TEST=coreboot and Depthcharge reports TPM found. Change-Id: Iab92259ebeaa40937309fad05cc45d9ca6d41357 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19848 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-31google/kahlee: Save VBNV data to CMOSMarc Jones
Store VBOOT NV data in CMOS. This allows VBOOT to save flags and data to be used in multiple stages and depthcharge. Fixes developer mode USB boot. Change-Id: I50b45e687a1a1c71838bcc390212b28d7e634a19 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19847 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-27google/kahlee: Set SERIRQ to continuous modeMarc Jones
The Kahlee Nuvoton EC firmware doesn't support SERIRQ quiet mode, yet. Set continuous mode until the quiet mode feature is available. This allows keyboard and other EC based interrupts through. Change-Id: If77c91fde2bd0f4da85413879fefb753ae6297de Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19840 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-27google/kahlee: Set FADT legacy and 8042 supportedMarc Jones
The EC is a legacy 8042 device. Don't set LEGACY_FREE and correctly report in the FADT. Change-Id: I041ea4b44372178f3d6073b6ebc8003abc097703 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19836 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-07-27google/kahlee: Add ChromeOS and ChromeECMarshall Dawson
Add the basics for building as a ChromeOS device. ChromeOS and ChromeEC are dependent on each other, so bring them in together. The EC is a Nuvoton and you can find additional details in the Chromium EC repo. Add the Google HWID "Kahlee TEST 6421". The chromeos.fmd for Kahlee takes advantage of the AGESA located outside cbfs and includes typical RW, VPD, and MRC areas. There are some updates required to depthcharge, vboot, GPIOs, and the ChromeEC before we have a complete-ish system. Change-Id: Ifb0a6afc01dd80ef9e7bb81039d9152936043999 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19835 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-27google/kahlee: Remove AMD IMCMarshall Dawson
Kahlee does not use the AMD IMC. Remove the files and calls. Change-Id: Ia837551b592b4f473eb38c06c516586fb6c95c88 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19832 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-07-27google/kahlee: Update KconfigMarc Jones
Update for the Stoney Ridge FT4 package and the on chip UART. Change-Id: I11468834a9ef03da084c156c74d55a19416d98c4 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19831 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-07-27google/kahlee: Start Kahlee mainboardMarc Jones
Copied from amd/gardenia. Update the appropriate board name strings. Uses the soc/ structure. Change-Id: Ia68b16969518f4d63d5d2dea7658a472b2daca05 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19830 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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