summaryrefslogtreecommitdiff
path: root/src/mainboard/google/jecht/variants
AgeCommit message (Collapse)Author
2022-12-27mainboard/acpi: Replace constant "Zero" with actual numberFelix Singer
Change-Id: I4f2f02623b060ef0ebefc5aceb713c77a8b1e9a6 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71523 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-27mainboard/acpi: Replace constant "One" with actual numberFelix Singer
Change-Id: Id1078b14a805eea53d2a7c5a8183a5413f26e115 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71521 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-14mb/google/jecht/acpi: Replace Store(a,b) with ASL 2.0 syntaxFelix Singer
Replace `Store (a, b)` with `b = a`. Change-Id: If6c37cc2ce51780e0bae007d884d8f77b20847fb Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70642 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-12mb/google/jecht/acpi: Replace LLessEqual(a,b) with ASL 2.0 syntaxFelix Singer
Replace `LLessEqual (a, b)` with `a <= b`. Change-Id: I4af47fdf5bab57c6bbfe417f55de35b074753120 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70621 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-12mb/google/jecht/acpi: Replace LEqual(a,b) with ASL 2.0 syntaxFelix Singer
Replace `LEqual (a, b)` with `a == b`. Change-Id: I74a6c949fa08a6eb712c053137369242e20e78fe Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70594 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-14broadwell: Move some MRC/refcode settings to devicetreeAngel Pons
There's no generic way to tell whether a mainboard has an EC or not. Making Kconfig symbols for these options seems overkill, too. So, just put them on the devicetree. Also, drop unnecessary assignments when the board's current value is zero, as the struct defaults to zero already. Change-Id: I8d3b352333bea7ea6f7b0f96d73e6c2d7d1a2cfb Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55809 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2022-08-13src/mb: Update unlicensable files with the CC-PDDC SPDX IDMartin Roth
These files contain no creative content, and therefore have no copyright. This effectively means that they are in the public domain. This commit updates the unlicensable empty (and effectively empty) files with the CC-PDDX identifier for license compliance scanning. Signed-off-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Change-Id: I0b76921a32e482b6aed154dddaba368f29ac2207 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66497 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-09mb/google/jecht/acpi: Replace LLess(a,b) with ASL 2.0 syntaxFelix Singer
Replace `LLess(a, b)` with `a < b`. Change-Id: Id61c537cc91edbd407fb6429eb4dd2bc8bc7f123 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60678 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2022-06-09mb/google/jecht: Replace Multiply(a,b,c) with ASL 2.0 syntaxFelix Singer
Replace `Multiply (a, b, c)` with `c = a * b`. Change-Id: Idc24216209bbfe73ef4197d4b8101f0d7e5891f7 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60652 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2022-06-09mb/google/jecht/acpi: Replace LGreaterEqual(a,b) with ASL 2.0 syntaxFelix Singer
Replace `LGreaterEqual(a, b)` with `a >= b`. Change-Id: I56e8fdb2503a84ded2bcf183402602579c3f2997 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60694 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2022-01-01mb/google/jecht/acpi: Replace LNot() with ASL 2.0 syntaxFelix Singer
Replace `LNot (a)` with `!a`. Change-Id: I4a9165b4610d7d035509b7f10eed0d9847afca1f Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60598 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2022-01-01mb/google/jecht: Replace LOr() with ASL 2.0 syntaxFelix Singer
Replace `LOr (a, b)` with `a || b`. Change-Id: Ib34e8af6668e3c875fabd1fa84862109afa94d18 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60577 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2021-12-31mb/google/jecht/acpi: Replace Add(a,b,c) with ASL 2.0 syntaxFelix Singer
Replace `Add (a, b, c)` with `c = a + b`. Change-Id: Ie7fa132623c7834e3d2f1acda032928579819a84 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60489 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2021-12-30mb/google/jecht/acpi: Replace Subtract(a,b,c) with ASL 2.0 syntaxFelix Singer
Replace `Subtract (a, b, c)` with `c = a - b`. Change-Id: I604a5c56e1941dd2932eaa5b44966e6ea06abb4c Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60474 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2021-12-29mb/google/jecht/acpi: Use Printf() for debug printsFelix Singer
Change-Id: Ie54637c451252fd38aab9207ab0b846cc50f4b12 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60427 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2021-09-17broadwell boards: Reflow USB2 parameter statementsAngel Pons
These statements fit on a single line. Reflow them to ease future works. Change-Id: Ie18e9a00f67b999fdcedcab3c28b68e34bc93da4 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55814 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-03-22lynxpoint/broadwell: Rename LP GPIO config globalAngel Pons
Do not use the same name as the non-LP GPIO config. This allows checking at build-time that a mainboard uses the correct GPIO config format. Without this commit, there are no build-time errors when using the wrong format of GPIO config, but there would be undefined behavior at runtime. Tested by trying to build asrock/b85m_pro4 and hp/folio_9480m after toggling the `INTEL_LYNXPOINT_LP` Kconfig option (and trimming down the USB config arrays for asrock/b85m_pro4). In both cases, building failed because the necessary GPIO config global is not defined, as expected. Change-Id: Ib06507ef8179da22bdb27593daf972e788051f3a Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51661 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-15broadwell boards: Switch to Lynxpoint GPIO headersAngel Pons
Move `CROS_GPIO_DEVICE_NAME` to a new `chromeos.h` header, because Lynxpoint uses a different value. Also drop unnecessary includes. Tested with BUILD_TIMELESS=1, Google Tidus remains identical. Change-Id: I38baed2c114fb93cfb82535a6ec00fb67e596d64 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50080 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-15mb/google/jecht/var/tidus: Switch to Lynxpoint GPIO macrosAngel Pons
Prepare to unify Lynxpoint LP and Broadwell GPIO code. Tested with BUILD_TIMELESS=1, Google Tidus remains identical. Change-Id: I1521a51455e2aa148298853bb1878e82b9f0c368 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50077 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-15mb/google/jecht/var/rikku: Switch to Lynxpoint GPIO macrosAngel Pons
Prepare to unify Lynxpoint LP and Broadwell GPIO code. Tested with BUILD_TIMELESS=1, Google Rikku remains identical. Change-Id: I4d5bec4ec18b645a14d21fbee7334761901a30df Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50076 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-15mb/google/jecht/var/jecht: Switch to Lynxpoint GPIO macrosAngel Pons
Prepare to unify Lynxpoint LP and Broadwell GPIO code. Tested with BUILD_TIMELESS=1, Google Jecht remains identical. Change-Id: I193fe1471b8ade5d03e874f92425962c1ed960c8 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50075 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-15mb/google/jecht/var/guado: Switch to Lynxpoint GPIO macrosAngel Pons
Prepare to unify Lynxpoint LP and Broadwell GPIO code. Tested with BUILD_TIMELESS=1, Google Guado remains identical. Change-Id: I3a806d07b0ca147492b90feaf90235ed919b1bb2 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50074 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-15soc/intel/broadwell/pch: Rename GPIO identifiersAngel Pons
Rename structs, types and functions to match Lynx Point's names. Tested with BUILD_TIMELESS=1, Purism Librem 13 v1 remains identical. Change-Id: I11ea27b00b5820eb5553712e0420836470ec0d27 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50064 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-13src: Remove unused '#include <stdint.h>'Elyes HAOUAS
unused includes of <stdin.h> found using following commande: diff <(git grep -l '#include <stdint.h>' -- src/) <(git grep -l 'int8_t\|uint8_t\|int16_t\|uint16_t\|int32_t\|uint32_t\|int64_t\| uint64_t\|intptr_t\|uintptr_t\|intmax_t\|uintmax_t\|s8\|u8\|s16\| u16\|s32\|u32\|s64\|u64\|INT8_MIN\|INT8_MAX\|UINT8_MAX\|INT16_MIN\ |INT16_MAX\|UINT16_MAX\|INT32_MIN\|INT32_MAX\|UINT32_MAX\|INT64_MIN\ |INT64_MAX\|UINT64_MAX\|INTMAX_MIN\|INTMAX_MAX\|UINTMAX_MAX' -- src/) |grep '<' |grep -v vendor |grep -vF '.h' Change-Id: Icb9b54c6abfb18d1e263665981968a4d7cccabeb Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41148 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-11treewide: Remove "this file is part of" linesPatrick Georgi
Stefan thinks they don't add value. Command used: sed -i -e '/file is part of /d' $(git grep "file is part of " |egrep ":( */\*.*\*/\$|#|;#|-- | *\* )" | cut -d: -f1 |grep -v crossgcc |grep -v gcov | grep -v /elf.h |grep -v nvramtool) The exceptions are for: - crossgcc (patch file) - gcov (imported from gcc) - elf.h (imported from GNU's libc) - nvramtool (more complicated header) The removed lines are: - fmt.Fprintln(f, "/* This file is part of the coreboot project. */") -# This file is part of a set of unofficial pre-commit hooks available -/* This file is part of coreboot */ -# This file is part of msrtool. -/* This file is part of msrtool. */ - * This file is part of ncurses, designed to be appended after curses.h.in -/* This file is part of pgtblgen. */ - * This file is part of the coreboot project. - /* This file is part of the coreboot project. */ -# This file is part of the coreboot project. -# This file is part of the coreboot project. -## This file is part of the coreboot project. --- This file is part of the coreboot project. -/* This file is part of the coreboot project */ -/* This file is part of the coreboot project. */ -;## This file is part of the coreboot project. -# This file is part of the coreboot project. It originated in the - * This file is part of the coreinfo project. -## This file is part of the coreinfo project. - * This file is part of the depthcharge project. -/* This file is part of the depthcharge project. */ -/* This file is part of the ectool project. */ - * This file is part of the GNU C Library. - * This file is part of the libpayload project. -## This file is part of the libpayload project. -/* This file is part of the Linux kernel. */ -## This file is part of the superiotool project. -/* This file is part of the superiotool project */ -/* This file is part of uio_usbdebug */ Change-Id: I82d872b3b337388c93d5f5bf704e9ee9e53ab3a9 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41194 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-06mb/google/jecht: Use SPDX for GPL-2.0-only filesAngel Pons
Done with sed and God Lines. Only done for C-like code for now. Change-Id: I90a3b2384797a15d5ac7f3cf9df808a5cfb1dc8c Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40178 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-18mainboard/google: Remove copyright noticesPatrick Georgi
They're listed in AUTHORS and often incorrect anyway, for example: - What's a "Copyright $year-present"? - Which incarnation of Google (Inc, LLC, ...) is the current copyright holder? - People sometimes have their editor auto-add themselves to files even though they only deleted stuff - Or they let the editor automatically update the copyright year, because why not? - Who is the copyright holder "The coreboot project Authors"? - Or "Generated Code"? Sidestep all these issues by simply not putting these notices in individual files, let's list all copyright holders in AUTHORS instead and use the git history to deal with the rest. Change-Id: I09cc279b1f75952bb397de2c3f2b299255163685 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39607 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2019-12-17mb/google/jecht: Add VBTs for all variantsMatt DeVillier
Add VBTs for jecht variants, extracted from VGA BIOS from stock firmware images using intelvbttool, zero-padded to 0x11ff bytes to make the Intel BMP editor happy. Use a common VBT for all except tidus, since it differs from the others. Change-Id: I570bdb749ef7d49f41539074220bb16c9c100342 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37735 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-05-14soc/intel/broadwell: Move GPIO init to a common placeArthur Heymans
This also links the gpio configuration instead of including it as a header. Change-Id: I9309d2b842495f6cff33fdab18aa139a82c1959c Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32759 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2019-03-20src: Use 'include <string.h>' when appropriateElyes HAOUAS
Drop 'include <string.h>' when it is not used and add it when it is missing. Also extra lines removed, or added just before local includes. Change-Id: Iccac4dbaa2dd4144fc347af36ecfc9747da3de20 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31966 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2018-11-30soc/intel/broadwell: Rework acpi/cpu.aslArthur Heymans
Use acpigen_write_processor_cnot to implement notifications to the CPU. Automatically generate \PPKG in SSDT. Change-Id: I79d2eed9b89b420554ce10d1fc0f151b1872afe2 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/29890 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2018-06-03intel bd82x6x/lynxpoint systems: Update ACPI thermal zone handlerMartin Roth
Currently the throttle event handler method THRM is defined as an extern on the intel bd82x6x and lynxpoint chipsets, then defined again in the platform with thermal event handling. In newer versions of IASL, this generates an error, as the method is defined in two places. Simply removing the extern causes the call to it to fail on platforms where it isn't actually defined, so add a preprocessor define where it's implemented, and only call the method on those platforms. This also requires moving the thermal handler, which now includes the define to before the gnvs asl file. TEST=Build before and after, make sure correct code is included. Change-Id: I7af4a346496c1352ec20bda8acb338b5d277d99b Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/26123 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-06-04google/jecht: add board-specific USB port infoMatt DeVillier
Add capability and location data for USB ports/devices via _PLD and _UPC ACPI methods, which is utilized by Windows and required by macOS. Each jecht variant has a different USB port config. Change-Id: I3b15aac9c4971e2ae230106016fba3a583ec6c9a Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/19971 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2016-12-22Combine Broadwell Chromeboxes using variant board schemeMatt DeVillier
Combine existing boards google/guado, rikku, and tidus using their common reference board google/jecht as a base. Additional changes besides simple consolidation include: - simplify power LED functions - simplify HDA verb definitions using azelia macros - use common SoC functions to generate FADT table - correct FADT table header version - remove unused haswell_pci_irqs.asl - remove unused header includes (various) - set sane default fan speed (0x4d) for all variants Variant setup modeled after google/beltino Change-Id: I77a2dffe9601734916a33fd04ead98016ad0bc4b Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/17913 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-13 12:56:21 +0000