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path: root/src/mainboard/google/jecht/devicetree.cb
AgeCommit message (Expand)Author
2022-12-05superio/ite/it8772f/chip.h: Use 'bool' when appropriateElyes Haouas
2022-11-25cpu/intel/haswell: Move chip_ops to cpu clusterArthur Heymans
2022-11-12soc/intel/broadwell: Hook up PCI domain and CPU cluster ops to devicetreeArthur Heymans
2022-08-14broadwell: Move some MRC/refcode settings to devicetreeAngel Pons
2022-01-04sb/intel: Use `bool` for PCIe coalescing optionAngel Pons
2021-01-24mb/google/jecht: Use Haswell CPU codeAngel Pons
2020-10-30soc/intel/broadwell: Separate PCH in devicetreeAngel Pons
2020-10-30mb/google/jecht: Prepare devicetree for PCH splitAngel Pons
2020-07-28broadwell: Factor out PIRQ routing from devicetreeAngel Pons
2020-07-26mb/*/*/devicetree.cb: Normalize disabled PIRQ valuesAngel Pons
2020-01-07mb/google/{beltino,jecht}: Drop SIO configuration linesNico Huber
2018-08-01mb/google,samsung/*: Add LPC TPM chip driver to devicetreeMatt DeVillier
2016-12-22Combine Broadwell Chromeboxes using variant board schemeMatt DeVillier
2015-06-09google/jecht: add new mainboardPatrick Georgi