summaryrefslogtreecommitdiff
path: root/src/mainboard/google/herobrine/Kconfig
AgeCommit message (Collapse)Author
2022-04-21tpm: Refactor TPM Kconfig dimensionsJes B. Klinke
Break TPM related Kconfig into the following dimensions: TPM transport support: config CRB_TPM config I2C_TPM config SPI_TPM config MEMORY_MAPPED_TPM (new) TPM brand, not defining any of these is valid, and result in "generic" support: config TPM_ATMEL (new) config TPM_GOOGLE (new) config TPM_GOOGLE_CR50 (new, implies TPM_GOOGLE) config TPM_GOOGLE_TI50 (new to be used later, implies TPM_GOOGLE) What protocol the TPM chip supports: config MAINBOARD_HAS_TPM1 config MAINBOARD_HAS_TPM2 What the user chooses to compile (restricted by the above): config NO_TPM config TPM1 config TPM2 The following Kconfigs will be replaced as indicated: config TPM_CR50 -> TPM_GOOGLE config MAINBOARD_HAS_CRB_TPM -> CRB_TPM config MAINBOARD_HAS_I2C_TPM_ATMEL -> I2C_TPM && TPM_ATMEL config MAINBOARD_HAS_I2C_TPM_CR50 -> I2C_TPM && TPM_GOOGLE config MAINBOARD_HAS_I2C_TPM_GENERIC -> I2C_TPM && !TPM_GOOGLE && !TPM_ATMEL config MAINBOARD_HAS_LPC_TPM -> MEMORY_MAPPED_TPM config MAINBOARD_HAS_SPI_TPM -> SPI_TPM && !TPM_GOOGLE && !TPM_ATMEL config MAINBOARD_HAS_SPI_TPM_CR50 -> SPI_TPM && TPM_GOOGLE Signed-off-by: Jes B. Klinke <jbk@chromium.org> Change-Id: I4656b2b90363b8dfd008dc281ad591862fe2cc9e Reviewed-on: https://review.coreboot.org/c/coreboot/+/63424 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-02-25herobrine: Add Villager variantShelley Chen
BUG=b:218415722 BRANCH=None TEST=./util/abuild/abuild -p none -t GOOGLE_VILLAGER -x -a -B Change-Id: I84935ea280023cb0df1dd51fcd2a83d80db17710 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62356 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-02-16mb/google/herobrine: Add Gigadevice SPI PartShelley Chen
BUG=b:182963902 BRANCH=None TEST=emerge-herobrine coreboot Change-Id: I73dc695afb7aa2b32aa966070eb057c828073d47 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62003 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-02-16mb/google/herobrine: Alphabetize SPI_FLASH configsShelley Chen
BUG=b:182963902 BRANCH=None TEST=None Change-Id: Ia73460d335e859644511b7e9ca80111a919baf2c Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62017 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-02-15herobrine: update SPI-NOR config optionsT Michael Turney
Configuration support for 4k-byte addressing mode BUG=b:215605946 TEST=Validated on qualcomm sc7280 developement board Signed-off-by: Veerabhadrarao Badiganti <quic_vbadigan@quicinc.com> Signed-off-by: Shaik Sajida Bhanu <quic_c_sbhanu@quicinc.com> Signed-off-by: T Michael Turney <quic_mturney@quicinc.com> Change-Id: If82de6204446251dded1b83684677e6eb536e6fd Reviewed-on: https://review.coreboot.org/c/coreboot/+/61279 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>
2022-02-04Hoglin: Switch to using i2c TPMShelley Chen
Redefine Hoglin to be used for Qualcomm's CRD 3.0 board, which uses i2c for TPM instead of SPI. From now on, the Piglin board will be used for all the Qualcomm reference boards that use SPI for TPM. BUG=b:206581077 BRANCH=None TEST=hacked an 8MB image and make sure boots on herobrine board Change-Id: Ie1d71ec8b01f305c1c8fa815a0fb9b7ee022cc19 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61604 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-01-07mb/google/herobrine: Initialize EC and TPM devicesShelley Chen
Initialize EC and H1/TPM instances on herobrine devices. BUG=b:182963902 BRANCH=None TEST=Validated on qualcomm sc7280 development board and verified booting on herobrine. Change-Id: I8cbdd1d59a0166688d52d61646db1b6764879a7c Signed-off-by: Roja Rani Yarubandi <rojay@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50581 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-01-04mb/google/herobrine: Transition BOARD_HEROBRINE to BOARD_HEROBRINE_REV0Shelley Chen
Deprecating Herobrine Rev0 board. The next board is very different from the Rev0 board (ie: Most GPIOs have been remapped). Deprecating and reusing the GOOGLE_BOARD_HEROBRINE Kconfig for next board and reslotting the old GOOGLE_BOARD_HEROBRINE source under GOOGLE_BOARD_HEROBRINE_REV0 config. Want to keep the code around in case somebody needs it but we can remove this code in future after we recall all the Rev0 devices. Also updating the remapped GPIOs to match those of the current herobrine board. BUG=b:211644878 BRANCH=None TEST=emerge-herobrine coreboot Change-Id: I67a0b282710031b927ce9022c7c535bd8d4ca1aa Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60284 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Douglas Anderson <dianders@chromium.org>
2021-09-29herobrine: Add fingerprint power sequencingShelley Chen
For Herobrine variants that include a finger print sensor, we will need to power sequence it. We are using the same FP sensor as trogdor, so we will follow the timings used for trogdor from CL:2695676. BUG=b:198474942 BRANCH=None TEST=./util/abuild/abuild -p none -t GOOGLE_HEROBRINE -x -a -c max -B Change-Id: Ica6eafc47cf1b95eeb8d94c6e0a8c88519665e3f Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58021 Reviewed-by: Alexandru Stan <amstan@chromium.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-20herobrine: Add Hoglin variantShelley Chen
Create a variant for the QC CRD device. BUG=b:197366666 BRANCH=None TEST=./util/abuild/abuild -p none -t GOOGLE_HOGLIN -x -a -B Change-Id: I883d17b3ad3c7e44a00f0d0e7007c119417c5028 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57720 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Bob Moragues <moragues@google.com> Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-09-16mb/google/herobrine: Increase the ROM size to 64 MBShaik Sajida Bhanu
SPI NOR size should match with coreboot ROM size. On QCOM Piglin board SPI NOR size is 64MB and the default coreboot ROM size is 8MB. So, update the coreboot ROM size to match with SPI NOR size. BUG=b:182963902 TEST=Validated on qualcomm sc7280 development board and checked basic boot up. Change-Id: I78f3f402b383bbad303f26c31d3d973c5f20d172 Signed-off-by: Shaik Sajida Bhanu <sbhanu@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55376 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>
2021-07-26mb/*: Specify type of `MAINBOARD_PART_NUMBER` onceAngel Pons
Specify the type of the `MAINBOARD_PART_NUMBER` Kconfig symbol once instead of doing so on each and every mainboard. Change-Id: I3692f9e82fe90af4d0da1d037018a20aa1b45793 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56554 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-26mb/*: Specify type of `MAINBOARD_DIR` onceAngel Pons
Specify the type of the `MAINBOARD_DIR` Kconfig symbol once instead of doing so on each and every mainboard. Change-Id: If1cc538b0c4938dac193699897b690e402b3c1e8 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56553 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-21mb/google/herobrine: Retrieve SKU ID from ECPhilip Chen
BUG=b:186264627 BRANCH=none TEST=build herobrine Signed-off-by: Philip Chen <philipchen@google.com> Change-Id: Id3faf7af64c0129ec646a01085adc43b561225d2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56354 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>
2021-06-29mb/google/herobrine: Add Senor and Piglin variantsShelley Chen
Add configs for Herobrine variants. Also enable ec sw sync as this should not be disabled by default. BUG=b:182963902 BRANCH=None TEST=./util/abuild/abuild -p none -t GOOGLE_SENOR -x -a -B ./util/abuild/abuild -p none -t GOOGLE_PIGLIN -x -a -B Change-Id: Ide4e375aa0236dce65a954a2f68455d05fa841eb Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55829 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-05-19herobrine: Enable macronix SPI configShaik Sajida Bhanu
Enable macronix SPI config on herobrine board. BUG=b:182963902 Change-Id: I505ee95d9f2ca16baf244135b3e2e8fe72f93491 Signed-off-by: Shaik Sajida Bhanu <sbhanu@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50583 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>
2021-04-15herobrine: sc7280: Provide initial mainboard supportT Michael Turney
BUG=b:182963902 TEST=Validated on qualcomm sc7280 developement board Change-Id: I428cf1a461ee63215f5683abbfed90202d1b2a88 Signed-off-by: Ravi Kumar Bokka <rbokka@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45206 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-27 13:09:47 +0000