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2019-11-16kohaku: Set GPP_A10 to NCShelley Chen
Setting GPP_A10 to NC now that older boards are deprecated and this GPIO is not in use anymore. BUG=b:142056166 BRANCH=hatch TEST=./util/abuild/abuild -p none -t google/hatch -x -a Change-Id: If8a249a3dcba90bb4ccb5e3f02595e680f789f93 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36869 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-14/mb/google/hatch: clean manufacturing information in spdWisley Chen
Clean the vendor/manufacturing information in 16G_3200_4bg spd to become generic spd. BUG=None TEST=emerge-hatch coreboot Change-Id: I163dc4631a6b71efd36c75cfe1fc759040113387 Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36810 Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-14/mb/google/hatch/var/dratini: Add new memory supportWisley Chen
1. ram id 8: 16G 2666 2 bank groups memory 2. ram id 9: 16G 3200 4 bank groups memory BUG=b:142762387 TEST=boot with memory (KAAG165WA-BCT/H5ANAG6NCMR-XNC) Change-Id: Ic63d911458b59de11c12ce776f6f7d04b1eb3b6c Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36667 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-13mb/google/hatch/variants/helios: Fix leakage voltage problem on touchscreenKane Chen
Set GPP_C4 default to low to fix leakage voltage problem on touchscreen during power on. BUG=b:142368161 BRANCH=Master TEST=emerge-hatch coreboot chromeos-ec chromeos-bootimage Flash FW to DUT, and make sure touchscreen works. Signed-off-by: Kane Chen <kane_chen@pegatron.corp-partner.google.com> Change-Id: Ie9197192c9d6dfb30c10559990c6010b1b2d3a45 Reviewed-on: https://review.coreboot.org/c/coreboot/+/36670 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Shelley Chen <shchen@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-12mainboard/google/hatch: Create helios_diskswap variantAlexis Savery
Created helios_diskswap as a variant of helios (hatch variant). BUG=b:143378037 BRANCH=None TEST=none Change-Id: I6536b3908ec569e1ac42ea7c5be85701012ab177 Signed-off-by: Alexis Savery <asavery@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36447 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2019-11-12/mb/google/hatch: add new memory config supportWisley Chen
1. Add 16G 2666 2 bank group 2. Add 16G 3200 4 bank group BUG=b:142762387 TEST=boot with memory (KAAG165WA-BCT/H5ANAG6NCMR-XNC) Change-Id: I04810091ef2bf8ec1bd306ad141a70436638eac8 Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36665 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2019-11-11Helios: Set the reset delay for Goodix touchscreen to 120msShelley Chen
With the 0.71586+ Goodix FW, we can reduce the reset delay from 500ms to 120ms. We should do the change in coreboot device tree after we ensure Helios DVT build is flashed with 0.71586+ Goodix FW. BUG=b:142316026 BRANCH=None TEST=./util/abuild/abuild -p none -t google/hatch -x -a Change-Id: I000ee4ea84c598b437992f1000f6e5b561cae605 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36655 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philip Chen <philipchen@google.com>
2019-11-08mb/google/hatch/var/akemi: disable unused USB port for Akemi platformPeichao Wang
Akemi platform dosen't support WWAN device and unused USB2 port 3, 4, 5, 7, 8 and USB3 port 3, 4, 5 so close them. BUG=None TEST=FW_NAME="akemi" emerge-hatch coreboot chromeos-ec chromeos-bootimage Signed-off-by: Peichao.Wang <peichao.wang@bitland.corp-partner.google.com> Change-Id: I7eff4da77caea7d4fe46597320be134d34d78a22 Reviewed-on: https://review.coreboot.org/c/coreboot/+/36644 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2019-11-07hatch: Create puff variantEdward O'Callaghan
Includes: - gpio mappings, - overridetree.cb, - kconfig adjustments for reading spd over smbus. V.2: Rework devicetree with comments and drop some useless gpio maps. BUG=b:141658115 TEST=./util/abuild/abuild -p none -t google/hatch -x -a Change-Id: I6449c4fcc1df702ed4f0d35afd7b0981e4c72323 Signed-off-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36452 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-11-07mainboard/google: Allow Hatch variants to read SPD data over SMBusEdward O'Callaghan
All Hatch variants so far embed static SPD data encoded within the firmware image. However we wish the flexibility for romstage implementations that allow for reading the SPD data dynamically over SMBus. This romstage variant allows for reading the SPD data over SMBus. V.2: Dispence with memcpy(). V.3: Revert back to previous patch with memcpy(). V.4: Rewrite again to avoid memcpy(). BRANCH=none BUG=b:143134702 TEST=./util/abuild/abuild -p none -t google/hatch -x -a Change-Id: I3516a46b91840a9f6d1f4cffb2553d939d79cda2 Signed-off-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36449 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-07mb/google/hatch/variants/helios: Modify touchscreen power on sequenceKane Chen
The previous values do not affect the touchscreen function. But, the previous values cause the power leakage in S0ix. from b/142368161: 1. Modify GPP_D: The specification define T1 >= 10ms. We change it to 12ms for a safety and low impact value in our mind. Enable pin as GPP_D9 is define to be AVDD in specification. Set it to 10ms to make it to be the final one to pull low during power off sequence . 2. Add GPP_C4: If we set stop_off_delay_ms to be 1. The true T4 we got will be 300us . Set stop_off_delay_ms to be 2 . True T4 will be 500us . So we change it to 5 to be a low impact value in our mind according to the true T4 value we got . BUG=b:142368161 BRANCH=Master TEST=emerge-hatch coreboot chromeos-bootimage ./util/abuild/abuild -p none -t google/hatch -x -a Signed-off-by: YenLu Chen <kane_chen@pegatron.corp-partner.google.com> Change-Id: I86c920ff1d5c0b510adde8a37f60003072d5f4e7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/35907 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Shelley Chen <shchen@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-06mainboard/google: Rework Hatch so that SPD in CBFS is optionalEdward O'Callaghan
All Hatch variants so far embed static SPD data encoded within the firmware image. However we wish the flexibility for romstage implementations that allow for reading the SPD data dynamically over SMBus. BRANCH=none BUG=b:143134702 TEST=./util/abuild/abuild -p none -t google/hatch -x -a Change-Id: Ie1637d08cdd85bc8d7c3b6f2d6f386d0e0c6589b Signed-off-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36250 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-11-05mb/google/hatch/variants/helios: Update TSR3 sensor thresholdsSumeet Pawnikar
Update thermal threshold settings for TSR3 sensor. There is an issue fan is always running, even during system idle state. This change fixes this issue and fan starts only when it breaches the temperature threshold. BRANCH=None BUG=b:143861559 TEST=Built and tested on Helios system Change-Id: Ia417f8c51442005cc8c2251c188cebc197e0a773 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36609 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Shelley Chen <shchen@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-04mb/google/hatch: update DLL values for KindredJamie Chen
Update emmc DLL values for Kindred BUG=b:131401116 BRANCH=none TEST=Boot to OS 100 times on Kindred EVT Change-Id: Ibd840b31bb0e5a742495758de55b532e6c3946aa Signed-off-by: Jamie Chen <jamie.chen@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36076 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Shelley Chen <shchen@google.com>
2019-11-01soc/intel/{cnl,icl}: Move globalnvs.asl/nvs.h into common/block/Subrata Banik
This patch creates a common instance of globalnvs.asl/nvs.h inside intel common code (soc/intel/common/block/) and ask cnl & icl soc code to refer globalnvs.asl and nvs.h from common code block. TEST=Able to build and boot Hatch and ICL DE system. Dump DSDT.asl to verify GNVS operation region presence after booting to OS. Change-Id: Ia9fb12a75557bd7dc38f6d22ba2b32065d18b3ee Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36457 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Michael Niewöhner Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-11-01soc/intel/{IA-CPU/SOC}: Move sleepstates.asl into southbridge/intel/common/acpiSubrata Banik
This patch creates a common instance of sleepstates.asl inside intel common code (southbridge/intel/common/acpi) and asks all IA CPU/SOC code to refer sleepstates.asl from common code block. TEST=Able to build and boot Hatch and ICL DE system. Dump DSDT.asl to verify S0/S3/S4/S5 entries after booting to OS. Change-Id: Ie2132189f91211df74f8b5546da63ded4fdf687a Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36463 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-30mb/google/hatch/variants/helios: Modify DPTF parametersKane Chen
Modify DPTF parameters. Modify TDP PL1 values to 15. Remove TCHG Level 3 - 0.5A. BUG=b:131272830 BRANCH=none TEST=emerge-hatch coreboot chromeos-bootimage Signed-off-by: YenLu Chen <kane_chen@pegatron.corp-partner.google.com> Change-Id: I0e5c079856a167b1c2ef52e446d055404e565858 Reviewed-on: https://review.coreboot.org/c/coreboot/+/35794 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-30hatch: refactor gpio table into baseboard, allow empty SPDsPaul Fagerburg
Each variant needed to define variant_early_gpio_table(), even if it didn't need to make any changes. Added a __weak version of the function into baseboard/gpio.c. Certain upcoming Hatch variants will not use SPD files. Allow SPD_SOURCES in spd/Makefile.inc to be empty. BUG=None BRANCH=None TEST=Build coreboot and see that it builds without error Change-Id: Ie946cfd7c071824168faa38fd53bd338a5a451e1 Signed-off-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36068 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-27Dragonair: Add sku23Wisley Chen
BUG=b:142987639 TEST=emerge-hatch coreboot Change-Id: I0ff1a81d0579d0b328a48bc7d4f867592ec63e8b Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36335 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philip Chen <philipchen@google.com> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2019-10-25mb/google/hatch: Configure GPIOs in mainboard chip->init()Furquan Shaikh
mainboard_silicon_init_params() is supposed to be used for only overriding any FSP params as per mainboard configuration. GPIOs should be configured by mainboard as part of its chip init(). This ensures proper ordering w.r.t. any common operations that the SoC code might want to perform e.g. snapshot ITSS polarities. This change moves the configuration of GPIOs from mainboard_silicon_init_params() to mainboard chip->init(). Additionally, this change moves mainboard_ec_init() to mainboard dev->init(). TEST=Verified that GPIOs are configured properly and hatch boots to OS. Change-Id: Ia509471a3678c60454cd4f14625f151860d9b9d2 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36267 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-25mb/google/hatch: Set DSM parameters for HeliosCheng-Yi Chiang
Set VPD keys for DSM parameters in overridetree.cb for Helios. RT1011 driver will load values from VPD and set them to device property. BUG=b:140397934 BRANCH=none TEST=On Helios, with patch series, check realtek,r0_calib and realtek,temperature_calib are available to rt1011 codec driver. Signed-off-by: Cheng-Yi Chiang <cychiang@chromium.org> Change-Id: Ic72fd57becf93e70a1a716dbb76633509f2fd5c1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/36031 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-10-25mb/google/hatch: Fix speaker mapping for HeliosCheng-Yi Chiang
The correct mapping for speakers to their names should be: uid 0: Woofer Left uid 1: Woofer Right uid 2: Tweeter Left uid 3: Tweeter Right Also, fix the name to be 4-character. BUG=b:140397934, b:143192767 BRANCH=none TEST=On Helios, with patch series, check realtek,r0_calib and realtek,temperature_calib are available to rt1011 codec driver. And the speaker mapping is correct. Change-Id: I353fb9ad0ca8ec85431eb2b59be748b4887278cf Signed-off-by: Cheng-Yi Chiang <cychiang@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36256 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-24mb/google/hatch/var/akemi: Update DPTF thermal sensor for AkemiPeichao Wang
Add thermal sensor: TSR2 to ACPI table, monitor CPU temperature BUG=b:143046086 TEST=FW_NAME="akemi" emerge-hatch coreboot chromeos-ec chromeos-bootimage Signed-off-by: Peichao.Wang <peichao.wang@bitland.corp-partner.google.com> Change-Id: Id150c5c3cb6d07407fd20417237457b5722e6f2d Reviewed-on: https://review.coreboot.org/c/coreboot/+/36052 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com> Reviewed-by: Philip Chen <philipchen@google.com>
2019-10-24mb/google/hatch: Select RT1011 and CHROMEOS_DSM_CALIB for HeliosCheng-Yi Chiang
Use RT1011 driver for Helios. Select CHROMEOS_DSM_CALIB to set device properties for RT1011 speaker calibration. BUG=b:140397934 BRANCH=none TEST=On Helios, with patch series, check realtek,r0_calib and realtek,temperature_calib are available to rt1011 codec driver. Signed-off-by: Cheng-Yi Chiang <cychiang@chromium.org> Change-Id: I1010be15466c5060aa1d73318393853a2515daac Reviewed-on: https://review.coreboot.org/c/coreboot/+/36030 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2019-10-22mb/google/hatch: Enable PchPmSlpS0Vm075VSupport for hatchKane Chen
On hatch and variant HW designs supports VCCPRIM_CORE Low Voltage Mode. VCCPRIM_CORE can be down to 0.75v when slp_s0 is asserted. This commit enables PchPmSlpS0Vm075VSupport UPD so that FSP can program related setttings to save power. BUG=b:134092071 TEST=Run suspend_stress_test on kohaku and pass 100 cycles Change-Id: Ia02ff8823883489b36349457213409496f082f36 Signed-off-by: Kane Chen <kane.chen@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35596 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-10-22mb/mainboard/hatch: support Goodix touch panel for AkemiPeichao Wang
Configure enable pin GPP_D9 pull high when active BUG=b:143046441 TEST=build bios and verify touch screen works fine Signed-off-by: Peichao.Wang <peichao.wang@bitland.corp-partner.google.com> Change-Id: I83060f31d4d22c9be05bba119816c6aa66e4126c Reviewed-on: https://review.coreboot.org/c/coreboot/+/36186 Reviewed-by: Philip Chen <philipchen@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-21src/{device,drivers,mb,nb,soc,sb}: Remove unused 'include <console/console.h>'Elyes HAOUAS
Change-Id: I0c965e598e260ff8129aa07fb9fc5bf6e784e1d8 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36057 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-10-21mb/google/hatch/var/dratini: Add ELAN touchscreen supportWisley Chen
Add ELAN EKTH6915 USI touchsreen support. BUG=b:139392144 TEST=check touchscreen work, and confirmed power sequence with vendor. Change-Id: I8ebc067bbb407498de00ea0b6c23b0848023cffe Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36125 Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Shelley Chen <shchen@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-21mb/google/hatch/akemi: disable unused devices for AkemiPeichao Wang
Akemi unused devices declare: - I2C #1 gpio_keys - close I2C #3 - close GSPO #1 BUG=b:142800988 TEST=Reboot stress test and suspend stress test, the DUT will be able to working properly Signed-off-by: Peichao.Wang <peichao.wang@bitland.corp-partner.google.com> Change-Id: Ibff1446ccb213abce1a2ae19718774d9d6737cc9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/36086 Reviewed-by: Ben Kao <ben.kao@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-18mb/google/hatch/var/dratini: Update DPTF parametersWisley Chen
The change applies the DPTF parameters. BUG=b:142849037 TEST=build and verified by thermal team Change-Id: I5da8d373f38d23929ffec95bc1c9e942f131297f Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36098 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2019-10-18mb/google: Shrink GBB section sizeHung-Te Lin
Chrome OS firmware images have moved bitmap resources from GBB into CBFS for a long time, so the GBB should only hold firmware keys and HWID, that is usually less than 10k. ARM boards usually limit GBB to 0x2f00 (see gru, cheza and kukui) but many recent x86 simply copy from old settings and may run out of space when we want to add more resources, for example EC RO software sync. Note, changing the GBB section (inside RO) implies RO update, so this change *must not* be cherry-picked back to old firmware branches if some devices were already shipped. BRANCH=none BUG=None TEST=make # board=darllion,hatch,kahlee,octopus,sarien Change-Id: I615cd7b53b556019f2d54d0df7ac2723d36ee6cf Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36088 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Mathew King <mathewk@chromium.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-10-16mb/google/hatch/akemi: Tune I2C bus 1 clockPeichao Wang
Tune I2C bus 1 clock and insure it meets I2C spec. BUG=b:142683257 TEST==flash coreboot to the DUT and measure I2C bus 1 clock frequency less than 400KHz Signed-off-by: Peichao.Wang <peichao.wang@bitland.corp-partner.google.com> Change-Id: Id4cdbad4dd9d451763fb536988402d6e6fe3a378 Reviewed-on: https://review.coreboot.org/c/coreboot/+/36050 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2019-10-16mb/google/hatch/var/dratini: Add enable pin for elan touchscreenWisley Chen
Add enable pin for elan touchscreen BUG=b:142710871 TEST=touchscreen work Change-Id: I09b6ffb962272bfe46e63b057be885b1bdf13554 Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36061 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2019-10-16mb/google/hatch/var/dratini: update goodix power sequenceWisley Chen
Update power sequence to meet spec. BUG=b:142710867 TEST=touchscreen work, and make sure power sequence to meet spec with vendor. Change-Id: I98f8b095374caa8c3540307a51f9d3b69baec905 Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36060 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-15helios: Add TEMP_SENSOR4 to DPTFPaul Fagerburg
Helios adds TEMP_SENSOR4 to the EC ADC2 pin. Add this to the DPTF. BRANCH=None BUG=b:142266102 TEST=`emerge-hatch coreboot` Verify that Helios builds correctly. Change-Id: I3bc19f9b9bd644e134987749ad9a4d875ad8b40a Signed-off-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35920 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>
2019-10-15mb/google/hatch: set wifi sar for dragonairWisley Chen
Enable wifi sar feature and set wifi sar name for dragonair sku. BUG=b:142109545 TEST=emerge-hatch coreboot chromeos-bootimage 1. Check wifi_sar-dragonair.hex in /cbfs-rw-raw/dratini 2. Add iwlwifi.debug into kernel params. 3. check SAR value from dmesg only when sku id is 21/22 Change-Id: I0e08610b7c7d2d8da5a749d278bcde26af590e31 Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35807 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2019-10-15mb/google/hatch: Initialize FPMCU_PCH_BOOT1Wisley Chen
FPMCU_PCH_BOOT1 pin is connected to GPP_C12. So, config GPP_C12. BUG=b:142188003 TEST=emerge-hatch coreboot Change-Id: I73a5c3529330ef3e72f4c7d5fcbbd2f6693494d8 Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35845 Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-11mb/google/hatch: Add new touchscreen option for KohakuTim Wawrzynczak
The next board rev will have a new option for an Elan touchscreen. Add support for this in the devicetree, as well as use the 'probed' property on both touchscreen options. BUG=b:141957731 BRANCH=none TEST=compiles (next board rev not available yet) Change-Id: I135e693304cbb8dffc0caf4c07846033d6802208 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35944 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Shelley Chen <shchen@google.com>
2019-10-09mb/google/hatch: Remove pen device for dratini/dragonairWisley Chen
Dratini/Dragonair doesn't support pen insertion/ejection feature, so remove it. BUG=b:142159117 TEST=emerge-hatch coreboot Change-Id: I64859a162d8dc75ffe55d98b72a056dd72e8de75 Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35844 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Shelley Chen <shchen@google.com>
2019-10-09mb/[google/intel/lenovo]/*: fix posix shell bug with SPD filesGreg V
FreeBSD's sh (basic posix shell) did not interpret the '\%o' escape in the same way bash/zsh do. As a result, the decoded files ended up with ASCII numbers instead of the decoded binary data. Change-Id: I95b414d959e5cd4479fcf100adcf390562032c68 Signed-off-by: Greg V <greg@unrelenting.technology> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35867 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-10-09mb/google/hatch: Set FPS as wake sourceShelley Chen
BUG=b:142131099 BRANCH=None TEST=powerd_dbus_suspend, ensure DUT in S0ix touch fp sensor and ensure DUT wakes up in S0 Change-Id: If57094aa1076d79ac0886b71fa5532411bfeb45f Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35903 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2019-10-08mb/google/kohaku: Assign GPP_A19 as reset_gpio of stylusSeunghwan Kim
Applying reset_gpio config of stylus for kohaku. GPP_A19 has been assigned in the latest schematics. We would keep GPP_A10 as output high for old revision devices temporarily. BUG=b:141914474 BRANCH=none TEST=verified stylus works internally Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com> Change-Id: I61f0f9a4378f47bf455f0726d44beeaf2f67197b Reviewed-on: https://review.coreboot.org/c/coreboot/+/35748 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>
2019-10-07mb/google/hatch: Preserve MRC training data across FW updateShelley Chen
Add PRESERVE to UNIFIED_MRC_CACHE so that we don't retain the memory training data upon a FW update unless we need to. We have had users complaining that a 15 second memory training upon update makes them believe that their device is not booting, thus many of them hard resetting before bootup. BUG=b:142084637 BRANCH=None TEST=flash RW_SECTION_A, RW_SECTION_B, and WP_RO sections and make sure memory training doesn't occur on following bootup. Change-Id: Ia5eb228b1f665a8371982544723dab3dfc40d401 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35803 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-03mb/[google/intel]/*: Specify Chrome EC bus - LPC or ESPIMartin Roth
Previously all boards using eSPI for the Chrome EC just called it LPC as the code for the chrome EC is the same between the two busses. I'm adding a new Kconfig symbol to specify eSPI, so switch the boards that actually use eSPI to that symbol and add the LPC symbol to all the others. The EC_GOOGLE_CHROMEEC_LPC symbol will no longer default to enabled for x86 platforms, so one symbol or the other needs to be specified for each platform. BUG=b:140055300 TEST=Build tested only. Change-Id: Icf242ca2b7d8b1470feda4e44b47a2cdc20680f2 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35153 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-10-02soc/intel: Replace config_of_path() with config_of_soc()Kyösti Mälkki
The previously provided device path made no difference, all integrated PCI devices point back to the same chip_info structure. Change reduces the exposure of various SA_DEVFN_xx and PCH_DEVFN_xx from (ugly) soc/pci_devs.h. Change-Id: Ibf13645fdd3ef7fd3d5c8217bb24d7ede045c790 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35656 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-09-30mb: remove test-only HWIDsHung-Te Lin
The CONFIG_GBB_HWID can be generated automatically now so we can remove the test-only HWIDs set in board config files. BUG=b:140067412 TEST=Built few boards (kukui, cheza, octopus) and checked HWID: futility gbb -g coreboot.rom Change-Id: I4070f09d29c5601dff1587fed8c60714eb2558b7 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35635 Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-26mb/mainboard/hatch: support elan touchpad for AkemiPeichao Wang
Modify IRQ pin from D21 to A21 and support wake-up from touchpad BUG=b:141519690 TEST=build bios and verify elan touchpad works fine Signed-off-by: Peichao Wang <peichao.wang@bitland.corp-partner.google.com> Change-Id: I6cc5b780ffcee24f1f2a04e88c30628ceb5904e8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/35551 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Shelley Chen <shchen@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-25mb/google/hatch: Move SOC_INTEL_COMETLAKE selection to KconfigFurquan Shaikh
All variants of hatch are using Comet Lake and so the selection can be done in Kconfig without requiring each variant to do the same. Change-Id: Ief34296334ede5ba0f5f13381e92427ccc440707 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35562 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Andrew McRae <amcrae@chromium.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
2019-09-24mb/google/kohaku: Update DPTF parameters and TCC offset settingSeunghwan Kim
This change applies fine-tuned DPTF parameters and TCC offset setting for kohaku. Also enables EC_ENABLE_MULTIPLE_DPTF_PROFILES for tablet mode. BUG=b:137688474 BRANCH=none TEST=built and verified the setting values Change-Id: I92e268b2e07ca5a04e29bda84ddb8fc21eb23251 Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35532 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>
2019-09-22mb/mainboard/hatch: add spd: 8G_3200 for AkemiPeichao Wang
BUG=b:140545732 TEST=build bios and spd index set to 6, verify DUT bring up normally Signed-off-by: Peichao Wang <peichao.wang@bitland.corp-partner.google.com> Change-Id: I337b0bdcd37a9c4baacccbc6786968031a41b31e Reviewed-on: https://review.coreboot.org/c/coreboot/+/35511 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-22mb/google/hatch: Add G2Touch Touchscreen supportWisley Chen
Add G2Touch Touchscreen support for dratini BUG=b:141281841 TEST=emerge-hatch coreboot chromeos-bootimage, and check touchscreen work. Change-Id: I0dbde7f8396da6335b22aeb4a9703336e2b862b8 Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35470 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2019-09-20mb/google/hatch: Remove GPIO_DRIVER from pen eject GPIO configurationTim Wawrzynczak
A closer read of the EDS indicates that when GPIO Driver mode is selected, GPIO input event updates are limited to GPI_STS only. GPI_GPE_STS updates are therefore masked, and we don't want to enable this behavior. It masks the GPE and does not allow us to see this GPE as a wake source, obscuring the reason that the system woke up. Also switch the IRQ from level-triggered to edge-triggered, otherwise the system will auto-wake from any sleep state when the pen is ejected from the garage. BUG=b:132981083 BRANCH=none TEST=Wake up system from S0ix using pen eject, verify that mosys eventlog shows GPE#8 as the S0ix wakeup source. Wake up system from S3 via pen eject, and verify that the wakeup source shows as GPE#8. Change-Id: If017e12e23134f5cfed7cbb6047cc9badd9bf7e8 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35459 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-20mb/google/hatch: override smbios manufacturer name from CBIWisley Chen
BUG=none TEST=emerge-hatch coreboot, use ectool to write oem name in CBI, and checked smbios manufacturer name. Change-Id: I9be85fbc47031d049b5bd51cfaf6232cab24e9fe Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35345 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-09-18mb/google/hatch/variants/helios: Add DPTF control for ambient sensorSumeet Pawnikar
Add DPTF based thermal control for ambient sensor for CML based Helios system. Also, update other sensor names information. BUG=b:139335207 BRANCH=None TEST=Build and Boot on Helios board and check all sensor details. Change-Id: I322d53536fbdf6db70f5a24afb322d9f206eaeac Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35447 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-09-18mb/google/hatch/variants/helios: Update DPTF parametersSumeet Pawnikar
Update DPTF thermal temperature threshold values for CML based Helios system. This updates CPU active cooling temperature threshold to appropriate values which addresses the issue of running the Fan at lower CPU temperature as per bug. Also, added active cooling temperature thresholds for other TSR sensors. BUG=b:141087272 BRANCH=None TEST=Build and boot on Helios board to check the fan functionality. Change-Id: I5c8502f8c9e6121c18024d2a8d5a4f7680797b8d Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35446 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-16mb/google/kohaku: Update USB port settingsSeunghwan Kim
This change overrides USB port settings for kohaku. Some port settings are same with baseboard, but I'd like to describe all settings here to be aware of current setting and usage of USB ports on kohaku. BUG=none BRANCH=none TEST=built and measured SI of USB ports internally Change-Id: I5ac05485d1cd94416e5a0aecf7fa6769bd7c9e84 Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35236 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-09-13mb/google/hatch: Merge emmc_sku_gpio_table and gpio_table to one tablePeichao Wang
BUG=b:140008849, b:140573677 TEST=verify eMMC SKU and SSD SKU will bring up normally. Signed-off-by: Peichao Wang <peichao.wang@bitland.corp-partner.google.com> Change-Id: I0c0adf569cc92e8b44ab72379420f2b190fa31f5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/35344 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marco Chen <marcochen@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Justin TerAvest <teravest@chromium.org>
2019-09-13mb/google/hatch/var: Increase Goodix touchscreen reset delay to 500msPhilip Chen
Even though GT7375P programming guide rev0.4 only requires a reset delay of 120ms, in practice, we have to increase the reset delay to 500ms, or Goodix FW update would fail. This is a workaround. In the long run, we hope Goodix can fix the power sequence in touch firmware. BUG=b:138795891, b:138796844 TEST=boot helios board and verify Goodix FW update succeeded Signed-off-by: Philip Chen <philipchen@google.com> Change-Id: Ic0049bf240de0a1c7f1b1f39bf155d48bb76fb86 Reviewed-on: https://review.coreboot.org/c/coreboot/+/35350 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-12mb/google/hatch: Configure SATA DEVSLP pad reset config to PLT_RSTAamir Bohra
BUG=b:133000685 Change-Id: Ia12174e3254153dbca55070f5daf84fd8aac51d0 Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35307 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: V Sowmya <v.sowmya@intel.com>
2019-09-11mb/google/hatch: Create dratini variantWisley Chen
Create dratini variant BUG=b:140610519 TEST=emerge-hatch coreboot, and boot into chromeos on proto board Change-Id: Ied1240d1be831568e4ab4695b893c3f48821f68b Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35285 Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-10mb/google/hatch/variants/helios: Modify FPU power on sequenceFrank_Chu
pull in the FPU VDDIO turn on to fix the power leakage problem on FPU VDDIO and FPU CS during power on sequence. BUG=b:138638571 BRANCH=none TEST=emerge-hatch coreboot chromeos-bootimage Signed-off-by: Frank_Chu <frank_chu@pegatron.corp-partner.google.com> Change-Id: I3f6bf3676922e987c2e282b697a2333e2d90289e Reviewed-on: https://review.coreboot.org/c/coreboot/+/34858 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2019-09-09mb/google/hatch: Distinguish SKU1 and 2 for eMMC and SSD respectivelyPeichao Wang
1. SKU1 for eMMC 2. SKU2 for SSD BUG=b:140008849, b:140573677 TEST=Verify SSD is disabled when SKU ID = 2/4/21/22 Signed-off-by: Peichao Wang <peichao.wang@bitland.corp-partner.google.com> Change-Id: I827e6f1420801d43e0eb4708b8b8ad1692ef7e9f Reviewed-on: https://review.coreboot.org/c/coreboot/+/35204 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Marco Chen <marcochen@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-06mb/google/hatch/variants/helios: Update DPTF parameters and TDP PL1/PL2Frank_Chu
Applying first tuned DPTF parameters and TDP PL1/PL2 values for helios. BUG=b:138752455 BRANCH=none TEST=emerge-hatch coreboot chromeos-bootimage Signed-off-by: Frank_Chu <frank_chu@pegatron.corp-partner.google.com> Change-Id: Ic7a96c33ce710c32b57e2ad8066830ff83398c57 Reviewed-on: https://review.coreboot.org/c/coreboot/+/34743 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2019-09-04mb/google/hatch/var/kindred: Update DPTF parameters and TDP PL1/PL2David Wu
Add TEMP_SENSOR_3 to DPTF, Update DPTF parameters and TDP PL1/PL2 values Cq-Depend: chromium:1751304 BUG=b:140127035 TEST=FW_NAME=kindred emerge-hatch coreboot chromeos-ec chromeos-bootimage Change-Id: I1817e277f4641db6bedc8b640b1dc5d57502d5dd Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35131 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2019-09-03mb/google/hatch/var/kindred: Update DRAM IDs for 8G and 16G 3200David Wu
Update DRAM IDs to support 8G and 16G 3200 spds BUG=b:132920013 b:131132486 TEST=FW_NAME=kindred emerge-hatch coreboot chromeos-bootimage Change-Id: I8e55b5e24ee2cefe90472a331e829b073bf0f92a Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35205 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2019-09-02mb/google/hatch/var/helios: Increase touchscreen reset delay to 120msPhilip Chen
As per GT7375P programming guide rev0.4, we want to enforce a delay of 120ms after the reset is completed, before HID_I2C starts. BUG=b:140276418 Signed-off-by: Philip Chen <philipchen@google.com> Change-Id: Id69a9db996bcd9001ef850c50898fbd55327b4df Reviewed-on: https://review.coreboot.org/c/coreboot/+/35158 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2019-08-30mb/google/hatch: Add settings for noise mitgationDtrain Hsu
Enable acoustic noise mitgation for hatch platform, the slow slew rates are fast time dived by 8 and disable Fast PKG C State Ramp(IA, GT, SA). BUG=b:131779678 TEST=waveform test and reduce the noise level. Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Change-Id: I49e834825b3f1e5bf02f9523d7caa93b544c9d17 Reviewed-on: https://review.coreboot.org/c/coreboot/+/35005 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2019-08-30mb/google/hatch: Add 16G 3200 generic SPD fileShelley Chen
BUG=b:139792883 BRANCH=None TEST=None Change-Id: I22974b015a40fb7ae592e182cf5da83a8252c031 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35138 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2019-08-28mb/google/hatch/variants: Increase touchscreen reset delay to 120msSumeet Pawnikar
During boot sequence sometime touchscreen reset keeps failing. Also, kernel dmesg shows "dmesg:i2c_hid i2c-GDIX0000:00: failed to reset device" message. This adds around 4 more seconds to the boot sequence. Setting the appropriate delay of 120ms between enable and reset for Goodix Touchscreen helps to synchronize and address this failure. This value is 120 ms as per Goodix Spec. BUG=b:138413748 BRANCH=None TEST=Built and tested on Hatch system Change-Id: I15005c568f285ec7bad9a0bec4498e2fdd20782b Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34626 Reviewed-by: V Sowmya <v.sowmya@intel.com> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-28mb/google/hatch: Enable Override DLLs for KindredJamie Chen
Enable SOC_INTEL_COMMON_MMC_OVERRIDE for Kindred BUG=b:136784418 BRANCH=none TEST=Boot to OS 100 times on Kindred proto 1 board. Change-Id: I390d237b9119ae42f4b0bb802bf9857552af78bf Signed-off-by: Jamie Chen <jamie.chen@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35094 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-08-28mb/google/hatch: Override DLL values for KindredJamie Chen
New emmc DLL values for Kindred BUG=b:136784418 BRANCH=none TEST=Boot to OS 100 times on Kindred proto 1 board. Change-Id: I52acb445c47fcdb9b60512dd501d810b1ae4dc10 Signed-off-by: Jamie Chen <jamie.chen@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35041 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-23mb/google/hatch/var/kindred:: Add enable signal for touch screenPhilip Chen
In the next board version, we will use GPP_D9 as enable control for touch screen. BUG=b:137133946 TEST=build Change-Id: I213d0878bfca1ce4059ec0393f59d8e79e1b274c Signed-off-by: Philip Chen <philipchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35039 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2019-08-23mb/google/hatch/variants/kindred: Remove unused devicesPhilip Chen
sx9310 and FPMCU are not used in Kindred. BUG=none TEST=build Change-Id: Ied09d4bdb899d991131a75d7c848ff8637022f53 Signed-off-by: Philip Chen <philipchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35038 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2019-08-21mb/google/kohaku: Correct DPTF temp sensor IDsSeunghwan Kim
This change corrects DPTF temperature sensor IDs BUG=none BRANCH=none TEST=none Change-Id: I25c76b0e938b2568da1833a4a5685ed36c00275e Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34985 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-08-20mb/google/hatch: Skip SD card controller WP pin configuration from FSPAamir Bohra
BUG=b:123907904 TEST=SD WP GPIO PAD retains coreboot configuration and FSP ScsSdCardWpPinEnabled UPD is set to 0. Change-Id: I30367cda09cc8c88abb649f70b4587889083f9af Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34901 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-20mb/google/kohaku: Use level trigger for touchscreen interruptSeunghwan Kim
Level trigger is recommended setting for touchscreen interrupt of kohaku, so we would change it as the recommedation. BUG=b:139179200 BRANCH=none TEST=Verified touchscreen works on kohaku Change-Id: Ibbcdbe3ab555d014048f66ff527e539c5b566187 Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34898 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-08-16mb/google/hatch: Create Akemi variantPeichao Wang
This is based on the hatch variant BUG=b:138879565 TEST=FW_NAME="akemi" emerge-hatch coreboot depthcharge intel-cmlfsp chromeos-bootimage look for image-akemi.*.bin generated under the /build/hatch/firmware/ Change-Id: I1a868839e2c598f8052d37c99713bc58b21e887c Signed-off-by: Peichao Wang <peichao.wang@bitland.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33824 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-08-15mb/google/hatch/var/kindred: Configure GPIOs for eMMC SKUsDavid Wu
Configure GPIOs for eMMC SKUs BUG=b:132918661 TEST=Verify SSD is disabled when SKU ID = 2/4/21/22 Change-Id: I9f678a40555dbc841487811cc1f680b211a51a89 Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34795 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2019-08-15mb/google/hatch/var/kindred: Disable SATA controller for eMMC SKUsDavid Wu
Disable SATA controller and SATA port 1 for eMMC SKUs BUG=b:132918661 TEST=Verify SSD is disabled when SKU ID = 2/4/21/22 Change-Id: I6d95ff94b079a564f74c19739370101899843f00 Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34789 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-15mb/google/hatch/var/kindred: Configure GPIOs for SSD SKUsDavid Wu
Configure GPIOs for SSD SKUs BUG=b:132918661 TEST=Verify eMMC is disabled when SKU ID = 1/3/23/24 Change-Id: Ief48a2fd2fa078aa5d89aec01f99af75510334b2 Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34851 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-15mb/google/hatch/var/kindred: Disable eMMC for new SKU ID 23 and 24David Wu
1. Disable eMMC controller for new SKU ID 23 and 24 2. Disable HS400 mode BUG=b:132918661 TEST=Verify eMMC is disabled when SKU ID = 1/3/23/24 Change-Id: I0d893f0f7339e7b1a1e6b56d1598c0a361c8d604 Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34788 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2019-08-15mainboard/google: Fix indirect includesKyösti Mälkki
Change-Id: Ie79702efab519b16cff45ccad61b95e7d8c2fbac Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34854 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-13mb/google/hatch/var/kohaku: Change Atmel touchscreen HID to PRP0001Furquan Shaikh
This change updates the Atmel touchscreen ACPI node to use PRP0001 as _HID to allow OF-style compatible string matching for enumeration. Reason for this change: Atmel touchscreen driver in Linux kernel looks for "compatible" property to decide if it is okay to attach to the device. This check seems to be a protection against old firmware in the field that do not have the right properties. BUG=b:129162037 TEST=Verified that touchscreen works on Kohaku. Change-Id: I6d027f8533494e903efd1da8da1fa273a97fe9b2 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34814 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2019-08-13mb/google/hatch: Kohaku: Enable DMIC1 in device treeMac Chiang
The default is DMIC0 on, but Kohaku is also using DMIC1 BUG=b:133282247 BRANCH=None TEST=arecord -D hw:0,1 -r 48000 -c 4 -f s32 4dmic.wav make sure 4 channels recording work Signed-off-by: Mac Chiang <mac.chiang@intel.com> Change-Id: I2dd573e1634516bcf9876bedb92b7d9148bb0e6a Reviewed-on: https://review.coreboot.org/c/coreboot/+/34692 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-11kohaku: add TEMP_SENSOR_3 and TEMP_SENSOR_4 to DPTFPaul Fagerburg
The Kohaku V24 schematic adds two additional temperature sensors to the EC. Add these to the DPTF tables. Cq-Depend: chromium:1742914 BRANCH=none BUG=b:138578073 TEST=Rebuild EC and BIOS, look for new thermal sensors in kernel. 1. Build EC ``cd ~/trunk/src/platform/ec`` ``make -j BOARD=kohaku`` 2. Program EC ``./util/flash_ec --board=kohaku`` 3. Reboot device 4. Rebuild BIOS ``cd ~/trunk/src/third_party/coreboot`` ``FEATURES="noclean" FW_NAME=kohaku emerge-hatch chromeos-ec depthcharge vboot_reference libpayload coreboot-private-files intel-cmlfsp coreboot-private-files-hatch coreboot chromeos-bootimage`` 5. Use flashrom to program the BIOS 6. Reboot device 7. Log into the root console (ctrl-alt-F2 or servo) 8. Example thermal sensor information ``grep . /sys/class/thermal/t*/type`` Look for "TSR0" through "TSR3" in the output. Change-Id: Ib8f38beae6392855927ce1249c229d7a114c72b2 Signed-off-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34765 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-11mb/google/hatch: Fix Kohaku pen GPIO configurationTim Wawrzynczak
Oops, I missed this in the last CL. The pin needs to be configured as owned by GPIO, so that the kernel driver can bind it with an IRQ. BUG=b:139165490 TEST=Ensure kernel nastygram about inability to claim the IRQ is gone Change-Id: I26c08d75d8b4e3b834db6e90868239899605fa5b Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34815 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-08-09mb/google/hatch: Refactor override_early_gpio_tableTim Wawrzynczak
There was the potential for misuse of the override early GPIO table, because if the override early GPIO table did not have a corresponding entry in the base table, it would not get overridden, and there was no way to know except manual inspection (this has already happened here), so now all hatch mainboards are required to explicitly list out all of their required early GPIOs. TEST=booted several hatch boards, verified that they can communicate with TPM and successfully train memory Change-Id: I0552b08a284fd6fb41a09fef431a0d006b0cf0bd Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34782 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2019-08-07mb/google/hatch: Kohaku: Re-setup dual-routing of EMR_GARAGE_DETTim Wawrzynczak
The pinctrl driver in the linux kernel automatically turns off SCI routing for all GPIOs exported via ACPI, so this patch sets up dual-routing of the EMR_GARAGE_DET signal so that one can be used for IRQs and one for the SCI wake. Change-Id: Iadeb4502c5a98a72ba651bdcad626609656c196f Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34780 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Shelley Chen <shchen@google.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-07mb/google/hatch: Kohaku: Add touchscreen controller to device treeTim Wawrzynczak
The touchscreen controller was never added to the device tree, and the next board rev will have this IC connected. Set it up in the device tree with conservative power resource timings from the datasheet. BUG=b:138869702 BRANCH=none TEST=compiles; current board rev does not have touch IC Change-Id: I759fb32f31c8eee0e6bd664c6a82308354ef5d08 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34763 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-08-07mb/google/kohaku: Enable stylus pen deviceSeunghwan Kim
Enabling stylus pen device and pen_eject event. - Adding enable_gpio for power sequencing - Configuring GPP_H4 and GPP_H5 as native function - Adding PENH device node for pen ejection event BUG=b:137326841 BRANCH=none TEST=Verified pen input operation and pen_eject event (pop-up and wake from s0ix on pen ejection) Change-Id: Ic252a1f90c0fc6cb9b1e426d75a8b503824681f3 Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com> Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34581 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2019-08-05mb/google/helios: Set SPKR_PA_EN PIN high for boot beepSubrata Banik
This patch makes SPKR_PA_EN PIN output and high for boot beep to work in pre-os environment. BUG=b:135104721 BRANCH=NONE TEST=Boot Beep is working with required ALC1011 depthcharge code changes. Change-Id: I012462f93e9e2bcafe5f18ce7d04e3fcd1db9ffa Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34705 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Usha P <usha.p@intel.com> Reviewed-by: V Sowmya <v.sowmya@intel.com> Reviewed-by: Meera Ravindranath <meera.ravindranath@intel.corp-partner.google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Sathya Prakash M R <sathya.prakash.m.r@intel.com>
2019-08-03mb/google/hatch/variants/helios: Adjust all I2C CLK and I2C0 SDA hold timeFrank_Chu
After adjustment Touch Pad CLK: 383.4 KHz Touch Screen CLK: 381.6 KHz Audio codec CLK: 386.0 KHz TouchPad SDA hold time: 0.325ns BUG=b:137722634 BRANCH=none TEST=emerge-hatch coreboot chromeos-bootimage Signed-off-by: Frank_Chu <frank_chu@pegatron.corp-partner.google.com> Change-Id: I27dec2f3e00eb6618cc429aff3dae7a5d937d638 Reviewed-on: https://review.coreboot.org/c/coreboot/+/34647 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2019-08-03mb/google/hatch: Enable PmTimerDisabled config to reduce S0ix power usageSubrata Banik
BRANCH=none BUG=b:138152075 TEST=Build for cometlake board with the PmTimerDisabled policy in devicetree set to 1. With PmTimerDisabled = 0 >> iotools mmio_read8 0xfe0018fc 0x00 With PmTimerDisabled = 1 >> iotools mmio_read8 0xfe0018fc 0x02 Bit 1: ACPI Timer Disable (ACPI_TIM_DIS): This bit determines whether the ACPI Timer is enabled to run. - 0: ACPI Timer is enabled - 1: ACPI Timer is disabled Change-Id: I83f49505a804c99d7978e5d541ea9fe8ead9b88f Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34611 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-by: V Sowmya <v.sowmya@intel.com>
2019-08-02mb/google/hatch: Fine-tune Kohaku I2C CLK frequencyPhilip Chen
Add rise time / fall time to I2C config in device tree to ensure I2C CLK runs accurately at I2C_SPEED_FAST (400 kHz). BUG=b:138258384 BRANCH=none TEST=probe I2C0/I2C2/I2C3 SCL on Kohaku board, verify all of them run at 395-399 kHz. Change-Id: Id98079e717f0db3fdcb88f85e45693925d11d7fd Signed-off-by: Philip Chen <philipchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34559 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-31mb/google/hatch: Initialize SSD GPIOs in bootblockShelley Chen
Moving these to bootblock as we are seeing some instances where devices are rebooting into the recovery broken screen with the 0x5a error (no bootable storage device in system). This needed to be done for KBL platforms and never got transferred to hatch. Please reference https://review.coreboot.org/c/coreboot/+/23647 BUG=b:137681648 BRANCH=None TEST=Run autotest faft_bios and faft_ec suites Change-Id: I8cf09c26d77d890f5d0490709504e9edf485a93f Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34484 Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-31mb/google/kohaku: Update DPTF parameters and TDP PL1/PL2Seunghwan Kim
Applying first tuned DPTF parameters and TDP PL1/PL2 values for kohaku. More fine-tuning will happen later. BUG=b:1704071 BRANCH=none TEST=build Change-Id: I8a87ff88e8e14ada473f9da59c15cdc779cbb108 Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34397 Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-31mb/google/hatch/variants/hatch: Set PCH Thermal Threshold value to 77 deg CSumeet Pawnikar
PMC logic shuts down the PCH thermal sensor when CPU is in a C-state and DTS Temp <= Low Temp Threshold (LTT) in case of Dynamic Thermal Shutdown when S0ix is enabled. BUG=133345634 BRANCH=None TEST=Verified Thermal Device (B0: D20: F2) TSPM offset 0x1c [LTT (8:0)] value is 0xFE on Hatch. Change-Id: Ib20fae04080b28c6105e5a187cc5d7a55b48d709 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33147 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-30mb/google/hatch: Enable chipset_lockdown coreboot config for hatchSubrata Banik
This patch enables lockdown configuration for hatch family (hatch, kindred, helios and kohaku) BUG=b:138200201 Change-Id: Ia6dc90156dc76fde490b25cf833da3cf80f664f2 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34514 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2019-07-30mb/google/hatch: Add option to enable WiFi SAR configsFurquan Shaikh
This change adds a user selectable option to enable all WiFi SAR configs that apply to hatch. BUG=b:138177048 Change-Id: I4b72f90896841e7c556d4a1b8cdad8ca89d01021 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34580 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2019-07-26mb/google/hatch/helios: Update GPIO and device treeTim Wawrzynczak
Based on updated schematics, change polarity of USI_INT, and add the reset and enable GPIOs to the touchscreen ACPI node. The stop GPIO can't be used with the current implementation of _ON, as the way it's wired will cause power sequencing to fail. BUG=b:137133194, b:138240502 BRANCH=none TEST=Compiles, don't have next board rev to test with Change-Id: I1dfb8e649418e4c5e9b897fb4bc11393adc21ea2 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34528 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-26 17:29:22 +0000