coreboot.git - my copy of coreboot

Age	Commit message (Collapse)	Author
2018-12-25	mb/google/hatch: Add SoC and EC asl files in DSDT	Aamir Bohra
	This implementation adds below code: 1. Add SOC ACPI code in dsdt.asl -> platform.asl -> globalnvs.asl -> cpu.asl -> northbridge.asl -> southbridge.asl -> sleepstate.asl 2. Add chromeos.asl in dsdt.asl 3. Add EC ACPI code in dsdt.asl -> superio.asl -> ec.asl 4. Remove config for WAK/PTS ACPI method as chromeec doesn't implement those. BUG=b:120914069 TEST=USE="-intel_mrc -bmpblk" emerge-hatch coreboot Change-Id: Icf1b1d7e34a7e863139c3583903f3b1e2cdc8da6 Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/30282 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2018-12-25	mb/google/hatch: Add EC trigger events and acpi configs	Aamir Bohra
	This implemetation adds EC SCI, SMI, S5/S3 wake trigger events. Also adds the EC specific ACPI configs to enable support for ALS, EC PD device and PS2 keyboard device. BUG=b:120914069 TEST=USE="-intel_mrc -bmpblk" emerge-hatch coreboot Change-Id: I3a86f609c269cb59e546fc7ba4ba032e5ea8341a Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/30281 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-12-23	mb/google/hatch: Enable IGD (Integrated GFX Device)	Maulik V Vaghela
	This patch ensures following 2 features 1. Enable IGD controller in devicetree.cb 2. Pass required FSP UPD to perform internal graphics initialization Change-Id: I607199590d793a70e1e20bb3241fc34467aa829d Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/30364 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2018-12-23	mb/google/hatch: Add memory init setup for hatch	Aamir Bohra
	This implementation adds below support: 1. Add support to read memory strap. 2. Add support to configure below memory parameters -> rcomp resistor configuration -> dqs mapping -> ect and ca vref config 3. Include SPD configuration BUG=b:120914069 BRANCH=None TEST=USE="-intel_mrc -bmplk" emerge-hatch coreboot Change-Id: I9bda08bd0b9f91ebb96b39291e15473492a6bf19 Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/30248 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Shelley Chen <shchen@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-12-22	mb/google/hatch: Enable Elan Trackpad	Shelley Chen
	BUG=b:120914069 BRANCH=None TEST=USE="-intel_mrc" emerge-hatch coreboot Change-Id: I91db5745d1db16ab4b2fbb7f8c415bd7c1eb29e9 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/30227 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2018-12-22	mb/google/hatch: Fixes to initial hatch mainboard checkin	Shelley Chen
	Incorporating some feedback to initial hatch mainboard checking (CL:30169) that came in after the CL merged. Updated the chromeos.fmd with the following, * SI_ALL = 3MB * SI_BIOS = 16MB BUG=b:20914069 BRANCH=None TEST=./util/abuild/abuild -p none -t google/hatch -x -a -v Change-Id: I4e311c68873f10f71314e44d3a714639a06dbee8 Signed-off-by: Shelley Chen <shchen@google.com> Signed-off-by: V Sowmya <v.sowmya@intel.com> Reviewed-on: https://review.coreboot.org/c/30296 Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-12-21	mb/google/hatch: Enable H1 TPM support over SPI interface	Aamir Bohra
	Add code support to enable H1 TPM interfaced to SOC on GSPI0. The TPM interrupt is mapped to GPP_C21. BUG=b:120914069 TEST=USE="-intel_mrc -bmpblk" emerge-hatch coreboot Change-Id: Ib63a0b473f632d91745102ebd01993e8d65b9552 Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/30210 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-12-21	mb/google/hatch: Clean up gpio definitions in hatch variant	Aamir Bohra
	This implementation cleans up gpio configuration functions and limit definition to baseboard only for now, until variant specfic overides are needed. BUG=b:120914069 TEST=USE="-intel_mrc -bmpblk" emerge-hatch coreboot Change-Id: I563f6b97812b32d6e3d99e3df512dc112da78aea Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/30291 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-12-13	mb/google/hatch: Creating skeleton directories and files	Shelley Chen
	Creating skeleton files and directories in mainboard for the new Hatch board. This is to facilitate development for different parties involved. BUG=None BRANCH=None TEST=./util/abuild/abuild -p none -t google/hatch -x -a Change-Id: I5fc60c178f83034abe5d846d0f4169072b66f448 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/30169 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>