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2019-09-16mb/google/kohaku: Update USB port settingsSeunghwan Kim
This change overrides USB port settings for kohaku. Some port settings are same with baseboard, but I'd like to describe all settings here to be aware of current setting and usage of USB ports on kohaku. BUG=none BRANCH=none TEST=built and measured SI of USB ports internally Change-Id: I5ac05485d1cd94416e5a0aecf7fa6769bd7c9e84 Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35236 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-09-13mb/google/hatch: Merge emmc_sku_gpio_table and gpio_table to one tablePeichao Wang
BUG=b:140008849, b:140573677 TEST=verify eMMC SKU and SSD SKU will bring up normally. Signed-off-by: Peichao Wang <peichao.wang@bitland.corp-partner.google.com> Change-Id: I0c0adf569cc92e8b44ab72379420f2b190fa31f5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/35344 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marco Chen <marcochen@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Justin TerAvest <teravest@chromium.org>
2019-09-13mb/google/hatch/var: Increase Goodix touchscreen reset delay to 500msPhilip Chen
Even though GT7375P programming guide rev0.4 only requires a reset delay of 120ms, in practice, we have to increase the reset delay to 500ms, or Goodix FW update would fail. This is a workaround. In the long run, we hope Goodix can fix the power sequence in touch firmware. BUG=b:138795891, b:138796844 TEST=boot helios board and verify Goodix FW update succeeded Signed-off-by: Philip Chen <philipchen@google.com> Change-Id: Ic0049bf240de0a1c7f1b1f39bf155d48bb76fb86 Reviewed-on: https://review.coreboot.org/c/coreboot/+/35350 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-12mb/google/hatch: Configure SATA DEVSLP pad reset config to PLT_RSTAamir Bohra
BUG=b:133000685 Change-Id: Ia12174e3254153dbca55070f5daf84fd8aac51d0 Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35307 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: V Sowmya <v.sowmya@intel.com>
2019-09-11mb/google/hatch: Create dratini variantWisley Chen
Create dratini variant BUG=b:140610519 TEST=emerge-hatch coreboot, and boot into chromeos on proto board Change-Id: Ied1240d1be831568e4ab4695b893c3f48821f68b Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35285 Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-10mb/google/hatch/variants/helios: Modify FPU power on sequenceFrank_Chu
pull in the FPU VDDIO turn on to fix the power leakage problem on FPU VDDIO and FPU CS during power on sequence. BUG=b:138638571 BRANCH=none TEST=emerge-hatch coreboot chromeos-bootimage Signed-off-by: Frank_Chu <frank_chu@pegatron.corp-partner.google.com> Change-Id: I3f6bf3676922e987c2e282b697a2333e2d90289e Reviewed-on: https://review.coreboot.org/c/coreboot/+/34858 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2019-09-09mb/google/hatch: Distinguish SKU1 and 2 for eMMC and SSD respectivelyPeichao Wang
1. SKU1 for eMMC 2. SKU2 for SSD BUG=b:140008849, b:140573677 TEST=Verify SSD is disabled when SKU ID = 2/4/21/22 Signed-off-by: Peichao Wang <peichao.wang@bitland.corp-partner.google.com> Change-Id: I827e6f1420801d43e0eb4708b8b8ad1692ef7e9f Reviewed-on: https://review.coreboot.org/c/coreboot/+/35204 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Marco Chen <marcochen@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-06mb/google/hatch/variants/helios: Update DPTF parameters and TDP PL1/PL2Frank_Chu
Applying first tuned DPTF parameters and TDP PL1/PL2 values for helios. BUG=b:138752455 BRANCH=none TEST=emerge-hatch coreboot chromeos-bootimage Signed-off-by: Frank_Chu <frank_chu@pegatron.corp-partner.google.com> Change-Id: Ic7a96c33ce710c32b57e2ad8066830ff83398c57 Reviewed-on: https://review.coreboot.org/c/coreboot/+/34743 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2019-09-04mb/google/hatch/var/kindred: Update DPTF parameters and TDP PL1/PL2David Wu
Add TEMP_SENSOR_3 to DPTF, Update DPTF parameters and TDP PL1/PL2 values Cq-Depend: chromium:1751304 BUG=b:140127035 TEST=FW_NAME=kindred emerge-hatch coreboot chromeos-ec chromeos-bootimage Change-Id: I1817e277f4641db6bedc8b640b1dc5d57502d5dd Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35131 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2019-09-03mb/google/hatch/var/kindred: Update DRAM IDs for 8G and 16G 3200David Wu
Update DRAM IDs to support 8G and 16G 3200 spds BUG=b:132920013 b:131132486 TEST=FW_NAME=kindred emerge-hatch coreboot chromeos-bootimage Change-Id: I8e55b5e24ee2cefe90472a331e829b073bf0f92a Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35205 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2019-09-02mb/google/hatch/var/helios: Increase touchscreen reset delay to 120msPhilip Chen
As per GT7375P programming guide rev0.4, we want to enforce a delay of 120ms after the reset is completed, before HID_I2C starts. BUG=b:140276418 Signed-off-by: Philip Chen <philipchen@google.com> Change-Id: Id69a9db996bcd9001ef850c50898fbd55327b4df Reviewed-on: https://review.coreboot.org/c/coreboot/+/35158 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2019-08-30mb/google/hatch: Add settings for noise mitgationDtrain Hsu
Enable acoustic noise mitgation for hatch platform, the slow slew rates are fast time dived by 8 and disable Fast PKG C State Ramp(IA, GT, SA). BUG=b:131779678 TEST=waveform test and reduce the noise level. Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Change-Id: I49e834825b3f1e5bf02f9523d7caa93b544c9d17 Reviewed-on: https://review.coreboot.org/c/coreboot/+/35005 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2019-08-30mb/google/hatch: Add 16G 3200 generic SPD fileShelley Chen
BUG=b:139792883 BRANCH=None TEST=None Change-Id: I22974b015a40fb7ae592e182cf5da83a8252c031 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35138 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2019-08-28mb/google/hatch/variants: Increase touchscreen reset delay to 120msSumeet Pawnikar
During boot sequence sometime touchscreen reset keeps failing. Also, kernel dmesg shows "dmesg:i2c_hid i2c-GDIX0000:00: failed to reset device" message. This adds around 4 more seconds to the boot sequence. Setting the appropriate delay of 120ms between enable and reset for Goodix Touchscreen helps to synchronize and address this failure. This value is 120 ms as per Goodix Spec. BUG=b:138413748 BRANCH=None TEST=Built and tested on Hatch system Change-Id: I15005c568f285ec7bad9a0bec4498e2fdd20782b Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34626 Reviewed-by: V Sowmya <v.sowmya@intel.com> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-28mb/google/hatch: Enable Override DLLs for KindredJamie Chen
Enable SOC_INTEL_COMMON_MMC_OVERRIDE for Kindred BUG=b:136784418 BRANCH=none TEST=Boot to OS 100 times on Kindred proto 1 board. Change-Id: I390d237b9119ae42f4b0bb802bf9857552af78bf Signed-off-by: Jamie Chen <jamie.chen@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35094 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-08-28mb/google/hatch: Override DLL values for KindredJamie Chen
New emmc DLL values for Kindred BUG=b:136784418 BRANCH=none TEST=Boot to OS 100 times on Kindred proto 1 board. Change-Id: I52acb445c47fcdb9b60512dd501d810b1ae4dc10 Signed-off-by: Jamie Chen <jamie.chen@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35041 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-23mb/google/hatch/var/kindred:: Add enable signal for touch screenPhilip Chen
In the next board version, we will use GPP_D9 as enable control for touch screen. BUG=b:137133946 TEST=build Change-Id: I213d0878bfca1ce4059ec0393f59d8e79e1b274c Signed-off-by: Philip Chen <philipchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35039 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2019-08-23mb/google/hatch/variants/kindred: Remove unused devicesPhilip Chen
sx9310 and FPMCU are not used in Kindred. BUG=none TEST=build Change-Id: Ied09d4bdb899d991131a75d7c848ff8637022f53 Signed-off-by: Philip Chen <philipchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35038 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2019-08-21mb/google/kohaku: Correct DPTF temp sensor IDsSeunghwan Kim
This change corrects DPTF temperature sensor IDs BUG=none BRANCH=none TEST=none Change-Id: I25c76b0e938b2568da1833a4a5685ed36c00275e Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34985 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-08-20mb/google/hatch: Skip SD card controller WP pin configuration from FSPAamir Bohra
BUG=b:123907904 TEST=SD WP GPIO PAD retains coreboot configuration and FSP ScsSdCardWpPinEnabled UPD is set to 0. Change-Id: I30367cda09cc8c88abb649f70b4587889083f9af Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34901 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-20mb/google/kohaku: Use level trigger for touchscreen interruptSeunghwan Kim
Level trigger is recommended setting for touchscreen interrupt of kohaku, so we would change it as the recommedation. BUG=b:139179200 BRANCH=none TEST=Verified touchscreen works on kohaku Change-Id: Ibbcdbe3ab555d014048f66ff527e539c5b566187 Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34898 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-08-16mb/google/hatch: Create Akemi variantPeichao Wang
This is based on the hatch variant BUG=b:138879565 TEST=FW_NAME="akemi" emerge-hatch coreboot depthcharge intel-cmlfsp chromeos-bootimage look for image-akemi.*.bin generated under the /build/hatch/firmware/ Change-Id: I1a868839e2c598f8052d37c99713bc58b21e887c Signed-off-by: Peichao Wang <peichao.wang@bitland.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33824 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-08-15mb/google/hatch/var/kindred: Configure GPIOs for eMMC SKUsDavid Wu
Configure GPIOs for eMMC SKUs BUG=b:132918661 TEST=Verify SSD is disabled when SKU ID = 2/4/21/22 Change-Id: I9f678a40555dbc841487811cc1f680b211a51a89 Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34795 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2019-08-15mb/google/hatch/var/kindred: Disable SATA controller for eMMC SKUsDavid Wu
Disable SATA controller and SATA port 1 for eMMC SKUs BUG=b:132918661 TEST=Verify SSD is disabled when SKU ID = 2/4/21/22 Change-Id: I6d95ff94b079a564f74c19739370101899843f00 Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34789 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-15mb/google/hatch/var/kindred: Configure GPIOs for SSD SKUsDavid Wu
Configure GPIOs for SSD SKUs BUG=b:132918661 TEST=Verify eMMC is disabled when SKU ID = 1/3/23/24 Change-Id: Ief48a2fd2fa078aa5d89aec01f99af75510334b2 Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34851 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-15mb/google/hatch/var/kindred: Disable eMMC for new SKU ID 23 and 24David Wu
1. Disable eMMC controller for new SKU ID 23 and 24 2. Disable HS400 mode BUG=b:132918661 TEST=Verify eMMC is disabled when SKU ID = 1/3/23/24 Change-Id: I0d893f0f7339e7b1a1e6b56d1598c0a361c8d604 Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34788 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2019-08-15mainboard/google: Fix indirect includesKyösti Mälkki
Change-Id: Ie79702efab519b16cff45ccad61b95e7d8c2fbac Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34854 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-13mb/google/hatch/var/kohaku: Change Atmel touchscreen HID to PRP0001Furquan Shaikh
This change updates the Atmel touchscreen ACPI node to use PRP0001 as _HID to allow OF-style compatible string matching for enumeration. Reason for this change: Atmel touchscreen driver in Linux kernel looks for "compatible" property to decide if it is okay to attach to the device. This check seems to be a protection against old firmware in the field that do not have the right properties. BUG=b:129162037 TEST=Verified that touchscreen works on Kohaku. Change-Id: I6d027f8533494e903efd1da8da1fa273a97fe9b2 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34814 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2019-08-13mb/google/hatch: Kohaku: Enable DMIC1 in device treeMac Chiang
The default is DMIC0 on, but Kohaku is also using DMIC1 BUG=b:133282247 BRANCH=None TEST=arecord -D hw:0,1 -r 48000 -c 4 -f s32 4dmic.wav make sure 4 channels recording work Signed-off-by: Mac Chiang <mac.chiang@intel.com> Change-Id: I2dd573e1634516bcf9876bedb92b7d9148bb0e6a Reviewed-on: https://review.coreboot.org/c/coreboot/+/34692 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-11kohaku: add TEMP_SENSOR_3 and TEMP_SENSOR_4 to DPTFPaul Fagerburg
The Kohaku V24 schematic adds two additional temperature sensors to the EC. Add these to the DPTF tables. Cq-Depend: chromium:1742914 BRANCH=none BUG=b:138578073 TEST=Rebuild EC and BIOS, look for new thermal sensors in kernel. 1. Build EC ``cd ~/trunk/src/platform/ec`` ``make -j BOARD=kohaku`` 2. Program EC ``./util/flash_ec --board=kohaku`` 3. Reboot device 4. Rebuild BIOS ``cd ~/trunk/src/third_party/coreboot`` ``FEATURES="noclean" FW_NAME=kohaku emerge-hatch chromeos-ec depthcharge vboot_reference libpayload coreboot-private-files intel-cmlfsp coreboot-private-files-hatch coreboot chromeos-bootimage`` 5. Use flashrom to program the BIOS 6. Reboot device 7. Log into the root console (ctrl-alt-F2 or servo) 8. Example thermal sensor information ``grep . /sys/class/thermal/t*/type`` Look for "TSR0" through "TSR3" in the output. Change-Id: Ib8f38beae6392855927ce1249c229d7a114c72b2 Signed-off-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34765 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-11mb/google/hatch: Fix Kohaku pen GPIO configurationTim Wawrzynczak
Oops, I missed this in the last CL. The pin needs to be configured as owned by GPIO, so that the kernel driver can bind it with an IRQ. BUG=b:139165490 TEST=Ensure kernel nastygram about inability to claim the IRQ is gone Change-Id: I26c08d75d8b4e3b834db6e90868239899605fa5b Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34815 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-08-09mb/google/hatch: Refactor override_early_gpio_tableTim Wawrzynczak
There was the potential for misuse of the override early GPIO table, because if the override early GPIO table did not have a corresponding entry in the base table, it would not get overridden, and there was no way to know except manual inspection (this has already happened here), so now all hatch mainboards are required to explicitly list out all of their required early GPIOs. TEST=booted several hatch boards, verified that they can communicate with TPM and successfully train memory Change-Id: I0552b08a284fd6fb41a09fef431a0d006b0cf0bd Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34782 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2019-08-07mb/google/hatch: Kohaku: Re-setup dual-routing of EMR_GARAGE_DETTim Wawrzynczak
The pinctrl driver in the linux kernel automatically turns off SCI routing for all GPIOs exported via ACPI, so this patch sets up dual-routing of the EMR_GARAGE_DET signal so that one can be used for IRQs and one for the SCI wake. Change-Id: Iadeb4502c5a98a72ba651bdcad626609656c196f Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34780 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Shelley Chen <shchen@google.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-07mb/google/hatch: Kohaku: Add touchscreen controller to device treeTim Wawrzynczak
The touchscreen controller was never added to the device tree, and the next board rev will have this IC connected. Set it up in the device tree with conservative power resource timings from the datasheet. BUG=b:138869702 BRANCH=none TEST=compiles; current board rev does not have touch IC Change-Id: I759fb32f31c8eee0e6bd664c6a82308354ef5d08 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34763 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-08-07mb/google/kohaku: Enable stylus pen deviceSeunghwan Kim
Enabling stylus pen device and pen_eject event. - Adding enable_gpio for power sequencing - Configuring GPP_H4 and GPP_H5 as native function - Adding PENH device node for pen ejection event BUG=b:137326841 BRANCH=none TEST=Verified pen input operation and pen_eject event (pop-up and wake from s0ix on pen ejection) Change-Id: Ic252a1f90c0fc6cb9b1e426d75a8b503824681f3 Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com> Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34581 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2019-08-05mb/google/helios: Set SPKR_PA_EN PIN high for boot beepSubrata Banik
This patch makes SPKR_PA_EN PIN output and high for boot beep to work in pre-os environment. BUG=b:135104721 BRANCH=NONE TEST=Boot Beep is working with required ALC1011 depthcharge code changes. Change-Id: I012462f93e9e2bcafe5f18ce7d04e3fcd1db9ffa Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34705 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Usha P <usha.p@intel.com> Reviewed-by: V Sowmya <v.sowmya@intel.com> Reviewed-by: Meera Ravindranath <meera.ravindranath@intel.corp-partner.google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Sathya Prakash M R <sathya.prakash.m.r@intel.com>
2019-08-03mb/google/hatch/variants/helios: Adjust all I2C CLK and I2C0 SDA hold timeFrank_Chu
After adjustment Touch Pad CLK: 383.4 KHz Touch Screen CLK: 381.6 KHz Audio codec CLK: 386.0 KHz TouchPad SDA hold time: 0.325ns BUG=b:137722634 BRANCH=none TEST=emerge-hatch coreboot chromeos-bootimage Signed-off-by: Frank_Chu <frank_chu@pegatron.corp-partner.google.com> Change-Id: I27dec2f3e00eb6618cc429aff3dae7a5d937d638 Reviewed-on: https://review.coreboot.org/c/coreboot/+/34647 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2019-08-03mb/google/hatch: Enable PmTimerDisabled config to reduce S0ix power usageSubrata Banik
BRANCH=none BUG=b:138152075 TEST=Build for cometlake board with the PmTimerDisabled policy in devicetree set to 1. With PmTimerDisabled = 0 >> iotools mmio_read8 0xfe0018fc 0x00 With PmTimerDisabled = 1 >> iotools mmio_read8 0xfe0018fc 0x02 Bit 1: ACPI Timer Disable (ACPI_TIM_DIS): This bit determines whether the ACPI Timer is enabled to run. - 0: ACPI Timer is enabled - 1: ACPI Timer is disabled Change-Id: I83f49505a804c99d7978e5d541ea9fe8ead9b88f Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34611 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-by: V Sowmya <v.sowmya@intel.com>
2019-08-02mb/google/hatch: Fine-tune Kohaku I2C CLK frequencyPhilip Chen
Add rise time / fall time to I2C config in device tree to ensure I2C CLK runs accurately at I2C_SPEED_FAST (400 kHz). BUG=b:138258384 BRANCH=none TEST=probe I2C0/I2C2/I2C3 SCL on Kohaku board, verify all of them run at 395-399 kHz. Change-Id: Id98079e717f0db3fdcb88f85e45693925d11d7fd Signed-off-by: Philip Chen <philipchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34559 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-31mb/google/hatch: Initialize SSD GPIOs in bootblockShelley Chen
Moving these to bootblock as we are seeing some instances where devices are rebooting into the recovery broken screen with the 0x5a error (no bootable storage device in system). This needed to be done for KBL platforms and never got transferred to hatch. Please reference https://review.coreboot.org/c/coreboot/+/23647 BUG=b:137681648 BRANCH=None TEST=Run autotest faft_bios and faft_ec suites Change-Id: I8cf09c26d77d890f5d0490709504e9edf485a93f Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34484 Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-31mb/google/kohaku: Update DPTF parameters and TDP PL1/PL2Seunghwan Kim
Applying first tuned DPTF parameters and TDP PL1/PL2 values for kohaku. More fine-tuning will happen later. BUG=b:1704071 BRANCH=none TEST=build Change-Id: I8a87ff88e8e14ada473f9da59c15cdc779cbb108 Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34397 Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-31mb/google/hatch/variants/hatch: Set PCH Thermal Threshold value to 77 deg CSumeet Pawnikar
PMC logic shuts down the PCH thermal sensor when CPU is in a C-state and DTS Temp <= Low Temp Threshold (LTT) in case of Dynamic Thermal Shutdown when S0ix is enabled. BUG=133345634 BRANCH=None TEST=Verified Thermal Device (B0: D20: F2) TSPM offset 0x1c [LTT (8:0)] value is 0xFE on Hatch. Change-Id: Ib20fae04080b28c6105e5a187cc5d7a55b48d709 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33147 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-30mb/google/hatch: Enable chipset_lockdown coreboot config for hatchSubrata Banik
This patch enables lockdown configuration for hatch family (hatch, kindred, helios and kohaku) BUG=b:138200201 Change-Id: Ia6dc90156dc76fde490b25cf833da3cf80f664f2 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34514 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2019-07-30mb/google/hatch: Add option to enable WiFi SAR configsFurquan Shaikh
This change adds a user selectable option to enable all WiFi SAR configs that apply to hatch. BUG=b:138177048 Change-Id: I4b72f90896841e7c556d4a1b8cdad8ca89d01021 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34580 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2019-07-26mb/google/hatch/helios: Update GPIO and device treeTim Wawrzynczak
Based on updated schematics, change polarity of USI_INT, and add the reset and enable GPIOs to the touchscreen ACPI node. The stop GPIO can't be used with the current implementation of _ON, as the way it's wired will cause power sequencing to fail. BUG=b:137133194, b:138240502 BRANCH=none TEST=Compiles, don't have next board rev to test with Change-Id: I1dfb8e649418e4c5e9b897fb4bc11393adc21ea2 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34528 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2019-07-23mb/google/hatch: Add FP MCU to helios device treePhilip Chen
BUG=b:136606255 Change-Id: I8fa29dc96e7a066f6708ede6b7bee2382c7008cb Signed-off-by: Philip Chen <philipchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34465 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-07-21mb/google/hatch: Remove hatch_whlPhilip Chen
Hatch_whl variant is deprecated. BUG=b:137180390 Change-Id: I88fa201398ad5fb70da48d022f1ae86fecafa660 Signed-off-by: Philip Chen <philipchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34432 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-21mb/google/hatch/var/kindred: Implement variant_devtree_update()David Wu
This change provides an implementation of variant_devtree_update() for kindred that disable eMMC controller when SKU ID = 1 or 3 BUG=b:132918661 TEST=Verify eMMC is disabled when SKU ID = 1 or 3 Change-Id: I8ccb4dae54f223881e0ced9e034bf45b994cc6f2 Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34400 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2019-07-21mb/google/hatch: expose get_board_sku() as globalDavid Wu
BUG=None TEST=emerge-hatch coreboot chromeos-bootimage Change-Id: I217e13acd337034554ff055e8bf5011558d1f8bf Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34431 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-07-21mb/google/hatch: Add support for variant_devtree_update()David Wu
This change adds support for variant_devtree_update() that allows variant to update device tree. BUG=None TEST=emerge-hatch coreboot chromeos-bootimage Change-Id: I0e9ad360b6c02c83fe49387ce7bc66d56448ffb9 Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34399 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-07-19mb/google/hatch: Fix SD card is detected as read only issueSubrata Banik
This patch configures GPIO pin GPP_G7 as NF1 with internal pull down. As per schematics SD host controller SD_WP pin is not connected to uSD card connector. Configured gpio pin as NF1 with internal pull down in order to overcome gpio default state in hatch which makes SoC SD_WP pin is enable. BUG=b:137729527 BRANCH=None TEST=Able to write/read data to/from sd card after mounting card device. Change-Id: I0187267670e1dea3e1d5e83d0b29967714d6065e Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34396 Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-19mb/google/helios: Add ALC1011 in device tree to enable speaker ampsSathya Prakash M R
Following changes are done to enable ALC1011 codec on Helios 1. ACL1011 4 devices to I2C4 2. GPIO H13 is set to GPO as per schematics Verified SSDT table and i2cdetect from kernel. Signed-off-by: Naveen Manohar <naveen.m@intel.com> Change-Id: I0d71e3bd2d4493d059a33023c1afe1b630181d4f Signed-off-by: Sathya Prakash M R <sathya.prakash.m.r@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33932 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-07-18mb/google/hatch/var/helios: Implement variant_memory_sku()Furquan Shaikh
This change provides an implementation of variant_memory_sku() for helios that overrides memory ID 3 and 4 to 0 and 1 to workaround the incorrect memory straps in hardware for board id 0 and unknown. BUG=b:133455595 Change-Id: I38fab1f91decac5d0a146e5a6c74e88f677af305 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34252 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2019-07-18mb/google/hatch: Add support for variant_memory_sku()Furquan Shaikh
This change adds support for variant_memory_sku() that allows variant to return memory SKU ID. Current implementation of memory_sku() is renamed to weak implementation of variant_memory_sku(). Functionally this change should be the same as before for all hatch variants. This function will be overriden by helios in a follow-up CL. BUG=b:133455595 Change-Id: I509c263ec08e0060c12ef1ea9fed673f1e3f3a41 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34251 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2019-07-18mb/google/hatch: Add FP MCU to kohaku device treeShelley Chen
BUG=b:137654283 BRANCH=None TEST=Make sure can see FP MCU spidev in dmesg on bootup Change-Id: Iffa13f29e1abdf430e8dc4a0ee1a931a9e69168c Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34371 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-18mb/google/hatch: Disable wireless chargingSubrata Banik
This patch makes VGPIO_3 GPIO PIN output and low independent of cnvi is connected or not. BUG=b:123062346 BRANCH=None TEST=boot up Hatch device and make sure VGPIO_3 gpio pin is driven low. Change-Id: I629b99676f56747de1b244724709e14069250097 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34376 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: V Sowmya <v.sowmya@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-16mb/google/hatch: Disable Bluetooth in bootblock and enable in ramstageShelley Chen
Currently, bluetooth FW is not loaded after a reboot. In order to do this, we have to disable the bluetooth disable gpio (GPP_C14) in bootblock and re-enable it in ramstage. BUG=b:137307516 BRANCH=None TEST=boot up Hatch device and make sure (in dmesg) that proper bluetooth FW in loaded Change-Id: Ic5e447d9de57790f7a100e9e03f36b047c19d8f9 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34354 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-13mb/google/hatch: Fix trackpad configuration in overridetreeFurquan Shaikh
Hatch and variants use GPP_A21 for trackpad IRQ and wake. Fix overridetree.cb to advertise the right IRQ. Change-Id: Ib87c858b89e8726c3bc80f83be0729ef4625268e Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34248 Reviewed-by: Philip Chen <philipchen@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-11mb/google/hatch: Update AC/DC loadline valuesRizwan Qureshi
Update the AC/DC loadline values for all domains. Using the same values as in arcada. BUG=None BRANCH=None TEST=Build and Boot hatch EVT Change-Id: If8ea48794d11dc68e40e6504c0d46a2b273a8ab6 Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33371 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-07-11mb/google/hatch/variants: Fix nonworking touch padFrank_Chu
Correct ELAN Touch pad IRQ GPIO to GPP_A21 BUG=b:135507215 BRANCH=none TEST=emerge-hatch coreboot chromeos-ec chromeos-bootimage Signed-off-by: Frank_Chu <frank_chu@pegatron.corp-partner.google.com> Change-Id: I60816a4652fa39ab2a91034b268efe8f84a13e17 Reviewed-on: https://review.coreboot.org/c/coreboot/+/33954 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-11mb/google/hatch: Enable/disable GPIO clock gatingTim Wawrzynczak
Before the system enters S0ix or S3, each GPIO community will have its dynamic clock gating turned on. Upon return to S0, the dynamic clock gating will be turned back off. BUG=b:130764684 BRANCH=none TEST=Used dut-power to verify that the clock gating is enabled in S0ix and S3. Also used Store(..., Debug) statements in the ASL code to verify it was getting called. Change-Id: I20ff2aac035eaa5912af6c946d837567a4918bbf Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34180 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-07-11mb/google/hatch: Enable LPIT inclusion in DSDTTim Wawrzynczak
Include the lpit.asl file in Hatch's DSDT definition. BUG=b:130764684 BRANCH=none TEST=S3 suspend/resume and S0ix entry/exit work correctly. Ran > 200 iterations of suspend_stress_test and no issues found. Change-Id: If8ebff3db091257e8452869636c0e024f3123e8b Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34175 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2019-07-11mb/google/hatch: Disable GPIO community dynamic clock gatingTim Wawrzynczak
The dynamic clock gating is causing boards to miss interrupts whose pulses are shorter than 4us. Disable it using FSP UPDs. BUG=b:130764684 BRANCH=none TEST=Compiles Change-Id: I8f1ec8f7c31192bce2a761ec99b86638435dc27c Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34176 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Evan Green <evgreen@chromium.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2019-07-11mb/google/hatch: Fix interrupt trigger type for GPP_H0(HP_INT_L)Furquan Shaikh
HP_INT_L(GPP_H0) is configured for GPIO IRQ instead of APIC IRQ since it needs to trigger on both edges. With GPIO IRQ, it is necessary to configure the trigger type in coreboot to match the ACPI configuration. This is because: 1. ACPI configuration is used by intel-pinctrl driver in Linux kernel to re-configure the trigger type for the pad in GPIO DW0 config register. This is done when kernel driver probes and requests irq for its device. 2. On resume from S3, the pad configuration gets reset and coreboot sets the trigger type to LEVEL. However, kernel driver does not probe again. This results in the trigger type being configured incorrectly. This change updates the GPIO configuration for GPP_H0 to set the same trigger type as advertised in ACPI for the kernel. BUG=b:132672011 TEST=Verified that S3 works fine. Verified that interrupt on GPP_H0 works fine on boot as well as after suspend/resume. Change-Id: Ieb44c7403a2f4911b4a8f422053dee8bcfb91d85 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34181 Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Sathya Prakash M R <sathya.prakash.m.r@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-09arch/x86: Avoid HAVE_SMI_HANDLER conditional with smm-classKyösti Mälkki
Build of the entire smm-class is skipped if we have HAVE_SMI_HANDLER=n. Change-Id: I10b4300ddd18b1673c404b45fd9642488ab3186c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34125 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Lance Zhao <lance.zhao@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-08mb/google/hatch: Set GPP_D9 as enable pin for Goodix Touch Screen andFrank Wu
increase reset off delay time Goodix touchscreen cannot work in normal mode because PP3300_TOUCHSCREEN_DX dropped. Configure GPP_D9 as enable pin in the devicetree.cb to fix the power sequence. Increase reset_off_delay time from 1ms to 3ms to met the HW requirement. BUG=b:135287161 BRANCH=None TEST=local build and measure sequence with Goodix touch screen Change-Id: I33140869990aa4715c780b0fa322921e450530ef Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33808 Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-07mb/google/hatch: Update GPIO settings for SD card and SPI1 Chip selectKrishna Prasad Bhat
This patch updates the following GPIO settings. 1. Set Native termination for GPP_G0 - G4 SD card pins. 2. Set GPP_B19 to NF1. BUG=b:123907904 TEST=Verified SD card functionality on hatch. Checked for SD detection, transferred files to and from SD card. Change-Id: I4549ac7377d7f58f51cda0eb96a62604fd31d2f2 Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32176 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2019-07-07mb/google/hatch/var/kindred: Add Raydium touchscreen supportDavid Wu
Add Raydium controller BUG=b:135728282 BRANCH=master TEST= 1. FW_NAME="kindred" emerge-hatch coreboot chromeos-bootimage 2. boot up on kindred DUT to check touchscreen device by evtest /dev/input/event3: Raydium Touchscreen 3. Raydium TS is working Change-Id: Id963300ab0dadcb78786c5a1328c2a4098a48a05 Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33857 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-07mb/google/hatch/var/kindred: Update ELAN GPIO/IRQ and add Synaptics TouchpadDavid Wu
Update ELAN GPIO and IRQ setting and add Synaptics Touchpad BUG=b:132708463 BRANCH=None TEST=Verify ELAN/Synaptics touchpad is working fine. Change-Id: I883ce2e50ca5c6bd2b1ca76cbe24177055cc5d60 Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33660 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-07-07mb/google/hatch/variants/kindred: Enable eMMC supportDavid Wu
Enable eMMC support for kindred. Cq-Depend: chromium:1666982 BUG=b:135464155 BRANCH=none TEST=Boot kindred onboard eMMC. Change-Id: I040af6da30313f8dd59e3ef910b290922e090cdc Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33618 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-02mb/google/hatch: Set trackpad irq and wake to GPP_A21Shelley Chen
Previously, We had to use GPP_A21 for trackpad wake and GPP_D21 for trackpad interrupts due to ITSS not honoring the INVERT config. Now that's fixed, we can configure trackpad wake and interrupts on GPP_A21 only. BUG=b:130436471 BRANCH=None TEST=1. boot a hatch device and make sure we can move the cursor with the trackpad 2. Run powerd_dbus_suspend and wake by clicking on the trackpad and ensure through "mosys eventlog list" that the wake source is the trackpad.\ 3. Run "echo mem > /sys/power/state", wait until device goes into S3, click trackpad to ensure device wakes. Change-Id: I26a99206c42ba442f91ae577b98366fc2fd6c0ca Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33820 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2019-07-02mb/google/hatch: Add INVERT to all IOAPIC padsShelley Chen
Now that ITSS config is fixed, we can set the IOAPIC pad configs correctly. BUG=b:123967687 BRANCH=None TEST=Make sure Hatch is booting and tested out trackpad to make sure can move cursor and wake by clicking on the trackpad after running powerd_dbus_suspend. Change-Id: I0b125996338b6f16e03b7ca184f6337c696a5f64 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33819 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-28mb/google/kohaku: Correct trackpad i2c addressSeunghwan Kim
Correct i2c address of trackpad. It should be 0x20. BUG=None BRANCH=None TEST=Verified trackpad works on pre-evt system Change-Id: I7ded21ce8ff9e907e436777a27edb4273512011d Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33798 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Shelley Chen <shchen@google.com>
2019-06-26mb/google/hatch: Add a GPIO to enable/disable FPMCU powerPhilip Chen
A FPMCU power-control pin (GPP_C11) is added to the latest hatch reference schematic. Even though this is not implemented in hatch rev1 board, the future hatch family boards with FPMCU should all have this control pin. On the old boards without this control pin, GPP_C11 is a floating TP, and thus this patch should be backward-compatible. BUG=b:130307667, b:135216932 TEST=build Signed-off-by: Philip Chen <philipchen@google.com> Change-Id: I6a84eeb6aab562258e749a8a5d09dadfa0e43587 Reviewed-on: https://review.coreboot.org/c/coreboot/+/33655 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-06-26mb/google/hatch: Remove pulls on NC padsFurquan Shaikh
There is no need to add internal termination (PU/PD) on the not-connected pads. This change gets rid of the terminations on the NC pads. Change-Id: I3df538d7127e5ef75e6e6ff9db3524e26f0450ed Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33570 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2019-06-26mb/google/hatch/variants/baseboard: Update PL2 power limit valueSumeet Pawnikar
Update PL2 power limit value from 44W to 64W. BUG=None BRANCH=None TEST=Build and Boot hatch EVT Change-Id: I3f4b5ab8bf0ce9464c322c148843f5a3e8d706d9 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33662 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Shelley Chen <shchen@google.com>
2019-06-21mb/google/hatch/variants/kindred: Update memory strap GPIOsDavid Wu
According to the latest schematic (b:127996858#comment38), MEM_CONFIG_0 --> GPP_H19 MEM_CONFIG_1 --> GPP_H22 MEM_CONFIG_2 --> GPP_F10 MEM_CONFIG_3 --> GPP_F3 BUG=none BRANCH=none TEST=Boot kindred proto board Change-Id: Ib79f9454116583a94fe1fd53a37ed928d32988d5 Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33617 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2019-06-21mb/google/hatch: Do not pull down GPP_F2 internallyPhilip Chen
There is already an external pull-up/down resistor tied to this pin to identify if the board is single-channel or dual-channel memory SKU. BUG=b:135496271 BRANCH=none TEST=build Signed-off-by: Philip Chen <philipchen@google.com> Change-Id: Ie218657fd9dde113ab26cf5551d1dff1b6e392b6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/33583 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-06-20mb/google/hatch: Remove unused USB2 port5 from baseboard devicetreeAamir Bohra
Hatch newer board revision do not use USB port5 for discrete BT. Hence remove the port configuration and UBS2 P5 asl entry. The older board version would continue to use USB2 P5 hence moved the entry to overridetree.cb Change-Id: I98297d6b81e3184b7b0a14710f3790f5df30d68b Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33060 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2019-06-19mb/google/hatch/variants/hatch: Adjust all I2C CLK to meet specJohn Su
After adjustment on Hatch Touch Pad CLK: 383.4 KHz Touch Screen CLK: 381.6 KHz SAR Sensor CLK: 392.0 KHz Audio codec CLK: 386.0 KHz BUG=b:134911522 BRANCH=master TEST=emerge-hatch coreboot chromeos-bootimage measure by scope with hatch. Change-Id: Iee2b692c268381af267b70e92a577ac89ce41cbb Signed-off-by: John Su <john_su@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33384 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-06-16mb/google/hatch: Move memory strap GPIOs under variant gpio headerAamir Bohra
Move the memory strap gpios to variant/gpio.h, as the memory straps are different for helios. Change-Id: I1833c9539687011ee27fd3e88c0581e30ca59354 Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33541 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-06-15mainboard/google/hatch: Scrub Helios GPIOsTim Wawrzynczak
Helios has a number of GPIO changes w/r/t to its baseboard. Override early, sleep and normal GPIOs as appropriate. BUG=b:135257452 BRANCH=none TEST=Compile only (no boards to test with) Change-Id: I45793ad6515df5af5b925d92106bd943374353d4 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33485 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-06-14hatch: Fix pen eject wake polarityTim Wawrzynczak
The gpio_key wakeup_event_action in the ACPI tables was backwards, causing devices to wake up on pen insertion instead of removal. Changed to EV_ACT_DEASSERTED. BUG=b:134547896 BRANCH=none TEST=Verified in OS, device only wakes up on pen removal Change-Id: I0816ed9fb23cf00fd8e40bcdd25ff7a9f48badbd Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33427 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-14mainboard/google/hatch: Update Helios device treeTim Wawrzynczak
Update Helios device tree override to match schematics. BUG=b:133182138 BRANCH=none TEST=Compiles Change-Id: I3d15fc43651a289d16ffb3cfadaea8f786e858fc Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33050 Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-13mb/google/hatch/variants/helios: Use LPDDR3 memoryPaul Fagerburg
Change the SPD makefile to use the LPDDR3 SPDs. Set up the arrays for mapping SoC DQS pins to LPDDR3 pins. BRANCH=none BUG=b:133455595 TEST=`FEATURES="noclean" FW_NAME="helios" emerge-hatch chromeos-ec depthcharge vboot_reference libpayload coreboot-private-files intel-cmlfsp coreboot-private-files-hatch coreboot chromeos-bootimage` Ensure the firmware builds without error. Change-Id: Iebaba2ec65dfcf36674b4733b421ada107b22b09 Signed-off-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33456 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Shelley Chen <shchen@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-13mb/google/{hatch, sarien, arcada}: Make HECI1 chip config disableSubrata Banik
This patch is not actually disabling HECI1 as it requires a dedicated FSP UPD for WHL/CML SoC code to set this HECI1 chip config. Change-Id: Ia88f3315a9dc3365d0acc13ed887e7c596c97c91 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33194 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-06-12mb/google/hatch: Disable dynamic clock gating for cr50's GPIOSubrata Banik
Disable dynamic clock gating for the community cr50's IRQ lives on. That IRQ is pulsed very quickly, and with clock gating enabled pulses tend to be missed. This is expecially true on the default 0.0.22 firmware that cr50 comes with out of the factory. BUG=b:130764684 b:130338605 BRANCH=None TEST=Boot hatch with cr50 "intap" firmware that can vary the pulse width, observe that even with sub-microsecond pulses no IRQs are missed. Change-Id: I34d14fb7cc97e33eecfda2c99cc53a541c87662d Signed-off-by: Subrata Banik <subrata.banik@intel.com> Signed-off-by: Evan Green <evgreen@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33326 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-06-09mb/google/hatch: Add 16G 2666 LPDDR3 SPDShelley Chen
One variant is asking for support for 16G 2666 LPDDR3, so adding generic SPD for that. BUG=b:133455595 BRANCH=None TEST=None as this is not being used yet Change-Id: If16a101119aabc30d6ea83e95e9ded2e089a982d Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33274 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2019-06-09mb/google/hatch: Add 8G 3200 SPDShelley Chen
One variant is asking for support for 8G 3200 DDR4, so adding generic SPD for that. BUG=b:132920013 BRANCH=None TEST=None as this is not being used yet Change-Id: I89cd3287aaf0baf384c4fe82d0881b0c48e09753 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33258 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-05mb/google/hatch: Increase RW_LEGACY to 1M for 16MB BIOSShelley Chen
The RW_LEGACY section needs to be minimum 1M. For the 16MB BIOS region, we had this region set too small, which was causing the firmware_FMap FAFT test to fail. BUG=b:133857135, b:129464811 BRANCH=None TEST=test_that -b hatch <IP> firmware_FMap Change-Id: Ie6311613ca3bb08e7f058a41d12f9a1153dc9c5e Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33212 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2019-06-04mb/google/hatch: Enable LTR for PCIe portsFurquan Shaikh
Enable LTR for NVMe and WiFi PCIe ports so that they can use ASPM L1.2 BUG=b:134195632 TEST=Verified L1 substate with lspci on hatch: Before: L1SubCtl1: PCI-PM_L1.2+ PCI-PM_L1.1+ ASPM_L1.2- ASPM_L1.1+ After: L1SubCtl1: PCI-PM_L1.2+ PCI-PM_L1.1+ ASPM_L1.2+ ASPM_L1.1+ Change-Id: I7fce60897b78dde12747ac7fb857c988d16118ab Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33161 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-05-31mainboard/google/hatch: Add Helios supportTim Wawrzynczak
Add Helios as a variant of Hatch. BUG=b:133182138 BRANCH=None TEST=util/abuild/abuild -p none -t google/hatch -x -a attempts to build a Helios target. Change-Id: I64ba06932eb0ee32405f7b14a94971a64c8fce71 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32918 Reviewed-by: Shelley Chen <shchen@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-05-31mb/google/hatch: Create helios variantTim Wawrzynczak
Created helios (hatch variant). Currenly copied from kohaku. Helios- specific changes will come later. BUG=b:133182138 BRANCH=none TEST=none Change-Id: I9d151621a1c42e6f3cadb288f7ea476828c059b5 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32919 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2019-05-31mb/google/hatch: Create kindred variantPaul Fagerburg
Create the Kindred variant of Hatch by taking a copy of the Hatch files as placeholders. Kindred-specific changes will happen in future CLs. BUG=b:133181366 BRANCH=NONE TEST=util/abuild/abuild -p none -t google/hatch -x -a make sure the build includes GOOGLE_KINDRED Change-Id: I09ad3da0505d599fc3797d7fa24b4dc170dcd18b Signed-off-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32936 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-05-23mb/google/hatch/variants: Fix DPTF sensor IDsEvan Green
There are indeed two temperature sensors hooked up to the EC, but they are indexed as 0 and 1, not 1 and 2. BUG=b:132999028 TEST=Boot hatch with hardened EC, observe no more index overflows Change-Id: Ia7f503bc1dc941635db52fce40f217bf34da6d2b Signed-off-by: Evan Green <evgreen@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32920 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-05-21mb/google/kohaku: Set ACPI_GPIO_IRQ_EDGE_BOTH for headset INTKane Chen
Currently, GPP_H0 gpio input rout is set to GPI_INT. So, ACPI_GPIO_IRQ is required for GPP_H0 in devicetree This change also aligns hatch's setting. BUG=b:131742713 TEST=headset is working Change-Id: Ie1264641bc4dfa5f98b6dab2d6f2133a6f9cbdb8 Signed-off-by: Kane Chen <kane.chen@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32845 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ben Kao <ben.kao@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2019-05-20mb/google/{arcada, hatch, sarien}: Override FSP default GPIO PM configurationSubrata Banik
sarien/arcada: GPIO_COMM_0/2/3/4: Enable gpio community all PM configuration GPIO_COMM_1: Disable RCOMP clock gating due to GPP_D18 IRQ mapped for H1 TPM. hatch: GPIO_COMM_0/1/2/3: Enable gpio community all PM configuration GPIO_COMM_4: Disable RCOMP clock gating due to GPP_C21 IRQ mapped for H1 TPM. BUG=b:130764684 TEST=H1 TPM interrupt working find and able to boot from fixed boot media Change-Id: Ia4d5483847a4d243b9038119d4bb5990591cc754 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32848 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-05-20mb/google/hatch: Change SD_CD# reset config to PLTRSTKrishna Prasad Bhat
The system should boot fine to OS on pressing power button before the system enters G3. However, on hatch, we observe that the system waits for few seconds at "Starting kernel" and then resets, with SD card tray inserted and SD_CD# pad reset config set to DEEP. Hence configuring SD_CD# pad reset config to PLTRST. BUG=b:129933011 TEST=Built and verified on hatch. Change-Id: Ic4466b96332f095ff39b28d98607e95fc3d12d6a Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32782 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-05-15soc/intel/cannonlake: Support different SPD read type for each slotPhilip Chen
Also clean up cannonlake_memcfg_init. The major changes include: (1) Add enum 'mem_info_read_type' to spd_info. (2) Add per-dimm-slot spd_info to cnl_mb_cfg. (3) Setup memory config for each slot independently. (4) Squash meminit_memcfg_spd(). BUG=chromium:960581, b:124990009 BRANCH=none TEST=boot hatch, hatch_whl, and kohaku Change-Id: I686a85996858204c20fd05ef24787a0487817c34 Signed-off-by: Philip Chen <philipchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32513 Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-05-13mainboard: remove "recovery" gpio, selectively add "presence" gpio.Matt Delco
The gpio table is only used by depthcharge, and depthcharge rarely has a need for the "recovery" gpio. On a few boards it does use the gpio as a signal for confirming physical presence, so on that boards we'll advertise the board as "presence". All these strings probably should have been #defines to help avoid typos (e.g., the "ec_in_rw" in stout seems questionable since everybody else uses "EC in RW"). Cq-Depend: chromium:1580454 BUG=b:129471321 BRANCH=None TEST=Local compile and flash (with corresponding changes to depthcharge) to 2 systems, one with a "presence" gpio and another without. Confirmed that both systems could enter dev mode. Change-Id: Id6d62d9e48d3e6646cbc1277ea53f0ca95dd849e Signed-off-by: Matt Delco <delco@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32718 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
generated by cgit v1.2.3 (git 2.39.1) at 2024-07-17 18:12:25 +0000