coreboot.git - my copy of coreboot

Age	Commit message (Collapse)	Author
2019-12-20	mainboard/google/puff: Add extra USB configuration	Kangheui Won
	Adding extra USB configuration since Puff has different USB ports compared to hatch BRANCH=none BUG=b:146437609 TEST=none Change-Id: I42ef6b6b718274953711c84ebe90971f108501fa Signed-off-by: Kangheui Won <khwon@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37853 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
2019-12-20	mainboard/google/puff: Enable pcie7 ep in dt	Edward O'Callaghan
	Missing bus init for RTL8111H ethernet chip hanging on bus. V.2: Include admendments from Kangheui. BRANCH=none BUG=b:146437819 TEST=./util/abuild/abuild -p none -t google/hatch -x -a Change-Id: I22aba312f183ea05eeb81d326ca0c05ce340a2e8 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37804 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-12-20	mainboard/google/puff: Clean up dt for pci 15.2	Edward O'Callaghan
	Seems nothing special is needed here from coreboot. V.2: Fix typo as well in speed map. BRANCH=none BUG=b:143047058 TEST=./util/abuild/abuild -p none -t google/hatch -x -a Change-Id: Ief750f98677b2017af78fb0b5bc98e1492dedbe4 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37736 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-12-19	mainboard/google/puff: enable emmc	Kangheui Won
	enable eMMC in puff/overridetree.cb BRANCH=none BUG=b:146455177 TEST=./util/abuild/abuild -p none -t google/hatch -x -a Change-Id: I432f437e0c9a618bbbf76d22976ea757c8fbdb83 Signed-off-by: Kangheui Won <khwon@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37817 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
2019-11-07	hatch: Create puff variant	Edward O'Callaghan
	Includes: - gpio mappings, - overridetree.cb, - kconfig adjustments for reading spd over smbus. V.2: Rework devicetree with comments and drop some useless gpio maps. BUG=b:141658115 TEST=./util/abuild/abuild -p none -t google/hatch -x -a Change-Id: I6449c4fcc1df702ed4f0d35afd7b0981e4c72323 Signed-off-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36452 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>