| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2019-05-15 | soc/intel/cannonlake: Support different SPD read type for each slot | Philip Chen | |
| Also clean up cannonlake_memcfg_init. The major changes include: (1) Add enum 'mem_info_read_type' to spd_info. (2) Add per-dimm-slot spd_info to cnl_mb_cfg. (3) Setup memory config for each slot independently. (4) Squash meminit_memcfg_spd(). BUG=chromium:960581, b:124990009 BRANCH=none TEST=boot hatch, hatch_whl, and kohaku Change-Id: I686a85996858204c20fd05ef24787a0487817c34 Signed-off-by: Philip Chen <philipchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32513 Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> | |||
| 2019-04-29 | mb/google/hatch/variants/kohaku: Add support for LPDDR3 configurations | Paul Fagerburg | |
| First configuration supported is 8 GB system memory: 4 x 2 GB (K4E6E304ED-EGCG). BRANCH=none BUG=b:129706819 TEST=ensure the firmware builds without error; I don't have hardware available to test this just yet. Signed-off-by: Paul Fagerburg <pfagerburg@chromium.org> Change-Id: Ibd92d585118ff75492e8a7188dcdb2a286836d56 Reviewed-on: https://review.coreboot.org/c/coreboot/+/32364 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> | |||
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