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path: root/src/mainboard/google/hatch/variants/kohaku/gpio.c
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2021-01-21mb/google/hatch: do UART pad configuration at board-levelMichael Niewöhner
UART pad configuration should not be done in common code, because that may cause short circuits, when the user sets a wrong UART index. Thus, add the corresponding pads to the early UART gpio table for the board as a first step. Common UART pad config code then gets dropped in CB:48829. Also switch to `bootblock_mainboard_early_init` to configure the pads in early bootblock before console initialization, to make the console work as early as possible. The board does not do any other gpio configuration in bootblock, so this should not influence behaviour in a negative way (e.g. breaking overrides). Change-Id: I62ffbe36bd7b7675aa0f41a8c6e9214d04ad4ae5 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49428 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-11treewide: Remove "this file is part of" linesPatrick Georgi
Stefan thinks they don't add value. Command used: sed -i -e '/file is part of /d' $(git grep "file is part of " |egrep ":( */\*.*\*/\$|#|;#|-- | *\* )" | cut -d: -f1 |grep -v crossgcc |grep -v gcov | grep -v /elf.h |grep -v nvramtool) The exceptions are for: - crossgcc (patch file) - gcov (imported from gcc) - elf.h (imported from GNU's libc) - nvramtool (more complicated header) The removed lines are: - fmt.Fprintln(f, "/* This file is part of the coreboot project. */") -# This file is part of a set of unofficial pre-commit hooks available -/* This file is part of coreboot */ -# This file is part of msrtool. -/* This file is part of msrtool. */ - * This file is part of ncurses, designed to be appended after curses.h.in -/* This file is part of pgtblgen. */ - * This file is part of the coreboot project. - /* This file is part of the coreboot project. */ -# This file is part of the coreboot project. -# This file is part of the coreboot project. -## This file is part of the coreboot project. --- This file is part of the coreboot project. -/* This file is part of the coreboot project */ -/* This file is part of the coreboot project. */ -;## This file is part of the coreboot project. -# This file is part of the coreboot project. It originated in the - * This file is part of the coreinfo project. -## This file is part of the coreinfo project. - * This file is part of the depthcharge project. -/* This file is part of the depthcharge project. */ -/* This file is part of the ectool project. */ - * This file is part of the GNU C Library. - * This file is part of the libpayload project. -## This file is part of the libpayload project. -/* This file is part of the Linux kernel. */ -## This file is part of the superiotool project. -/* This file is part of the superiotool project */ -/* This file is part of uio_usbdebug */ Change-Id: I82d872b3b337388c93d5f5bf704e9ee9e53ab3a9 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41194 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-02acpi: Move ACPI table support out of arch/x86 (3/5)Furquan Shaikh
This change moves all ACPI table support in coreboot currently living under arch/x86 into common code to make it architecture independent. ACPI table generation is not really tied to any architecture and hence it makes sense to move this to its own directory. In order to make it easier to review, this change is being split into multiple CLs. This is change 3/5 which basically is generated by running the following command: $ git grep -iIl "arch/acpi" | xargs sed -i 's/arch\/acpi/acpi\/acpi/g' BUG=b:155428745 Change-Id: I16b1c45d954d6440fb9db1d3710063a47b582eae Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40938 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2020-04-06mb/google/hatch: Use SPDX for GPL-2.0-only filesAngel Pons
Done with sed and God Lines. Only done for C-like code for now. Change-Id: If85e246550abe323d6a2a7c6301e8e91858cbe3a Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40177 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-03-18mainboard/google: Remove copyright noticesPatrick Georgi
They're listed in AUTHORS and often incorrect anyway, for example: - What's a "Copyright $year-present"? - Which incarnation of Google (Inc, LLC, ...) is the current copyright holder? - People sometimes have their editor auto-add themselves to files even though they only deleted stuff - Or they let the editor automatically update the copyright year, because why not? - Who is the copyright holder "The coreboot project Authors"? - Or "Generated Code"? Sidestep all these issues by simply not putting these notices in individual files, let's list all copyright holders in AUTHORS instead and use the git history to deal with the rest. Change-Id: I09cc279b1f75952bb397de2c3f2b299255163685 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39607 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2020-01-22mb/google/hatch: Kohaku: Add MKBP to suspend wake eventsTim Wawrzynczak
This CL allows MKBP events from the EC to wake the system from suspend states. BUG=b:144122000 BRANCH=firmware-hatch-12672.B TEST=Verify that MKBP events generated from EC will wake the system from S0ix. Change-Id: I8a0d2c7ed89fa1ea937a08c3082cc5d3e782efff Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38496 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-12-25mb/google/hatch/variant/kohaku: Fix Kohaku baseboard/gpio.c mux commentsEdward O'Callaghan
Follow MEM_STRAP_* comment style to be consistent with other boards. BUG=b:144809606 BRANCH=hatch TEST=./util/abuild/abuild -p none -t google/hatch -x -a Change-Id: I4945f676f307af9b8c0baa1fbcaf33113de647c3 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37592 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-25mainboard/google/hatch: Move gpio GPP_H3 config up from baseboardEdward O'Callaghan
The baseboard GPIO table definitions are too straineous to the extend that variants need to redefine assumptions back to NC. Invert this so that baseboard by default assumes the safer NC and move the specific board configurations to their respective places. This patch handles the GPP_H3 gpio config for easier review. This toggles the MAX amp which not all boards have. Move the pin configuration to boards with the respective devicetree configuration following on from the theme of commit b417786525. BUG=b:142094759 BRANCH=none TEST=builds Change-Id: Iefd2223af79a13c8a42d07bc10b2772dbff6d3e5 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37922 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-12-25mainboard/google/hatch: Move gpio GPP_A* NC down into baseboardEdward O'Callaghan
The baseboard GPIO table definitions are too straineous to the extend that variants need to redefine assumptions back to NC. Invert this so that baseboard by default assumes the safer NC and move the specific board configurations to their respective places. This patch handles the GPP_A* group for easier review. BUG=b:142094759 BRANCH=none TEST=builds Change-Id: I29b4323ac80b1288b2562846217c4f377714fc2c Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37920 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-12-05hatch: Fix FPMCU pwr/rst gpio handlingCraig Hesling
1. No gpio control in bootblock 2. Disable power and assert reset in ramstage gpio 3. Power on and then deassert reset at the end of ramstage gpio 4. Disable power and assert reset when entering S5 On "reboot", the amount of time the power is disabled for is equivalent to the amount of time between triggering #4 and wrapping around to #3, which is about 400ms on Kohaku. Since #2 forces power off for FPMCU, S3 resume will still not work properly. Additionally, we must ensure that GPP_A12 is reconfigured as an output before going to any sleep state, since user space could have configured it to use its native3 function. See https://review.coreboot.org/c/coreboot/+/32111 for more detail. The control signals have been validated on a Kohaku in the following scenarios: 1. Cold startup 2. Issuing a "reboot" command 3. Issuing a "halt -p" and powering back on within 10 seconds 4. Issuing a "halt -p" and powering back on after 10 seconds 5. Entering and leaving S3 (does not work properly) 6. Entering and leaving S0iX BRANCH=hatch BUG=b/142751685 TEST=Verify all signals as mentioned above TEST=reboot flash_fp_mcu /opt/google/biod/fw/dartmonkey_v2.0.2417-af88cc91a.bin TEST=halt -p # power back on within 10 seconds flash_fp_mcu /opt/google/biod/fw/dartmonkey_v2.0.2417-af88cc91a.bin TEST=halt -p # power back on after 10 seconds flash_fp_mcu /opt/google/biod/fw/dartmonkey_v2.0.2417-af88cc91a.bin Change-Id: I2e3ff42715611d519677a4256bdd172ec98687f9 Signed-off-by: Craig Hesling <hesling@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37459 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-11-22mb/google/hatch/variant/kohaku: Config MEM_STRAP GPIOsShelley Chen
Kohaku always used the default MEM_STRAPs in hatch baseboard. Adding explicit configuration for Kohaku in the event that MEM_STRAP is set differently in the baseboard gpio file. BUG=b:144895517 BRANCH=hatch TEST=None ./util/abuild/abuild -p none -t google/hatch -x -a Change-Id: I8f7105b3925f17c1741660d84c83c5d15f398a8d Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37106 Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-16kohaku: Set GPP_A10 to NCShelley Chen
Setting GPP_A10 to NC now that older boards are deprecated and this GPIO is not in use anymore. BUG=b:142056166 BRANCH=hatch TEST=./util/abuild/abuild -p none -t google/hatch -x -a Change-Id: If8a249a3dcba90bb4ccb5e3f02595e680f789f93 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36869 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-08mb/google/kohaku: Assign GPP_A19 as reset_gpio of stylusSeunghwan Kim
Applying reset_gpio config of stylus for kohaku. GPP_A19 has been assigned in the latest schematics. We would keep GPP_A10 as output high for old revision devices temporarily. BUG=b:141914474 BRANCH=none TEST=verified stylus works internally Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com> Change-Id: I61f0f9a4378f47bf455f0726d44beeaf2f67197b Reviewed-on: https://review.coreboot.org/c/coreboot/+/35748 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>
2019-08-11mb/google/hatch: Fix Kohaku pen GPIO configurationTim Wawrzynczak
Oops, I missed this in the last CL. The pin needs to be configured as owned by GPIO, so that the kernel driver can bind it with an IRQ. BUG=b:139165490 TEST=Ensure kernel nastygram about inability to claim the IRQ is gone Change-Id: I26c08d75d8b4e3b834db6e90868239899605fa5b Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34815 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-08-09mb/google/hatch: Refactor override_early_gpio_tableTim Wawrzynczak
There was the potential for misuse of the override early GPIO table, because if the override early GPIO table did not have a corresponding entry in the base table, it would not get overridden, and there was no way to know except manual inspection (this has already happened here), so now all hatch mainboards are required to explicitly list out all of their required early GPIOs. TEST=booted several hatch boards, verified that they can communicate with TPM and successfully train memory Change-Id: I0552b08a284fd6fb41a09fef431a0d006b0cf0bd Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34782 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2019-08-07mb/google/hatch: Kohaku: Re-setup dual-routing of EMR_GARAGE_DETTim Wawrzynczak
The pinctrl driver in the linux kernel automatically turns off SCI routing for all GPIOs exported via ACPI, so this patch sets up dual-routing of the EMR_GARAGE_DET signal so that one can be used for IRQs and one for the SCI wake. Change-Id: Iadeb4502c5a98a72ba651bdcad626609656c196f Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34780 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Shelley Chen <shchen@google.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-07mb/google/hatch: Kohaku: Add touchscreen controller to device treeTim Wawrzynczak
The touchscreen controller was never added to the device tree, and the next board rev will have this IC connected. Set it up in the device tree with conservative power resource timings from the datasheet. BUG=b:138869702 BRANCH=none TEST=compiles; current board rev does not have touch IC Change-Id: I759fb32f31c8eee0e6bd664c6a82308354ef5d08 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34763 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-08-07mb/google/kohaku: Enable stylus pen deviceSeunghwan Kim
Enabling stylus pen device and pen_eject event. - Adding enable_gpio for power sequencing - Configuring GPP_H4 and GPP_H5 as native function - Adding PENH device node for pen ejection event BUG=b:137326841 BRANCH=none TEST=Verified pen input operation and pen_eject event (pop-up and wake from s0ix on pen ejection) Change-Id: Ic252a1f90c0fc6cb9b1e426d75a8b503824681f3 Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com> Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34581 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2019-04-19kohaku: mb/hatch/gpio: Scrub Kohaku GPIOs.Tim Wawrzynczak
Ensure Kohaku GPIO pins are configured correctly w/r/t Hatch. Implement the base/override model for GPIOs (regular and early). The 'hatch' baseboard contains the base GPIOs, and variants can override individual pads. BUG=b:129707481 BRANCH=none TEST=Compiles for all variants. Change-Id: Ie5c83a0538d367ea11e9499f21cea41891d7a78e Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32326 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
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