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path: root/src/mainboard/google/hatch/variants/baseboard/gpio.c
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2020-05-11treewide: Remove "this file is part of" linesPatrick Georgi
Stefan thinks they don't add value. Command used: sed -i -e '/file is part of /d' $(git grep "file is part of " |egrep ":( */\*.*\*/\$|#|;#|-- | *\* )" | cut -d: -f1 |grep -v crossgcc |grep -v gcov | grep -v /elf.h |grep -v nvramtool) The exceptions are for: - crossgcc (patch file) - gcov (imported from gcc) - elf.h (imported from GNU's libc) - nvramtool (more complicated header) The removed lines are: - fmt.Fprintln(f, "/* This file is part of the coreboot project. */") -# This file is part of a set of unofficial pre-commit hooks available -/* This file is part of coreboot */ -# This file is part of msrtool. -/* This file is part of msrtool. */ - * This file is part of ncurses, designed to be appended after curses.h.in -/* This file is part of pgtblgen. */ - * This file is part of the coreboot project. - /* This file is part of the coreboot project. */ -# This file is part of the coreboot project. -# This file is part of the coreboot project. -## This file is part of the coreboot project. --- This file is part of the coreboot project. -/* This file is part of the coreboot project */ -/* This file is part of the coreboot project. */ -;## This file is part of the coreboot project. -# This file is part of the coreboot project. It originated in the - * This file is part of the coreinfo project. -## This file is part of the coreinfo project. - * This file is part of the depthcharge project. -/* This file is part of the depthcharge project. */ -/* This file is part of the ectool project. */ - * This file is part of the GNU C Library. - * This file is part of the libpayload project. -## This file is part of the libpayload project. -/* This file is part of the Linux kernel. */ -## This file is part of the superiotool project. -/* This file is part of the superiotool project */ -/* This file is part of uio_usbdebug */ Change-Id: I82d872b3b337388c93d5f5bf704e9ee9e53ab3a9 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41194 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-02acpi: Move ACPI table support out of arch/x86 (3/5)Furquan Shaikh
This change moves all ACPI table support in coreboot currently living under arch/x86 into common code to make it architecture independent. ACPI table generation is not really tied to any architecture and hence it makes sense to move this to its own directory. In order to make it easier to review, this change is being split into multiple CLs. This is change 3/5 which basically is generated by running the following command: $ git grep -iIl "arch/acpi" | xargs sed -i 's/arch\/acpi/acpi\/acpi/g' BUG=b:155428745 Change-Id: I16b1c45d954d6440fb9db1d3710063a47b582eae Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40938 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2020-04-06mb/google/hatch: Use SPDX for GPL-2.0-only filesAngel Pons
Done with sed and God Lines. Only done for C-like code for now. Change-Id: If85e246550abe323d6a2a7c6301e8e91858cbe3a Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40177 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-03-18mainboard/google: Remove copyright noticesPatrick Georgi
They're listed in AUTHORS and often incorrect anyway, for example: - What's a "Copyright $year-present"? - Which incarnation of Google (Inc, LLC, ...) is the current copyright holder? - People sometimes have their editor auto-add themselves to files even though they only deleted stuff - Or they let the editor automatically update the copyright year, because why not? - Who is the copyright holder "The coreboot project Authors"? - Or "Generated Code"? Sidestep all these issues by simply not putting these notices in individual files, let's list all copyright holders in AUTHORS instead and use the git history to deal with the rest. Change-Id: I09cc279b1f75952bb397de2c3f2b299255163685 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39607 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2020-02-26mainboard/hatch: Fix GPE wake commentsEdward O'Callaghan
The indirection of names is exceedingly confusing for ultimately the single interrupt trace of EC_PCH_WAKE_ODL between the EC gpio#74 to GPD2/LAN_WAKE# on the PCH side. This helps folks chase this indirection down through the code. BUG=b:147026979 BRANCH=none TEST=builds Change-Id: I35d746a202dae06d2f6f1edfaa3889864b09f50d Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38491 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-12-25mainboard/google/hatch: Move gpio GPP_H3 config up from baseboardEdward O'Callaghan
The baseboard GPIO table definitions are too straineous to the extend that variants need to redefine assumptions back to NC. Invert this so that baseboard by default assumes the safer NC and move the specific board configurations to their respective places. This patch handles the GPP_H3 gpio config for easier review. This toggles the MAX amp which not all boards have. Move the pin configuration to boards with the respective devicetree configuration following on from the theme of commit b417786525. BUG=b:142094759 BRANCH=none TEST=builds Change-Id: Iefd2223af79a13c8a42d07bc10b2772dbff6d3e5 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37922 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-12-25mainboard/google/hatch: Move gpio GPP_C* NC down into baseboardEdward O'Callaghan
The baseboard GPIO table definitions are too straineous to the extend that variants need to redefine assumptions back to NC. Invert this so that baseboard by default assumes the safer NC and move the specific board configurations to their respective places. This patch handles the GPP_C15 group for easier review. BUG=b:142094759 BRANCH=none TEST=builds Change-Id: I578245e24895d361d80ad016a4f18204e2b6e1ca Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37921 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-12-25mainboard/google/hatch: Move gpio GPP_A* NC down into baseboardEdward O'Callaghan
The baseboard GPIO table definitions are too straineous to the extend that variants need to redefine assumptions back to NC. Invert this so that baseboard by default assumes the safer NC and move the specific board configurations to their respective places. This patch handles the GPP_A* group for easier review. BUG=b:142094759 BRANCH=none TEST=builds Change-Id: I29b4323ac80b1288b2562846217c4f377714fc2c Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37920 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-12-05hatch: Fix FPMCU pwr/rst gpio handlingCraig Hesling
1. No gpio control in bootblock 2. Disable power and assert reset in ramstage gpio 3. Power on and then deassert reset at the end of ramstage gpio 4. Disable power and assert reset when entering S5 On "reboot", the amount of time the power is disabled for is equivalent to the amount of time between triggering #4 and wrapping around to #3, which is about 400ms on Kohaku. Since #2 forces power off for FPMCU, S3 resume will still not work properly. Additionally, we must ensure that GPP_A12 is reconfigured as an output before going to any sleep state, since user space could have configured it to use its native3 function. See https://review.coreboot.org/c/coreboot/+/32111 for more detail. The control signals have been validated on a Kohaku in the following scenarios: 1. Cold startup 2. Issuing a "reboot" command 3. Issuing a "halt -p" and powering back on within 10 seconds 4. Issuing a "halt -p" and powering back on after 10 seconds 5. Entering and leaving S3 (does not work properly) 6. Entering and leaving S0iX BRANCH=hatch BUG=b/142751685 TEST=Verify all signals as mentioned above TEST=reboot flash_fp_mcu /opt/google/biod/fw/dartmonkey_v2.0.2417-af88cc91a.bin TEST=halt -p # power back on within 10 seconds flash_fp_mcu /opt/google/biod/fw/dartmonkey_v2.0.2417-af88cc91a.bin TEST=halt -p # power back on after 10 seconds flash_fp_mcu /opt/google/biod/fw/dartmonkey_v2.0.2417-af88cc91a.bin Change-Id: I2e3ff42715611d519677a4256bdd172ec98687f9 Signed-off-by: Craig Hesling <hesling@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37459 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-10-30hatch: refactor gpio table into baseboard, allow empty SPDsPaul Fagerburg
Each variant needed to define variant_early_gpio_table(), even if it didn't need to make any changes. Added a __weak version of the function into baseboard/gpio.c. Certain upcoming Hatch variants will not use SPD files. Allow SPD_SOURCES in spd/Makefile.inc to be empty. BUG=None BRANCH=None TEST=Build coreboot and see that it builds without error Change-Id: Ie946cfd7c071824168faa38fd53bd338a5a451e1 Signed-off-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36068 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-09mb/google/hatch: Set FPS as wake sourceShelley Chen
BUG=b:142131099 BRANCH=None TEST=powerd_dbus_suspend, ensure DUT in S0ix touch fp sensor and ensure DUT wakes up in S0 Change-Id: If57094aa1076d79ac0886b71fa5532411bfeb45f Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35903 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2019-09-20mb/google/hatch: Remove GPIO_DRIVER from pen eject GPIO configurationTim Wawrzynczak
A closer read of the EDS indicates that when GPIO Driver mode is selected, GPIO input event updates are limited to GPI_STS only. GPI_GPE_STS updates are therefore masked, and we don't want to enable this behavior. It masks the GPE and does not allow us to see this GPE as a wake source, obscuring the reason that the system woke up. Also switch the IRQ from level-triggered to edge-triggered, otherwise the system will auto-wake from any sleep state when the pen is ejected from the garage. BUG=b:132981083 BRANCH=none TEST=Wake up system from S0ix using pen eject, verify that mosys eventlog shows GPE#8 as the S0ix wakeup source. Wake up system from S3 via pen eject, and verify that the wakeup source shows as GPE#8. Change-Id: If017e12e23134f5cfed7cbb6047cc9badd9bf7e8 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35459 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-09mb/google/hatch: Refactor override_early_gpio_tableTim Wawrzynczak
There was the potential for misuse of the override early GPIO table, because if the override early GPIO table did not have a corresponding entry in the base table, it would not get overridden, and there was no way to know except manual inspection (this has already happened here), so now all hatch mainboards are required to explicitly list out all of their required early GPIOs. TEST=booted several hatch boards, verified that they can communicate with TPM and successfully train memory Change-Id: I0552b08a284fd6fb41a09fef431a0d006b0cf0bd Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34782 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2019-08-07mb/google/hatch: Kohaku: Re-setup dual-routing of EMR_GARAGE_DETTim Wawrzynczak
The pinctrl driver in the linux kernel automatically turns off SCI routing for all GPIOs exported via ACPI, so this patch sets up dual-routing of the EMR_GARAGE_DET signal so that one can be used for IRQs and one for the SCI wake. Change-Id: Iadeb4502c5a98a72ba651bdcad626609656c196f Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34780 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Shelley Chen <shchen@google.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-31mb/google/hatch: Initialize SSD GPIOs in bootblockShelley Chen
Moving these to bootblock as we are seeing some instances where devices are rebooting into the recovery broken screen with the 0x5a error (no bootable storage device in system). This needed to be done for KBL platforms and never got transferred to hatch. Please reference https://review.coreboot.org/c/coreboot/+/23647 BUG=b:137681648 BRANCH=None TEST=Run autotest faft_bios and faft_ec suites Change-Id: I8cf09c26d77d890f5d0490709504e9edf485a93f Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34484 Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-19mb/google/hatch: Fix SD card is detected as read only issueSubrata Banik
This patch configures GPIO pin GPP_G7 as NF1 with internal pull down. As per schematics SD host controller SD_WP pin is not connected to uSD card connector. Configured gpio pin as NF1 with internal pull down in order to overcome gpio default state in hatch which makes SoC SD_WP pin is enable. BUG=b:137729527 BRANCH=None TEST=Able to write/read data to/from sd card after mounting card device. Change-Id: I0187267670e1dea3e1d5e83d0b29967714d6065e Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34396 Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-18mb/google/hatch: Disable wireless chargingSubrata Banik
This patch makes VGPIO_3 GPIO PIN output and low independent of cnvi is connected or not. BUG=b:123062346 BRANCH=None TEST=boot up Hatch device and make sure VGPIO_3 gpio pin is driven low. Change-Id: I629b99676f56747de1b244724709e14069250097 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34376 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: V Sowmya <v.sowmya@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-16mb/google/hatch: Disable Bluetooth in bootblock and enable in ramstageShelley Chen
Currently, bluetooth FW is not loaded after a reboot. In order to do this, we have to disable the bluetooth disable gpio (GPP_C14) in bootblock and re-enable it in ramstage. BUG=b:137307516 BRANCH=None TEST=boot up Hatch device and make sure (in dmesg) that proper bluetooth FW in loaded Change-Id: Ic5e447d9de57790f7a100e9e03f36b047c19d8f9 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34354 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-11mb/google/hatch: Fix interrupt trigger type for GPP_H0(HP_INT_L)Furquan Shaikh
HP_INT_L(GPP_H0) is configured for GPIO IRQ instead of APIC IRQ since it needs to trigger on both edges. With GPIO IRQ, it is necessary to configure the trigger type in coreboot to match the ACPI configuration. This is because: 1. ACPI configuration is used by intel-pinctrl driver in Linux kernel to re-configure the trigger type for the pad in GPIO DW0 config register. This is done when kernel driver probes and requests irq for its device. 2. On resume from S3, the pad configuration gets reset and coreboot sets the trigger type to LEVEL. However, kernel driver does not probe again. This results in the trigger type being configured incorrectly. This change updates the GPIO configuration for GPP_H0 to set the same trigger type as advertised in ACPI for the kernel. BUG=b:132672011 TEST=Verified that S3 works fine. Verified that interrupt on GPP_H0 works fine on boot as well as after suspend/resume. Change-Id: Ieb44c7403a2f4911b4a8f422053dee8bcfb91d85 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34181 Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Sathya Prakash M R <sathya.prakash.m.r@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-08mb/google/hatch: Set GPP_D9 as enable pin for Goodix Touch Screen andFrank Wu
increase reset off delay time Goodix touchscreen cannot work in normal mode because PP3300_TOUCHSCREEN_DX dropped. Configure GPP_D9 as enable pin in the devicetree.cb to fix the power sequence. Increase reset_off_delay time from 1ms to 3ms to met the HW requirement. BUG=b:135287161 BRANCH=None TEST=local build and measure sequence with Goodix touch screen Change-Id: I33140869990aa4715c780b0fa322921e450530ef Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33808 Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-07mb/google/hatch: Update GPIO settings for SD card and SPI1 Chip selectKrishna Prasad Bhat
This patch updates the following GPIO settings. 1. Set Native termination for GPP_G0 - G4 SD card pins. 2. Set GPP_B19 to NF1. BUG=b:123907904 TEST=Verified SD card functionality on hatch. Checked for SD detection, transferred files to and from SD card. Change-Id: I4549ac7377d7f58f51cda0eb96a62604fd31d2f2 Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32176 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2019-07-02mb/google/hatch: Set trackpad irq and wake to GPP_A21Shelley Chen
Previously, We had to use GPP_A21 for trackpad wake and GPP_D21 for trackpad interrupts due to ITSS not honoring the INVERT config. Now that's fixed, we can configure trackpad wake and interrupts on GPP_A21 only. BUG=b:130436471 BRANCH=None TEST=1. boot a hatch device and make sure we can move the cursor with the trackpad 2. Run powerd_dbus_suspend and wake by clicking on the trackpad and ensure through "mosys eventlog list" that the wake source is the trackpad.\ 3. Run "echo mem > /sys/power/state", wait until device goes into S3, click trackpad to ensure device wakes. Change-Id: I26a99206c42ba442f91ae577b98366fc2fd6c0ca Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33820 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2019-07-02mb/google/hatch: Add INVERT to all IOAPIC padsShelley Chen
Now that ITSS config is fixed, we can set the IOAPIC pad configs correctly. BUG=b:123967687 BRANCH=None TEST=Make sure Hatch is booting and tested out trackpad to make sure can move cursor and wake by clicking on the trackpad after running powerd_dbus_suspend. Change-Id: I0b125996338b6f16e03b7ca184f6337c696a5f64 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33819 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-26mb/google/hatch: Add a GPIO to enable/disable FPMCU powerPhilip Chen
A FPMCU power-control pin (GPP_C11) is added to the latest hatch reference schematic. Even though this is not implemented in hatch rev1 board, the future hatch family boards with FPMCU should all have this control pin. On the old boards without this control pin, GPP_C11 is a floating TP, and thus this patch should be backward-compatible. BUG=b:130307667, b:135216932 TEST=build Signed-off-by: Philip Chen <philipchen@google.com> Change-Id: I6a84eeb6aab562258e749a8a5d09dadfa0e43587 Reviewed-on: https://review.coreboot.org/c/coreboot/+/33655 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-06-26mb/google/hatch: Remove pulls on NC padsFurquan Shaikh
There is no need to add internal termination (PU/PD) on the not-connected pads. This change gets rid of the terminations on the NC pads. Change-Id: I3df538d7127e5ef75e6e6ff9db3524e26f0450ed Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33570 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2019-06-21mb/google/hatch: Do not pull down GPP_F2 internallyPhilip Chen
There is already an external pull-up/down resistor tied to this pin to identify if the board is single-channel or dual-channel memory SKU. BUG=b:135496271 BRANCH=none TEST=build Signed-off-by: Philip Chen <philipchen@google.com> Change-Id: Ie218657fd9dde113ab26cf5551d1dff1b6e392b6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/33583 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-05-20mb/google/hatch: Change SD_CD# reset config to PLTRSTKrishna Prasad Bhat
The system should boot fine to OS on pressing power button before the system enters G3. However, on hatch, we observe that the system waits for few seconds at "Starting kernel" and then resets, with SD card tray inserted and SD_CD# pad reset config set to DEEP. Hence configuring SD_CD# pad reset config to PLTRST. BUG=b:129933011 TEST=Built and verified on hatch. Change-Id: Ic4466b96332f095ff39b28d98607e95fc3d12d6a Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32782 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-05-06mainboard/google/hatch: Enable PEN_EJECT_L as wake & notify source.Tim Wawrzynczak
Updated GPP_A8 to be a GPI and SCI source, to support both wake and notifications. BUG=b:128941098 BRANCH=none TEST=Compiles, simulated pen eject with PCH_INT_L signal. Both evtest and waking from s0ix confirm this works. The output of /proc/interrupts confirms the correct interrupt is triggered. Change-Id: I080fb3cbfb3e2f55209ca31824b00ca820d70f78 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32487 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-04-30mb/google/hatch: Modify IRQ configuration to enable RT5682 headset INTNaveen Manohar
Patch corrects IRQ and GPIO configuration for RT5682 codec's Jack INT. Switching IOAPIC to GpioInt because ACPI Interrupt() doesn't support jack triggering on both edges. BUG=b:130180492 TEST=build and boot on a CML EVT board. Use evtest & verify headset jack detection functions as expected. Change-Id: Ia9bf8d554b54554f9ac1e78fd44a508964c8a14d Signed-off-by: Naveen Manohar <naveen.m@intel.com> Suggested-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32474 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Shelley Chen <shchen@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-25mb/google/hatch/: FPMCU not rebooted when DUT rebootsTim Wawrzynczak
Add FP_RST_ODL to early GPIO table, configured as low, so that the FPMCU will get reset when coreboot enters bootblock. BUG=b:130229952 BRANCH=none TEST=Compiles (no Hatch device w/FP to test) Change-Id: I8a8d8cc2c560f6518337f7500575fdc2265b6347 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32419 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2019-04-25mb/google/hatch: Pull up GPP_C13 for hatch and hatch_whlPhilip Chen
On EC end, we want to change this pin from push-pull to open-drain. And since there is no external pull-up resistor on the board, we'll have to configure this pin as internal-pull-up on AP end. BUG=b:129306003 TEST=None Change-Id: Ibc1f89fc25773220db009c6571400b01390dd756 Signed-off-by: Philip Chen <philipchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32292 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-04-19kohaku: mb/hatch/gpio: Scrub Kohaku GPIOs.Tim Wawrzynczak
Ensure Kohaku GPIO pins are configured correctly w/r/t Hatch. Implement the base/override model for GPIOs (regular and early). The 'hatch' baseboard contains the base GPIOs, and variants can override individual pads. BUG=b:129707481 BRANCH=none TEST=Compiles for all variants. Change-Id: Ie5c83a0538d367ea11e9499f21cea41891d7a78e Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32326 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-04-12mb/google/hatch: Use GPIO IRQ for sx9310 deviceFurquan Shaikh
This change uses GPIO IRQ instead of IOAPIC for GPP_A0 pad which is the interrupt line for sx9310. This is required because IRQ# used by GPP_A0 is allocated for PIRQ which does not allow IRQ# sharing. Additionally, this change also configures GPP_A6 for GPIO IRQ. GPP_A6 is currently unused in the devicetree. BUG=b:129794308 TEST=Verified that there are no interrupt storms on GPP_A0. Change-Id: Ibb510a647391c0d9cb854d23656bb4b1cb7756ab Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32270 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2019-04-12mb/google/hatch: Configure reset config to PLTRST for IOAPIC padsFurquan Shaikh
This change configures reset config for all pads routed to IOAPIC as PLTRST. This is required to ensure that the internal logic of the GPIO gets reset any time the platform enters S3 or powers off and avoids any interrupt storms on boot-up. BUG=b:129933011 TEST=Verified that there are no interrupt storms on boot-up from S5. Change-Id: Ib790280c9f1410fa18746d4d7d2a5027afd7585b Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32268 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2019-04-04mb/google/hatch: Change the DEVSLP reset config to PLTRSTRizwan Qureshi
In S3 the PCH is driving the DEVSLP signal low, assuming that the SATA device is already powered off. However on hatch the SATA power is still enabled. And, since DEVSLP is low, this causes the SATA device to not enter low power state. The fix here is to set the pad config to be reset on PLTRST assertion which will cause the pin to be high impedance state and will be pulled up by the SATA device. BUG=b:126611255 BRANCH=None TEST=Make sure that S3 and S0ix is working fine on hatch. And also make sure that DEVSLP is pulled high in S3. Change-Id: Ifb6a71a72244522c8dd8d48e9b9f8dc6feef8981 Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32136 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-04-02mb/google/hatch: Change GPIO_E1 settingJohn Su
For HW require to change GPIO_E1. Change GOIO_E1 setting from NF2(SATAGP1) to NF1(SATAPCIE1). BUG=b:123730924 TEST=flash BIOS and make sure hatch boots up properly Change-Id: I0f5569e13b17a2dc713be5031a63436e8f31f911 Signed-off-by: John Su <john_su@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32099 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-02mb/google/hatch: Re-configure GPP_A12 as GPO before entering sleepKrishna Prasad Bhat
GPP_A12 has a Native3 (SX_EXIT_HOLDOFF#) mode, which allows to delay resuming to S0. If this pad is not locked and platform was not initially designed for this functionality, malware could reconfigure this pads setting under OS (switch to Native3), which would make platform not able to resume until G3 is applied. To prevent misuse of this pad, re-configure this pad before entering S3 and S5 to guarantee that the pad configuration is correct. BUG=b:128686027 Change-Id: I1e7979baa491acf2c56d223afb4618f0f6429e37 Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32111 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-03-29mb/google/hatch: Deassert EN_PP3300_WWAN during sleepMaulik V Vaghela
Deassert EN_PP3300_WWAN to turn the WWAN module completely off when entering S5. This is the same fix in commit eeb475c5c for coral board. BUG=none BRANCH=none TEST=On hatch, Perform a quick system power cycle, verify that the modem is powered cycle and the SIM with PIN lock enabled requests unlocking. Change-Id: I3ec8ccb7618189b9e8586f5571a68d3309597ee7 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32051 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-03-28mb/google/hatch: Initialize FPMCU_PCH_BOOT1Shelley Chen
In the latest hatch schematics, BOOT1 for the FP MCU is now connected to the AP. Configuring it to be the same as BOOT0. BUG=b:126455006 BRANCH=None TEST=./util/abuild/abuild -p none -t google/hatch -x -a -c max Change-Id: Ibb451983674a7d812dc562cb8addb1dc50fb155c Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32060 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-03-27mb/google/hatch: Add GPIO_A8 for Pen detect functionDtrain Hsu
Add GPIO_A8 for pen detect function. BUG=b:122765828 TEST=flash BIOS and using switch to verify GPIO_A8 value change. Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Change-Id: Ie7c888ea61dd61e60c1d184565bd95e6b03777be Reviewed-on: https://review.coreboot.org/c/coreboot/+/31815 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-22mb/google/hatch: Enable FP MCUShelley Chen
AP communicates with FP MCU through gspi1. BUG=b:126455006 BRANCH=None TEST=ensure during bootup we see spi id spi-PRP0001:01 in dmesg FP MCU fw is not ready yet, so not much testing to be done yet. Signed-off-by: Shelley Chen <shchen@google.com> Change-Id: I2eba205d5e63664dca684fbd849454c5a2fe0d0e Reviewed-on: https://review.coreboot.org/c/coreboot/+/32017 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-14mb/google/hatch: Use MEM_CH_SEL to indicate single_channel skuShelley Chen
MEM_CH_SEL is used to indicate whether we are on a single or dual channel device, where MEM_CH_SEL = 1 for single channel skus and MEM_CH_SEL = 0 for dual channel skus. Initialize single_channel field (from GPP_F2), which will in turn initialize MemorySpdPtr pointers in cannonlake soc code. In the first build, we did not use GPP_F2, so we need to add an internal pulldown as those early devices were all dual channel devices. BUG=b:123062346, b:122959294 BRANCH=None TEST=Boot into current boards and ensure that we have 2 channels as expected Also, verify that GPP_F2 is set to 0. Change-Id: I89d022793580be603a93d0b177d73ce968529b5c Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31358 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-03-11mb/google/hatch: Enable audio supportSathya Prakash M R
Following changes are done to enable audio support on hatch 1. Enable I2C4 device at 400Khz at 1.8V 2. Configure GPIO for HP INT and SPKR_PA_EN 3. Add ACPI entry for RT5682 and MAX98357A 4. Enable I2S0 and I2S1 lines 5. Enable generic max98357a driver in Kconfig BUG=b:123738217 BRANCH=none TEST=Check SSDT table for RT5682 & MAX98357a entry. Verify audio using Sound Open firmware (SOF) Change-Id: I93f3917c19cc3f0f8fd7b5e1b4d9b24a59f45f84 Signed-off-by: Sathya Prakash M R <sathya.prakash.m.r@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31280 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-03-08mb/google/hatch: Initialize all gpiosShelley Chen
BUG=b:123490912 BRANCH=None TEST=flash BIOS and make sure hatch boots up properly Change-Id: I9e41f0b38703f2c7a2b5a7ac9b108f8f10070004 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31724 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-02-28mb/google/hatch: Add GPIO programming for GPP_C0 to GPP_C7Maulik V Vaghela
coreboot did not program all GPIOs from C0 to C7 correctly which are SMBUS GPIO. Some of the GPIOs are left in default mode which is native function but we need to configure as GPIO mode and provide proper configuration as per schematic. After fixing GPIO, CSME power gating issue also gets fixed since SMBUS was not getting idle due to GPIO configuration and CSME was not getting power gated due to SMBUS. BUG=b:123702553 BRANCH=none TEST=Check on hatch board. CSME was not getting power gated for s0ix. After applying this patch CSME is power gated now Change-Id: I5c6b9310dcc7bade0023abd5524781ce71df28be Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/31640 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-02-27mb/google/hatch: Initialize GPIO_PCH_WP early in bootRizwan Qureshi
Initialize GPIO_PCH_WP early in boot. Update cros_gpios[] array with GPIO_PCH_WP information. Also, Configure recovery mode GPIO as virtual since hatch does not have one. BUG=b:125943273 Change-Id: I0b7e6dbf9229941aca4952965fb54f07457dccae Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/c/31599 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-02-27mb/google/hatch: update SD card detect GPIORizwan Qureshi
SD_CD# in Cannonlake PCH is also wired to an internal virtual GPIO, expose that GPIO for kernel to configure card detect IRQ. BUG=b:123350329 Change-Id: I566cc2eb11dc257366897a1efba905b8ddcf493d Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/c/31553 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-02-22mb/google/hatch: Enable wake from trackpadShelley Chen
For some reason, wake does not currently work from GPP_D21, but IRQs are working fine from that gpio. Thus, we have to switch IRQ to GPP_D21 and wake to GPP_A21, which was previously used for IRQs from the trackpad. Additionally, we need to use two gpios for irqs and wake source at the moment because of b:123967687, where FSP is locking down PCR and configuring ITSS. We need to configure the wake source gpio as inverted and the IRQ gpio as non-inverted until the bug is resolved. BUG=b:121212459 BRANCH=None TEST=run evtest with trackpad Use trackpad with ChromeOS UI and make sure it reacts as expected. Run powerd_dbus_suspend and press trackpad and make sure DUT wakes. Change-Id: I7b236136befc05c6586d9ba69185ed4b5d385273 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/31533 Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-02-13mb/google/hatch: Configure GPIO pad for non-inversionAamir Bohra
This implementation configures GPIO (GPP_A21, GPP_C21, GPP_D16) pad in non-inversion mode i.e Rx PAD state is not inverted as it is sent from GPIO to IOAPIC. BUG=b:123315212 TEST=Tested for below: -> Verify touchpad is working fine. -> TPM init is successful and boot with fixed boot media. Change-Id: I6034fd07ccc96a19218d57ef8bb9049c4b963ea5 Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/31328 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-02-06mb/google/hatch: Configure I2C busesFurquan Shaikh
This change enables I2C bus 2, 3 and 4 in devicetree and configures GPIO pads for the same. It also configures pads for I2C5 as no-connect. BUG=b:123711244 TEST=Verified that i2c shows up in "i2cdetect -l" after booting to OS. Change-Id: Ib4714a670d73228332115415e4393f82802c6475 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/31237 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-30mb/google/hatch: Enable AP Wake from ECShelley Chen
Initialize EC_PCH_WAKE_ODL GPIO to make sure that ec events will wake the AP from suspend. Also create a task to initialize the hostevent wake mask properly. BUG=b:123325238,b:123325720 BRANCH=None TEST=from AP console: powerd_dbus_suspend from EC console: hostevent (make sure wake mask set) from EC console: gpioset PCH_WAKE_L 0 Make sure device wakes up Also, checked to make sure keyboard press wakes up device from S3. Change-Id: I53d5291a6b9ab9a21e89ccd21f172180ce473bd5 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/31100 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-01-24mb/google/hatch: Enable support for WWANMaulik V Vaghela
This patch enables relevant GPIOs to enable WWAN. WWAN also requires to enable USB 2 port 6 and USB3 port 5 which is already enabled in device tree related changes. BUG=b:120914069 BRANCH=none TEST=check if code compiles with changes. Change-Id: I1559bbc6168aec1a369bf3291d2c1e2f9a2fbe07 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/30678 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-01-24mb/google/hatch: Enable PCIe WLAN and BTMaulik V Vaghela
Enable PCIe WLAN for hatch 1. Enable PCI port 14 for PCIe WLAN 2. Enable CLKREQ, CLK SRC 3 for PCI port 14 3. GPIO pad config for WLAN and BT USB port for BT has already been enabled so not included in this patch BUG=b:120914069 BRANCH=none TEST=check if code compiles correctly and verify GPIO configuration with schematics Change-Id: I4f2a6eb37a467ad8b8cdde8fe6b657fabb383b04 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/30467 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
2019-01-23mb/google/hatch: Enable SD card support for hatchMaulik V Vaghela
Enable support for SD card support for hatch 1. Enable PCI device for SD and also configure SD detect GPIO 2. Configure SD card related GPIOs in gpio.c BUG=b:120914069 BRANCH=none TEST=Verify GPIO configuration with schematics Change-Id: I8ccaa28323b1e1fcc192e245347a96309227660b Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/30545 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2019-01-07mb/google/hatch: Enable touch panel supportMaulik V Vaghela
Following changes are done to enable touch screen support on hatch 1. Enable I2C1 device at 400Khz at 3.3V 2. Configure GPIO for touch screen 3. Add ACPI entry for ELAN touch panel 4. update GPIO table with not connected GPIO pins for panel BUG=b:120914069 BRANCH=none TEST=check if code compiles with changes. Change-Id: I8dab07dad4cb197865bb9cf0e8da240810fcfabe Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/30425 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2019-01-01mb/google/hatch: Enable CNVi Wifi for hatchMaulik V Vaghela
This patch enables CNVi wifi for hatch 1. Enable CNVi device in device tree 2. Configure GPIO pad config for CNVi BUG=b:120914069 BRANCH=none TEST=check if code compiles correctly and verify GPIO configuration with schematics Change-Id: I0c5542737d3a629b6a40116b4aa8ab6cbdd6a4dc Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/30436 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-01mb/google/hatch: Add NC gpios for display and correct the orderMaulik V Vaghela
Correcting order of display related GPIOs and also adding not connected pin definitions for display GPIOs BUG=b:120914069 BRANCH=none TEST=check if code compiles with changes. Change-Id: I9498284d263516f65513d6395883b6b09dd70fd5 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/30544 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
2018-12-31mb/google/hatch: Enable NVME support for HatchV Sowmya
This patch enables the x4 NVME device for hatch, * Enable the Root port 9. * Assign the usage type for clock source. * Configure the GPIO for CLK SRC 1. BUG=b:120914069 BRANCH=none TEST=USE="-intel_mrc -bmpblk" emerge-hatch coreboot. Change-Id: I69be6b21a5ae5962877a5c38180b5ffac532fed4 Signed-off-by: V Sowmya <v.sowmya@intel.com> Reviewed-on: https://review.coreboot.org/c/30431 Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-12-31mb/google/hatch: Add the USB port configurationV Sowmya
This patch adds the configurations for, * USB 2.0 ports. * USB 3.0 ports. * Enables USB xHCI controller. * GPIO config for USB2_OC2 and USB2_OC3. * Add the ACPI objects to configure USB ports. BUG=b:120914069 BRANCH=none TEST=USE="-intel_mrc -bmpblk" emerge-hatch coreboot. Change-Id: Ia7b25c25b8208c678aeae3a32033611b69b54062 Signed-off-by: V Sowmya <v.sowmya@intel.com> Reviewed-on: https://review.coreboot.org/c/30457 Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-12-31mb/google/hatch: Enable SATA for HatchV Sowmya
This patch enables the SATA for hatch, * Enable the SATA port 1. * Configure the GPIO for SATA. BUG=b:120914069 BRANCH=none TEST=USE="-intel_mrc -bmpblk" emerge-hatch coreboot. Change-Id: Iaf800d1531688c3d3b82600038ea1d7160ae4b0b Signed-off-by: V Sowmya <v.sowmya@intel.com> Reviewed-on: https://review.coreboot.org/c/30435 Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-12-28mb/google/hatch: Enable console UARTMaulik V Vaghela
This patch incorporates following changes to enable console on UART0 1. update default console number to 0 2. Enable PCI port for UART0 GPIO configuration will be done by coreboot based on correct console number. Change-Id: I735d33674b276b28e2cbb753d3a6d83edbabe89d Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/30424 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
2018-12-25mb/google/hatch: Add HPD GPIO support for displaysMaulik V Vaghela
Adding hot plug detect GPIO support for external Type-C display in event for cable connect/disconnect. Change-Id: If9d52dc0f9916f761c8fdd88c76968aaf663e650 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/30365 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-12-23mb/google/hatch: Add memory init setup for hatchAamir Bohra
This implementation adds below support: 1. Add support to read memory strap. 2. Add support to configure below memory parameters -> rcomp resistor configuration -> dqs mapping -> ect and ca vref config 3. Include SPD configuration BUG=b:120914069 BRANCH=None TEST=USE="-intel_mrc -bmplk" emerge-hatch coreboot Change-Id: I9bda08bd0b9f91ebb96b39291e15473492a6bf19 Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/30248 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Shelley Chen <shchen@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-12-22mb/google/hatch: Enable Elan TrackpadShelley Chen
BUG=b:120914069 BRANCH=None TEST=USE="-intel_mrc" emerge-hatch coreboot Change-Id: I91db5745d1db16ab4b2fbb7f8c415bd7c1eb29e9 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/30227 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2018-12-22mb/google/hatch: Fixes to initial hatch mainboard checkinShelley Chen
Incorporating some feedback to initial hatch mainboard checking (CL:30169) that came in after the CL merged. Updated the chromeos.fmd with the following, * SI_ALL = 3MB * SI_BIOS = 16MB BUG=b:20914069 BRANCH=None TEST=./util/abuild/abuild -p none -t google/hatch -x -a -v Change-Id: I4e311c68873f10f71314e44d3a714639a06dbee8 Signed-off-by: Shelley Chen <shchen@google.com> Signed-off-by: V Sowmya <v.sowmya@intel.com> Reviewed-on: https://review.coreboot.org/c/30296 Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-12-21mb/google/hatch: Enable H1 TPM support over SPI interfaceAamir Bohra
Add code support to enable H1 TPM interfaced to SOC on GSPI0. The TPM interrupt is mapped to GPP_C21. BUG=b:120914069 TEST=USE="-intel_mrc -bmpblk" emerge-hatch coreboot Change-Id: Ib63a0b473f632d91745102ebd01993e8d65b9552 Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/30210 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-12-21mb/google/hatch: Clean up gpio definitions in hatch variantAamir Bohra
This implementation cleans up gpio configuration functions and limit definition to baseboard only for now, until variant specfic overides are needed. BUG=b:120914069 TEST=USE="-intel_mrc -bmpblk" emerge-hatch coreboot Change-Id: I563f6b97812b32d6e3d99e3df512dc112da78aea Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/30291 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-12-13mb/google/hatch: Creating skeleton directories and filesShelley Chen
Creating skeleton files and directories in mainboard for the new Hatch board. This is to facilitate development for different parties involved. BUG=None BRANCH=None TEST=./util/abuild/abuild -p none -t google/hatch -x -a Change-Id: I5fc60c178f83034abe5d846d0f4169072b66f448 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/30169 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-10-20 17:38:49 +0000