coreboot.git - my copy of coreboot

Age	Commit message (Collapse)	Author
2019-11-01	soc/intel/{cnl,icl}: Move globalnvs.asl/nvs.h into common/block/	Subrata Banik
	This patch creates a common instance of globalnvs.asl/nvs.h inside intel common code (soc/intel/common/block/) and ask cnl & icl soc code to refer globalnvs.asl and nvs.h from common code block. TEST=Able to build and boot Hatch and ICL DE system. Dump DSDT.asl to verify GNVS operation region presence after booting to OS. Change-Id: Ia9fb12a75557bd7dc38f6d22ba2b32065d18b3ee Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36457 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Michael Niewöhner Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-11-01	soc/intel/{IA-CPU/SOC}: Move sleepstates.asl into southbridge/intel/common/acpi	Subrata Banik
	This patch creates a common instance of sleepstates.asl inside intel common code (southbridge/intel/common/acpi) and asks all IA CPU/SOC code to refer sleepstates.asl from common code block. TEST=Able to build and boot Hatch and ICL DE system. Dump DSDT.asl to verify S0/S3/S4/S5 entries after booting to OS. Change-Id: Ie2132189f91211df74f8b5546da63ded4fdf687a Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36463 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-11	mb/google/hatch: Enable/disable GPIO clock gating	Tim Wawrzynczak
	Before the system enters S0ix or S3, each GPIO community will have its dynamic clock gating turned on. Upon return to S0, the dynamic clock gating will be turned back off. BUG=b:130764684 BRANCH=none TEST=Used dut-power to verify that the clock gating is enabled in S0ix and S3. Also used Store(..., Debug) statements in the ASL code to verify it was getting called. Change-Id: I20ff2aac035eaa5912af6c946d837567a4918bbf Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34180 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-07-11	mb/google/hatch: Enable LPIT inclusion in DSDT	Tim Wawrzynczak
	Include the lpit.asl file in Hatch's DSDT definition. BUG=b:130764684 BRANCH=none TEST=S3 suspend/resume and S0ix entry/exit work correctly. Ran > 200 iterations of suspend_stress_test and no issues found. Change-Id: If8ebff3db091257e8452869636c0e024f3123e8b Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34175 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2019-03-08	coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX)	Julius Werner
	This patch is a raw application of find src/ -type f \| xargs sed -i -e 's/IS_ENABLED\s*(CONFIG_/CONFIG(/g' Change-Id: I6262d6d5c23cabe23c242b4f38d446b74fe16b88 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31774 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-02-15	mb/google/hatch: Enable DPTF functionality	Sumeet Pawnikar
	Enable DPTF functionality on hatch platform. Change-Id: If9ef74364616f95b27b73c39fea42d2623d78ae2 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/31276 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-12-25	mb/google/hatch: Add SoC and EC asl files in DSDT	Aamir Bohra
	This implementation adds below code: 1. Add SOC ACPI code in dsdt.asl -> platform.asl -> globalnvs.asl -> cpu.asl -> northbridge.asl -> southbridge.asl -> sleepstate.asl 2. Add chromeos.asl in dsdt.asl 3. Add EC ACPI code in dsdt.asl -> superio.asl -> ec.asl 4. Remove config for WAK/PTS ACPI method as chromeec doesn't implement those. BUG=b:120914069 TEST=USE="-intel_mrc -bmpblk" emerge-hatch coreboot Change-Id: Icf1b1d7e34a7e863139c3583903f3b1e2cdc8da6 Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/30282 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2018-12-13	mb/google/hatch: Creating skeleton directories and files	Shelley Chen
	Creating skeleton files and directories in mainboard for the new Hatch board. This is to facilitate development for different parties involved. BUG=None BRANCH=None TEST=./util/abuild/abuild -p none -t google/hatch -x -a Change-Id: I5fc60c178f83034abe5d846d0f4169072b66f448 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/30169 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>