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Regenerate SPD for MT53E1G32D2NP-046 WT:B with correct value of ranks.
BUG=b:190692797
TEST=Build and boot to OS
Signed-off-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com>
Change-Id: Icee095c7114f1d6dd960f2134db3816b367bf987
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55384
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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The next guybrush build uses 2 new LPDDR4X memory chips:
- Micro MT53E1G32D2NP-046 WT:B
- Hynix H9HCNNNBKMMLXR-NEE
The MT53E2G32D4NQ-046 WT:A chip has been added to the global LPDDR4X
list since the last time guybrush was updated, so that's brought into
the guybrush SPD directory as lp4x-spd-10.hex, but it's not used.
BUG=b:186027256
TEST=Build only
Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: Ia5efd548f8b9442fb3703518387175aba8933a33
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52587
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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These SPDs were generated by the lpddr4 version of gen_spd.go from the
global_lp4x_mem_parts.json.txt file.
BUG=b:178715165
TEST=None
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I7b9bd04534d6e45dbfe10a0028052978ef3d7c17
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51020
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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