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path: root/src/mainboard/google/guybrush/mainboard.c
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2021-12-23ChromeOS: Refactor ACPI CNVS generationKyösti Mälkki
Remove chromeos_dsdt_generator() calls under mainboard, it is possible to make the single call to fill \CNVS and \OIPG without leveraging device operations. Change-Id: Id79af96bb6c038d273ac9c4afc723437fc1f3fc9 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55502 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-11mb/google/guybrush: Define ACPI Power Resources for FPMCUKarthikeyan Ramasubramanian
Currently all the power sequencing for FPMCU is done explicitly in different stages of coreboot. This can all be done by adding ACPI power resources for FPMCU and clean up the unused code. Here is the expected power sequence: PowerUp : Assert EN_PWR_FP -> 3 ms delay -> De-assert FPMCU_RST_ODL Shutdown : De-assert EN_PWR_FP -> Assert FPMCU_RST_ODL Reboot : Shutdown -> 200 ms delay -> PowerUp BUG=None TEST=Build and boot to OS in Guybrush. Ensure that the FP is able to unlock the system after the first login attempt. Ensure that the FP is able to wakeup the system. Observed that the power resource is added correctly in the FPMCU ACPI object Name (_PR0, Package (0x01) // _PR0: Power Resources for D0 { PR01 }) Name (_PR3, Package (0x01) // _PR3: Power Resources for D3hot { PR01 }) PowerResource (PR01, 0x00, 0x0000) { Method (_STA, 0, NotSerialized) // _STA: Status { Return (0x01) } Method (_ON, 0, Serialized) // _ON_: Power On { \_SB.CTXS (0x0B) \_SB.STXS (0x20) \_SB.STXS (0x0B) } Method (_OFF, 0, Serialized) // _OFF: Power Off { \_SB.CTXS (0x0B) \_SB.CTXS (0x20) } } Change-Id: I52322eaecf6961ff9a196ca9ab2d58b7d4599d4f Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58705 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Rob Barnes <robbarnes@google.com>
2021-10-27mb/google/guybrush: Move GSC_SOC_INT_L from GPIO_3 to GPIO_85Karthikeyan Ramasubramanian
GSC_SOC_INT_L gpio is used by Google Security Chip (GSC) to interrupt SoC when the SoC is in S0 state. Hence use GPIO_85 which is in S0 domain and save the GPIO_3 in S5 domain for other use-cases. This move applies to all board except: * Guybrush * Nipperkin board version 1 Update the GPIO configuration, device tree configuration accordingly. BUG=b:202992077 TEST=Build and boot to OS in Guybrush and Nipperkin. Ensure that the SoC <-> TPM communication is working fine. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: I019f10f2f457ab81bcff77ce8ca609b2b40cb2ea Reviewed-on: https://review.coreboot.org/c/coreboot/+/58638 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Rob Barnes <robbarnes@google.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-10-14mb/google/guybrush: Assert WWAN_AUX_RST_L on S0i3 entryKarthikeyan Ramasubramanian
Currently WWAN_AUX_RST_L is in S5 domain and does not get asserted on S0i3 entry. Based on the schematics, the pull-down on that signal leads to 10 mW power leakage on S0i3 entry. Assert the signal on S0i3 entry to achieve some power savings and de-assert it on S0i3 exit. BUG=b:195748540 TEST=Build and boot to OS in Guybrush. Ensure that the signal gets asserted on S0i3 entry and de-asserted on S0i3 exit. Trigger suspend/resume cycles and ensure that the WWAN module is enumerated after each cycle. Change-Id: I43c8655ee5209779748e4365db973e094cb08aca Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58275 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-16mb/google/guybrush: Update GPIOs for fingerprint MCUMartin Roth
Add mainboard finalize and shutdown call to match zork. Deassert EN_PWR_FP in bootblock, power up correctly in finalize. | Phase | SOC_FP_RST_L | EN_PWR_FP | S3 resume | |-----------|--------------|-----------|----------------------| | Bootblock | **Low** | **Low** | Maintain High / High | | Romstage | Low | Low | Maintain High / High | | Ramstage | Low | **High** | Maintain High / High | | Finalize | **High** | High | | | Shutdown | **Low** | **Low** | | BUG=b:191694480 TEST=Build, verify GPIO configuration. Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: Iaae5feec60abb2480777d1f99174254c5132bb43 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56499 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-06-17mb/*: Fix some indirect includesKyösti Mälkki
Fix build failures in the case <vc/.../chromeos.h> is removed. Change-Id: Ie45066f39cd6fb92cca697a6bd5bc8bb8c60b4e7 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55506 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-05-09mb/google/guybrush: Populate PIC IRQ dataRaul E Rangel
The PIC IRQs are required so we can correctly set up the PCI_INT registers. This only matters when booting in PIC mode. We don't need to set the IO-APIC registers since the linux kernel will auto-assign those to reduce conflicts. BUG=b:184766519 TEST=Boot guybrush with `pci=nomsi,noacpi amd_iommu=off noapic` and verify xhci and graphics continue to work. $ cat /proc/interrupts 12: 285064 XT-PIC nvme0q0, nvme0q1, rtw88_pci 13: 100000 XT-PIC xhci-hcd:usb1 14: 4032 XT-PIC amdgpu, xhci-hcd:usb3 Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I1d66ccd08a86a64242dbc909c57ff9685828f61f Reviewed-on: https://review.coreboot.org/c/coreboot/+/52915 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-16mb/google/guybrush: Enable backlight in the OSMartin Roth
Add ACPI code to enable the backlight when we enter the OS. BUG=b:184198808 TEST=Backlight enabled in the OS Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: I3e0a6c06120ac5abf0a0d82494e03d9cf80c1f8c Reviewed-on: https://review.coreboot.org/c/coreboot/+/52113 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-08mb/google/guybrush: Unmask eSPI keyboard IRQRaul E Rangel
PS/2 keyboard used IRQ 1. BUG=none TEST=Boot guybrush and see internal keyboard working Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I97b7382eac28aae2cc82f430c58cf8066b9701e1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52143 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-01mb/google/guybrush: Add IRQ numbersRaul E Rangel
BUG=b:183737011 TEST=cat /proc/interrupts and see i2c controllers and gpio controller listed Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I5b2f23b2c2a7c4cec198276814d80f545e85aa41 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51959 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mathew King <mathewk@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-03-29mb/google/guybrush: select DISABLE_KEYBOARD_RESET_PINFelix Held
Now that we have the DISABLE_KEYBOARD_RESET_PIN Kconfig option, select it and remove the temporary workaround that was implemented in the mainboard code in commit 39ef89033624a2d14b0c77cdbdf287dd7d7059e1. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I634d11290dad8c93f10979f06243b1bf84737ae2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51785 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-03-24mb/google/guybrush: disable KBRSTENKangheui Won
GPIO129 is muxed with KBRST, so setting GPIO129 to low causes reset when KBRSTEN is set to 1. Since reset value of KBRSTEN is 1 we need a logic to clear it. BUG=b:183340503 TEST=build Signed-off-by: Kangheui Won <khwon@chromium.org> Change-Id: I194e8432a14d6105f6bcf12111647f5aad4e2de2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51727 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-03-16mb/google/guybrush: Add initial fch irq routingMathew King
BUG=b:181972598 TEST=builds Signed-off-by: Mathew King <mathewk@chromium.org> Change-Id: I1abb070324254e21b03bfe00d6eee3b70120564c Reviewed-on: https://review.coreboot.org/c/coreboot/+/51473 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-03-10mb/google/guybrush: Enable Chrome ECMathew King
BUG=b:180507937 TEST=builds Signed-off-by: Mathew King <mathewk@chromium.org> Change-Id: I3cdd6422b1bc53ea934346327359cbc6d86baeeb Reviewed-on: https://review.coreboot.org/c/coreboot/+/51043 Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-22mb/google/guybrush: Enable ACPI tablesMathew King
BUG=b:180419454 TEST=builds Signed-off-by: Mathew King <mathewk@chromium.org> Change-Id: I1e724e78b5ef378d474063417aa2b7e57a00886f Reviewed-on: https://review.coreboot.org/c/coreboot/+/50814 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2021-02-06mb/google/guybrush: Add stubs to configure GPIOsMathew King
BUG=b:175143925 TEST=builds Signed-off-by: Mathew King <mathewk@chromium.org> Change-Id: I5afd2df396ba41f7d25fa7ff6879b7c1f82f438c Reviewed-on: https://review.coreboot.org/c/coreboot/+/49954 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-12-17mb/google/guybrush: Add new mainboardMathew King
Guybrush is a new Google mainboard with an AMD SOC. BUG=b:175143925 TEST=builds Change-Id: I1792f21ff7616f364ddc8b0c04481049b2a5fb04 Signed-off-by: Mathew King <mathewk@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48479 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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