coreboot.git - my copy of coreboot

Age	Commit message (Collapse)	Author
2022-12-10	mb/google/guybrush: use gpio.h include	Felix Held
	Replace the amdblocks/gpio.h and soc/gpio.h includes with the common gpio.h which will include soc/gpio.h which will include amdblocks/gpio.h in the AMD SoC case. Since baseboard/ec.h and indirectly baseboard/gpio.h files will get included in the DSDT, the soc/gpio.h includes in those aren't replaced with a gpio.h include for now. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ifa82c10d10e4438b0437b78ddd95b5e823805571 Reviewed-on: https://review.coreboot.org/c/coreboot/+/70435 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-23	soc/amd/common/blocks/include: rename gpio_banks.h to gpio.h	Felix Held
	This brings the AMD SoC GPIO code in line with the Intel SoC code and removes the not really needed suffix. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ie2dbec81dfe503869beb2872b01a7475e2b88b33 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57842 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-04-27	mb/google/guybrush: Fix EC SCI configuration	Raul E Rangel
	This change fixes two problems: 1) We had the enum values for .direction and .level swapped. The naming is very confusing... 2) ESPI_SYS is not a good event to use for EC SCI. It is a level/low event that is only cleared by reading the eSPI status register 0x9C. Cezanne has added a new event source that directly exposes the SCI bit. This is the correct event source to use for EC SCI. BUG=b:186045622, b:181139095 TEST=`lpc sci` on EC console and see /proc/interrupts increase by 1 Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I764b9ec202376d5124331a320767cbf79371dc07 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52673 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-04-15	mb/google/guybrush,mancomb: use EC_SCI_GPI in espi_sci_sources struct	Felix Held
	The board's ec.h file defined EC_SCI_GPI as GEVENT_24, so use that definition in all places in the mainboard code instead of a mix of the board specific define and the SoC's GEVENT number define. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I46525ed24e9993acd3d850959dd63761a690d5df Reviewed-on: https://review.coreboot.org/c/coreboot/+/52309 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-03-15	mb/google/guybrush: Enable eSPI VW SCI events	Mathew King
	Guybrush does not have a dedicated SCI pin so it uses VW. BUG=b:181134664 TEST=builds Signed-off-by: Mathew King <mathewk@chromium.org> Change-Id: I12fb7c23718ad2350478b89b321e9f0aa099e53b Reviewed-on: https://review.coreboot.org/c/coreboot/+/51238 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-10	mb/google/guybrush: Enable Chrome EC	Mathew King
	BUG=b:180507937 TEST=builds Signed-off-by: Mathew King <mathewk@chromium.org> Change-Id: I3cdd6422b1bc53ea934346327359cbc6d86baeeb Reviewed-on: https://review.coreboot.org/c/coreboot/+/51043 Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>