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Anything below 128K will cause SMMSTORE driver in edk2 to fail, since
a minimum of (2) 64K blocks are needed. Increase the size to 256K to
match other boards in the tree.
TEST=build/boot guybrush (dewatt) with SMMSTORE enabled.
Change-Id: Ic4fdacd493d83fa3c1683a06d1276b0190f6db8b
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81866
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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SMMSTOREv2 requires 64k min size, 64k alignment.
TEST=build guybrush with SMMSTOREv2 enabled
Change-Id: I78cb873a5634c659067367260cc7063fbd60d77a
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68123
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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This area relates to storing of AP RO verification information.
CONFIG_VBOOT_GSCVD is enabled by default for TPM_GOOGLE_TI50 and
guybrush is using TPM_GOOGLE_CR50.
Signed PSP verstage has the FMAP embedded. Since CB:67376 shifted the
RO section up by 8K, they were misaligned. Hence marking this area as
unused instead of removing the same to work around ChromeOS
infrastructure shortcoming.
Signed-off-by: Himanshu Sahdev <himanshu.sahdev@intel.com>
Change-Id: Id852e5b5c1f777992a96a75143757f4df8d975b6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67901
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This area relates to storing of AP RO verification information.
CONFIG_VBOOT_GSCVD is enabled by default for TPM_GOOGLE_TI50 and
guybrush is using TPM_GOOGLE_CR50.
Signed-off-by: Himanshu Sahdev <himanshu.sahdev@intel.com>
Change-Id: I896b871bf2ac64e334514b979add9b8ac2c43945
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67376
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-by: Harsha B R <harsha.b.r@intel.com>
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This area is used for storing AP RO verification information.
BRANCH=none
BUG=b:141191727
TEST=built a guybrush firmware image and verified that the RO_GSCVD
area was indeed added:
$ dump_fmap /build/guybrush/firmware/image-guybrush.bin | \
grep -B3 RO_GSCVD
area: 25
area_offset: 0x00808000
area_size: 0x00002000 (8192)
area_name: RO_GSCVD
$
- verified that guybrush device boots fine with the new image.
Change-Id: Ifa24d5a6271a8bcbf737d4580ec85b9cfdd9af01
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57864
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The 448KB size of the GBB is larger than is needed, so adjust it down
to the minimum size needed.
BUG=b:186761897
TEST=Build & Boot guybrush
Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: I7a24945cd9ecc8872871f57b09ca71fc40e92473
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52764
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Guybrush is a new Google mainboard with an AMD SOC.
BUG=b:175143925
TEST=builds
Change-Id: I1792f21ff7616f364ddc8b0c04481049b2a5fb04
Signed-off-by: Mathew King <mathewk@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48479
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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