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Update the memory ramid.
Move to one CA training pattern.
BUG=chrome-os-partner:59454
BRANCH=firmware-gru-8785.B
TEST=Build firmware passed
Change-Id: Ic05cbc1700a13e372f63d5202459add0e984f9d8
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 1030a78af3d489d13508f17a79df1e65bd5afa3b
Original-Change-Id: Ibe8acb5b698cec1adcdddbb13d35a5e20a5b8c0d
Original-Reviewed-on: https://chromium-review.googlesource.com/414664
Original-Commit-Ready: Shasha Zhao <Sarah_Zhao@asus.com>
Original-Tested-by: Shasha Zhao <Sarah_Zhao@asus.com>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Original-Change-Id: I0ae46e496cd18492a2b6c7167081798c2f2479b1
Original-Signed-off-by: Shasha Zhao <Sarah_Zhao@asus.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/411645
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/17679
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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Add bob in coreboot and update as necessary.
1. Add bob HWID
2. Add supported memory source
BUG=chrome-os-partner:59454
BRANCH=firmware-gru-8785.B
TEST=Build firmware passed
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Change-Id: Iad03a293bdbbb89450f0fea0822e34a4be7064bf
Original-Commit-Id: bff788c71a43403bff2c23b38e69cc27fb869559
Original-Change-Id: I0dcf47eb911337b176f73759a2c70a9dbf4dc68b
Original-Signed-off-by: Shasha Zhao <Sarah_Zhao@asus.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/411083
Original-Reviewed-by: Philip Chen <philipchen@chromium.org>
Original-(cherry picked from commit c5925dfcf59ac755a26182744b2bde59e41a37cf)
Original-Reviewed-on: https://chromium-review.googlesource.com/413744
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/17678
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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Several of the special function pins we're using in firmware have a
pre-assigned pull-up or pull-down on power-on reset. We don't want those
to interfere with any of the signaling we're trying to do on those pins,
so this patch disables them.
Also do some house-cleaning to group the bootblock code better, and
change the setup code for all SPI and I2C buses to first initialize the
controller and then mux the pins... I assume this might be a little
safer (in case the controller peripheral has some pins in a weird state
before it gets fully initialized, we don't want to mux it through too
early).
BRANCH=None
BUG=chrome-os-partner:52526
TEST=Booted Kevin.
Change-Id: I4d5bd3f7657b8113d90b65d9571583142ba10a27
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: f8f7fd56e945987eb0b1124b699f676bc68d0560
Original-Change-Id: I6bcf2b9a5dc686f2b6f82bd80fc9a1a245661c47
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/382532
Reviewed-on: https://review.coreboot.org/16711
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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If we setup the PWM _after_ the pinmux then there's a period of time
when we're driving the PWM incorrectly. Let's setup the regulator and
_then_ configure the pinmux.
This fixes no known bugs, but it is more correct and probably makes the
signals look better at bootup.
BRANCH=None
BUG=None
TEST=scope
Change-Id: I311c0eded873b65e0489373e87b88bcdd8e4b806
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: fcf4d0ba29d82cce779c0b25ead36de4a95d97a1
Original-Change-Id: I5124f48d04a18c07bbd2d54bc08ee001c9c7e8d1
Original-Signed-off-by: Douglas Anderson <dianders@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/381592
Original-Reviewed-by: Simon Glass <sjg@google.com>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/16700
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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We did yet another small adjustment to the PWM regulator ranges for
Kevin rev6... this patch reflects that in code. Also rewrite code and
descriptions to indicate that these new ranges are not just for Kevin,
but also planned to be used on Gru rev2 and any future Gru derivatives
(which as I understand it is the plan, right?).
BRANCH=None
BUG=chrome-os-partner:54888
TEST=Booted my rev5, for whatever that's worth...
Change-Id: Id78501453814d0257ee86a05f6dbd6118b719309
Signed-off-by: Martin Roth <martinroth@chromium.org>
Original-Commit-Id: 4e8be3f09ac16c1c9782dee634e5704e0bd6c7f9
Original-Change-Id: I723dc09b9711c7c6d2b3402d012198438309a8ff
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/379921
Original-Reviewed-by: Douglas Anderson <dianders@chromium.org>
Reviewed-on: https://review.coreboot.org/16580
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Before, we calculate the pwm duties for cpu cores and centerlogic by
hand, adding pwm_regulator.c to handle this. The default pwm design
min/max voltage may be different between revs.
With the pwm regulator, this patch changes the little cpu frequency from
600M to 1512M, and raises CPU voltage to 1.2V correspondingly.
This also means we decide to drop the ES1 because it may fail to
bootup with 1.5G ~ 1.2v.
BRANCH=none
BUG=chrome-os-partner:54376,chrome-os-partner:54862
TEST=Bootup on kevin board
Change-Id: Id04c176bddfb9cdf3d25b65736e40249a85f6aa1
Signed-off-by: Martin Roth <martinroth@chromium.org>
Original-Commit-Id: ee4365c787ec523b7ee1028ea100dcfbb331b3a9
Original-Change-Id: Ide75bbd92d1cbb14f934baeec0e38862bc08402b
Original-Signed-off-by: Eric Gao <eric.gao@rock-chips.com>
Original-Signed-off-by: Shunqian Zheng <zhengsq@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/364410
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/16368
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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