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path: root/src/mainboard/google/gru/mainboard.c
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2016-06-21rockchip: gru: pass poweroff gpio parameter to BL31Lin Huang
To support gpio power off SOC, we need to pass the power off gpio parameter to BL31. Gru reuse tsadc overtemp pin as power off gpio, so need to iomux to gpio function when use gpio power off function, either in bl31 or depthcharge. BRANCH=None BUG=chrome-os-partner:53448 TEST=Build gru Change-Id: Ibfe64042f39f6df1b87536b50fe432859bf74426 Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: Original-Change-Id: Ie7a1bbea4a12753f0abac7a9142f2e032686ce31 Original-Signed-off-by: Lin Huang <hl@rock-chips.com> Original-Signed-off-by: Douglas Anderson <dianders@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/349703 Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://review.coreboot.org/15119 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-06-21rockchip: gru: pass reset gpio parameter to BL31Lin Huang
To support gpio reset SOC, we need to pass the reset gpio parameter to BL31. Note: request BL31 have supported this function. BRANCH=None BUG=chrome-os-partner:51924 TEST=Build gru Change-Id: I182cff11ce6f5dc3354db0dc053c128b813acf9f Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: Original-Change-Id: I8283596565d552b1f3db31c28621a1601c226999 Original-Signed-off-by: Lin Huang <hl@rock-chips.com> Original-Signed-off-by: Douglas Anderson <dianders@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/349702 Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://review.coreboot.org/15118 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins)
2016-06-12rockchip: gru: Add USB DRD DWC3 controller supportLiangfeng Wu
This patch adds code to initialize the two DWC3 USB host controllers, and uses them to initialize USB3.0 on the gru rk3399 board. BRANCH=none BUG=chrome-os-partner:52684 TEST=boot from USB3.0 on gru/kevin rk3399 platform Change-Id: If6a6e56f3a7c7ce8e8b098634cfc2f250a91810d Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: 0306a9e Original-Change-Id: I796fa1133510876f75873d134ea752e1b52e40a8 Original-Signed-off-by: Liangfeng Wu <wulf@rock-chips.com> Original-Signed-off-by: Douglas Anderson <dianders@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/347524 Original-Commit-Ready: Brian Norris <briannorris@chromium.org> Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/15112 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-06-08rockchip: rk3399: Add support i2sXing Zheng
This patch enable and configure the clocks and IOMUX for i2s audio path, and the i2s0 clock is from CPLL. Please refer to TRM V0.3 Part 1 Chapter 3 CRU, P126/P128/P144/P154/P155 for the i2s clock div and gate setting. BRANCH=none BUG=chrome-os-partner:52172 TEST=boot kevin rev1, press ctrl+u and hear the beep voice. Change-Id: Id00baac965c8b9213270ba5516e1ca684e4304a6 Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: 9c58fa7 Original-Change-Id: I130a874a0400712317e5e7a8b3b10a6f04586f68 Original-Signed-off-by: Xing Zheng <zhengxing@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/347526 Original-Commit-Ready: Wonjoon Lee <woojoo.lee@samsung.com> Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://review.coreboot.org/15034 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-06-08gru: kevin: define GPIOs used on both platformsVadim Bendebury
The same GPIOs are used on both platforms, definitions are added an a new .h to make it easier to re-use them across the code. BRANCH=none BUG=chrome-os-partner:51537 TEST=panel backlight still enabled on Gru as before. The rest of the GPIOs are used in the upcoming patches. Change-Id: If06f4b33720ab4bf098d23fb91322bba23fe6e90 Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: c587880 Original-Change-Id: I1a6c5b5beb82ffcc5fea397e8e9ec2f183f4a7e0 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/346219 Original-Tested-by: Shunqian Zheng <zhengsq@rock-chips.com> Reviewed-on: https://review.coreboot.org/15029 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-06-03rockchip: gru: enable eDP displayLin Huang
This patch enables eDP display by: o. setting HPD pinmux, backlight, vdd for eDP o. setting vop mode o. enabling VGA configs for edid BRANCH=none BUG=chrome-os-partner:51537 TEST=The dev screen is shown on kevin board Change-Id: If8b07307454daa88727d317cc208d6c97de07ad7 Signed-off-by: Martin Roth <martinroth@google.com> Original-Commit-Id: b1ad9337510f5437f691153dc68883edf273e4c7 Original-Change-Id: Id7006619b5be638b286a5402d892a5361ac1e430 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/340026 Original-Reviewed-by: Shunqian Zheng <zhengsq@rock-chips.com> Reviewed-on: https://review.coreboot.org/14858 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-05-18rockchip: rk3399: enable sdhci clk for emmcShunqian Zheng
If booting from sdcard/usb, kernel can't recognize the /dev/mmcblk0. Before kernel find it's root cause, we add this workaround patch to enable clk for emmc. BRANCH=none BUG=chrome-os-partner:52873 TEST=boot from sdcard and check the /dev/mmcblk0 exists Change-Id: Ie36cc6fdbc24db8c30984c02ccfe2f8aaaf30cd2 Signed-off-by: Martin Roth <martinroth@google.com> Original-Commit-Id: 39b87ec3c73d6f56efc8c3f52b7ed759e548ee85 Original-Change-Id: I88a9cc2e3ea5a56aadfdbd94ef910daaf92a7eb7 Original-Signed-off-by: Shunqian Zheng <zhengsq@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/341632 Original-Commit-Ready: Vadim Bendebury <vbendeb@chromium.org> Original-Tested-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://review.coreboot.org/14856 Tested-by: build bot (Jenkins) Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
2016-05-18rockchip: rk3399: configure emmc clkLin Huang
Select aclk_emmc and clk_emmc source from GPLL, and both to 198MHz, that is GPLL(594MHz) divided by 3. BRANCH=none BUG=chrome-os-partner:51537 TEST=boot kevin rev1 to chromeos prompt from both emmc and sdcard TEST=LoadKernel faster, more than twice as I measured manually. Change-Id: I2580c43b8c79049c3fe16bbf60bfa1a8e0559948 Signed-off-by: Martin Roth <martinroth@google.com> Original-Commit-Id: 5fd37b66dcce77354e1cafab0d6e806d832c08d2 Original-Change-Id: Id22815b302af3204e0e5537af99c1577b09b0877 Original-Signed-off-by: Lin Huang <hl@rock-chips.com> Original-Signed-off-by: Shunqian Zheng <zhengsq@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/339152 Original-Commit-Ready: Vadim Bendebury <vbendeb@chromium.org> Original-Tested-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://review.coreboot.org/14855 Tested-by: build bot (Jenkins) Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
2016-05-18rk3399: set proper configuration of SDMMC interfaceVadim Bendebury
For proper interface operation the drive strength on all pins is set to 8 mA and all pull ups/pull downs disabled, this matches the current kernel configuration. BRANCH=none BUG=chrome-os-partner:53257 TEST=it is possible to boot Chrome OS on Gru from various micro SD cards which were failing to boot before. Change-Id: Ie43e52a52cd0513d48d0ecc8ac02fbb100baf9a4 Signed-off-by: Martin Roth <martinroth@google.com> Original-Commit-Id: 6bb0549ed728ac3c5faab6cbe16e2487400e67ed Original-Change-Id: I5180537d3ceb74a9a2f7b3982ca94d3e2daf0369 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/344491 Original-Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/14853 Tested-by: build bot (Jenkins) Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
2016-05-18gru: set correct gpio for SD card detectVadim Bendebury
The only outlier at this time is Kevin rev 0, treat it specially, the rest of the targets use the same GPIO. BRANCH=none BUG=none TEST=gru still boots off SD card just fine Change-Id: Ic603093a990d27166b16175db3303f155b4775aa Signed-off-by: Martin Roth <martinroth@google.com> Original-Commit-Id: 5788c5add1d1f803e7b22fb53215b6003ac04d03 Original-Change-Id: Ic5183f08dd1119f9588f243bd9e9c080d84687f9 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/344151 Original-Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/14851 Tested-by: build bot (Jenkins) Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
2016-05-09google/gru: kevin: use board version specific SD detect GPIO pinVadim Bendebury
This change reflects Kevin schematics differences, Gru will have to be addressed separately. BRANCH=None BUG=None TEST=the code still works fine on Kevin proto 1. Change-Id: Iecae0e82e6bd4d185b49587b6053dcef8ad2162d Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: e821bbebe902a293b1e78cdd868f6bf3548ddd30 Original-Change-Id: Icd606285aeca1e19189f5e3d24c09b376942708b Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/340429 Original-Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: https://review.coreboot.org/14728 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-05-09google/gru: power up SD cardVadim Bendebury
Make sure SD card is powered up properly. Please refer to TRM V0.3 Part1 Page 324 for sdmmc pinmux. BRANCH=none BUG=chrome-os-partner:51537 TEST=With other patches, boot into chromeos prompt Change-Id: Ib53b05c1fce851ca7cbcc2207fce2dce3b1bfe9a Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: d37e688a458749e331a50c2ebf2018cba6629823 Original-Change-Id: I9f67c0bc16ddefa5ebe52a10c6d9e54194828a89 Original-Signed-off-by: Lin Huang <hl@rock-chips.com> Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/337192 Reviewed-on: https://review.coreboot.org/14718 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-04-16google/gru: Incorporate feedback to #14279Patrick Georgi
To avoid diverging too much on an actively developed code base, keep the changes to a separate commit that can be downstreamed more easily: - removed unused includes - gave kevin board a "Kevin" part number - marked RW_LEGACY as CBFS region (to follow up upstream changes) - moved romstage entry point to SoC code (instead of encouraging per-board copy pasta) Change-Id: Ief0c8db3c4af96fe2be2e2397d8874ad06fb6f1f Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/14362 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-04-16google/gru: Add a stub rk3399 mainboardhuang lin
Most things still need to be filled in, but this will allow us to build boards which use this SOC. [pg: separated out from the combined commit that added both SoC and board. Added board_info.txt that will be added downstream, too.] Change-Id: I7facce7b98a5d19fb77746b1aee67fff74da8150 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 27dfc39efe95025be2271e2e00e9df93b7907840 Original-Change-Id: I6f2407ff578dcd3d0daed86dd03d8f5f4edcac53 Original-Signed-off-by: huang lin <hl@rock-chips.com> Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/332385 Reviewed-on: https://review.coreboot.org/14279 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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