coreboot.git - my copy of coreboot

Age	Commit message (Expand)	Author
2017-09-06	google/gru: Re-enable 3V rail GPIO on Scarlet	Julius Werner
2017-08-06	rockchip: gpio: add gpio_pull argument in gpio_input_irq() function	Lin Huang
2017-08-01	google/gru: Use 1.8V powerdomain for gpio4cd on Scarlet	Lin Huang
2017-07-19	google/gru: Add support for Scarlet rev1	Julius Werner
2017-04-28	google/gru: tpm on bob: cr50: add irq clear/irq status for tpm irq	Jeffy Chen
2016-10-06	rockchip/rk3399: Move big CPU cluster initialization into ramstage	Julius Werner
2016-10-04	google/gru: Ensure correct pull resistors for special-function pins	Julius Werner
2016-10-04	gru: Increase SPI speed to 33MHz	Simon Glass
2016-09-20	gru/kevin: Decrease voltage for little cpu 1.5G to 1.15v	Shunqian Zheng
2016-09-20	gru: Add watchdog reset support	Julius Werner
2016-08-31	rockchip/rk3399: Add pwm_regulator.c for pwm then ramp boot up cpu	Eric Gao
2016-08-18	Kconfig: rename BOOT_MEDIA_SPI_BUS to BOOT_DEVICE_SPI_FLASH_BUS	Aaron Durbin
2016-08-03	google/gru: Add code to support I2C TPM for Kevin	Julius Werner
2016-07-25	google/gru: Change UART _Static_assert() condition to #if	Julius Werner
2016-06-23	gru: kevin: initialize cr50 SPI interface	Vadim Bendebury
2016-06-08	gru: kevin: enable EC SPI interface	Vadim Bendebury
2016-06-08	gru: kevin: configure board GPIOs	Vadim Bendebury
2016-05-09	google/gru: enable pp1500 and pp3000 rails as soon as possible	Vadim Bendebury
2016-05-09	google/gru: select 1.8V as gpio2ab io domain	Lin Huang
2016-05-09	rockchip: rk3399: add spi clock driver	Shunqian Zheng
2016-05-09	google/gru: enable uart2 if configured	Shunqian Zheng
2016-04-16	google/gru: Add a stub rk3399 mainboard	huang lin