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2018-05-08mb/google: Get rid of device_tElyes HAOUAS
Use of device_t has been abandoned in ramstage. Change-Id: I8e549e4222ae2ed6b9c46f81c5b5253e8b227ee8 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26086 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-03-28soc/intel/skylake: Limit xDCI feature when VBOOT is enabledDuncan Laurie
Use the common xDCI function to check if the controller is allowed in the current mode before enabling it. Otherwise, disable the PCI device if it has been enabled in devicetree. To make the SOC behavior consistent the XdciEnable config option is removed in favor of direct control by devicetree.cb and the mainboards that had defined it were adjusted accordingly. This was tested on an Eve board with xDCI enabled in devicetree.cb to ensure the xDCI device is enabled in developer mode and disabled in normal mode. Change-Id: Ic3c84beac87452f17490de32082030880834501d Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/25365 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-01-26mb/*/*/cmos.layout: Fix the values for the console levelArthur Heymans
Fix the values that were off by one. This was discovered when using postcar stage that prints with debuglevel BIOS_NEVER. Change-Id: I73a077950ed0dc735d89c9747a8da0a25f30822d Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/23186 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-12-07boardid: Switch from Kconfig to weak functionsJulius Werner
This patch switches the board_id and ram_code helper framework to use weak functions rather than Kconfigs to determine whether the board supplies these IDs. This cuts down on the amount of boilerplate Kconfigs many boards have to set and also gives them more flexibility, such as being able to determine at runtime whether a given ID is present. Change-Id: I97d6d1103ebb2a2a7cf1ecfc45709c7e8c1a5cb0 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/22695 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-11-23google mainboards: select SYSTEM_TYPE_LAPTOP where appropriateMatt DeVillier
Some Google boards are missing this selection, leading them to being incorrectly identified as type 'Desktop' in SMBIOS type 3 table. Correct this by adding 'select SYSTEM_TYPE_LAPTOP' to the boards' Kconfigs. TEST: boot Linux and check correct chassis type listed via dmidecode Change-Id: Ib1145e314812a3f300cfd1a435a687aa0862158a Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/22340 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-23src/mainboard: Fix various typosJonathan Neuschäfer
These typos were found through manual review and grep. Change-Id: Ia5a9acae4fbe2627017743106d9326a14c99a225 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/22525 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-10-09skylake mainboards: Use PAD_CFG_GPI_GPIO_DRIVER instead of PAD_CFG_GPIFurquan Shaikh
Change 1760cd3e (soc/intel/skylake: Use common/block/gpio) updated all skylake boards to use common gpio driver. Common gpio code defines PAD_CFG_GPI without GPIO_DRIVER ownership. However, for skylake PAD_CFG_GPI set GPIO_DRIVER ownership by default. This resulted in Linux kernel failing to configure all GPIO IRQs since the ownership was not set correctly. (Observed error in dmesg: "genirq: Setting trigger mode 3 for irq 201 failed (intel_gpio_irq_type+0x0/0x110)") This change fixes the above issue by replacing all uses of PAD_CFG_GPI in skylake mainboards to PAD_CFG_GPI_GPIO_DRIVER. BUG=b:67507004 TEST=Verified on soraka that the genirq error is no longer observed in dmesg. Also, cat /proc/interrupts has the interrupts configured correctly. Change-Id: I7dab302f372e56864432100a56462b92d43060ee Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/21912 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-08ec/google/chromeec: Add library function google_chromeec_events_initFurquan Shaikh
mainboard_ec_init implemented by all x86-based mainboards using chromeec performed similar tasks for initializing and recording ec events. Instead of duplicating this code across multiple boards, provide a library function google_chromeec_events_init that can be called by mainboard with appropriate inputs to perform the required actions. This change also adds a new structure google_chromeec_event_info to allow mainboards to provide information required by the library function to handle different event masks. Also, google_chromeec_log_device_events and google_chromeec_log_events no longer need to be exported. Change-Id: I1cbc24e3e1a31aed35d8527f90ed16ed15ccaa86 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/21877 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2017-09-26mb/google/*: Use newly added Chrome EC boardid functionFurquan Shaikh
Instead of duplicating code across multiple mainboards, use newly added helper function to read boardid from Chrome EC. Change-Id: I1671c0a0b87d0c4c45da5340e8f17a4a798317ca Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/21682 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-23mb/*/*: Remove rtc nvram configurable baud rateArthur Heymans
There have been discussions about removing this since it does not seem to be used much and only creates troubles for boards without defaults, not to mention that it was configurable on many boards that do not even feature uart. It is still possible to configure the baudrate through the Kconfig option. Change-Id: I71698d9b188eeac73670b18b757dff5fcea0df41 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/19682 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-08-25soc/intel/skylake: Add LPC and SPI lock down config optionSubrata Banik
This patch to provide new config options to perform LPC and SPI lock down either by FSP or coreboot. Remove EISS bit programming as well. TEST=Build and boot Eve and Poppy. Change-Id: If174915b4d0c581f36b54b2b8cd970a93c6454bc Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/21068 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-01mainboards: Remove unused EC event for thermal overloadDuncan Laurie
The Chrome EC event for "thermal overload" was never implemented and is being repurposed as the EC event mask is out of free bits. Remove this from the boards that were enabling it. BUG=b:36024430 TEST=build coreboot for affected boards Change-Id: I6038389ad73cef8a57aec5041bbb9dea98ed2b6e Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/20424 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-06-02mainboard/*/*/Kconfig: Remove MONOTONIC_TIMER_MSR selectionAamir Bohra
Remove MONOTONIC_TIMER_MSR selection from mainboard Konfigs, as it only does a reduntant selection of HAVE_MONOTONIC_TIMER config, already selected under skylake soc Kconfig. Change-Id: Ib3177ceb9e8b6c16ce0e437a4a02b94f215af58f Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/20002 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
2017-04-24*.asl: Remove obsolete reference to TPM ASL filePatrick Rudolph
TPM ACPI entries are automatically generated, and the old static TPM ASL file is obsolete. Remove the reference to this obsolete static and empty ASL file. Delete src/drivers/pc80/tpm/acpi/tpm.asl. Change-Id: I6163e6d59c53117ecbbbb0a6838101abb468de36 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/19291 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-04-13soc/intel/skylake: Split AC/DC settings for Deep Sx configDuncan Laurie
Currently when enabling Deep S3 or Deep S5 it unconditionally gets enabled in both DC and AC states. However since using Deep S3 disables some expected features like wake-on-USB it is not always desired to enable the same state in both modes. To address this split the setting and add a separate config for Deep Sx in AC and DC states. All motherboards that set this config were updated, but there is no actual change in behavior in this commit. BUG=b:36723679 BRANCH=none TEST=This commit has no runtime visible changes, I verified on Eve that the Deep SX config registers are unchanged, and it compiles for all affected boards. Change-Id: I590f145847785b5a7687f235304e988888fcea8a Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/19239 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-03-28vboot: Move remaining features out of vendorcode/google/chromeosJulius Werner
This patch attempts to finish the separation between CONFIG_VBOOT and CONFIG_CHROMEOS by moving the remaining options and code (including image generation code for things like FWID and GBB flags, which are intrinsic to vboot itself) from src/vendorcode/google/chromeos to src/vboot. Also taking this opportunity to namespace all VBOOT Kconfig options, and clean up menuconfig visibility for them (i.e. some options were visible even though they were tied to the hardware while others were invisible even though it might make sense to change them). CQ-DEPEND=CL:459088 Change-Id: I3e2e31150ebf5a96b6fe507ebeb53a41ecf88122 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/18984 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-28vboot: Assume EC_SOFTWARE_SYNC and VIRTUAL_DEV_SWITCH by defaultJulius Werner
The virtualized developer switch was invented five years ago and has been used on every vboot system ever since. We shouldn't need to specify it again and again for every new board. This patch flips the Kconfig logic around and replaces CONFIG_VIRTUAL_DEV_SWITCH with CONFIG_PHYSICAL_DEV_SWITCH, so that only a few ancient boards need to set it and it fits better with CONFIG_PHYSICAL_REC_SWITCH. (Also set the latter for Lumpy which seems to have been omitted incorrectly, and hide it from menuconfig since it's a hardware parameter that shouldn't be configurable.) Since almost all our developer switches are virtual, it doesn't make sense for every board to pass a non-existent or non-functional developer mode switch in the coreboot tables, so let's get rid of that. It's also dangerously confusing for many boards to define a get_developer_mode() function that reads an actual pin (often from a debug header) which will not be honored by coreboot because CONFIG_PHYSICAL_DEV_SWITCH isn't set. Therefore, this patch removes all those non-functional instances of that function. In the future, either the board has a physical dev switch and must define it, or it doesn't and must not. In a similar sense (and since I'm touching so many board configs anyway), it's annoying that we have to keep selecting EC_SOFTWARE_SYNC. Instead, it should just be assumed by default whenever a Chrome EC is present in the system. This way, it can also still be overridden by menuconfig. CQ-DEPEND=CL:459701 Change-Id: If9cbaa7df530580a97f00ef238e3d9a8a86a4a7f Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/18980 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-27ec: Use EC_ENABLE_LID_SWITCH for all mainboards with LID using chromeecFurquan Shaikh
Instead of defining a separate LID device for mainboards using chromeec, define EC_ENABLE_LID_SWITCH for these boards. Change-Id: Iac58847c2055fa27c19d02b2dbda6813d6dec3ec Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/18964 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-02-22acpi: Add ACPI_ prefix to IRQ enum and struct namesFurquan Shaikh
This is done to avoid any conflicts with same IRQ enums defined by other drivers. BUG=None BRANCH=None TEST=Compiles successfully Change-Id: I539831d853286ca45f6c36c3812a6fa9602df24c Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/18444 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-02-20mainboard/{google,intel}: Change config option selectionFurquan Shaikh
Change config option selection from "config xyz default y" to "select xyz" if the config option has no dependencies. BUG=None BRANCH=None TEST=Verified that config option selection remains unchanged. Change-Id: I259ae40623b7f4d5589e2caa0988419ba4fefda4 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/18400 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-12-05mainboard & southbridge: Clear files that are just headersMartin Roth
These headers & comments indicating a lack of functionality don't help anything. We discourage copyrights and licenses on empty files, so just clear these. Change-Id: Id2ab060a2726cac6ab047d49a6e6b153f52ffe6d Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/17657 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-11-28soc/intel/skylake: Add USB Port Over Current (OC) Pin programmingSubrata Banik
Program USB Overcurrent pins as per board schematics definition. BUG=none BRANCH=none TEST=Build and boot kunimitsu from USB device. Change-Id: I6aeb65953c753e09ad639469de7d866a54f42f11 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/17570 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-11-22Remove explicit select MMCONF_SUPPORTKyösti Mälkki
Make MMCONF_SUPPORT selected with MMCONF_SUPPORT_DEFAULT. Platforms that remain to have explicit MMCONF_SUPPORT are ones that should be converted. Change-Id: Iba8824f46842607fb1508aa7d057f8cbf1cd6397 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17527 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-18google/chromeec: Add common infrastructure for boot-mode switchesFurquan Shaikh
Instead of defining the same functions for reading/clearing boot-mode switches from EC in every mainboard, add a common infrastructure to enable common functions for handling boot-mode switches if GOOGLE_CHROMEEC is being used. Only boards that were not moved to this new infrastructure are those that do not use GOOGLE_CHROMEEC or which rely on some mainboard specific mechanism for reading boot-mode switches. BUG=None BRANCH=None TEST=abuild compiles all boards successfully with and without ChromeOS option. Change-Id: I267aadea9e616464563df04b51a668b877f0d578 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/17449 Tested-by: build bot (Jenkins) Reviewed-by: Julius Werner <jwerner@chromium.org>
2016-11-11soc/intel/skylake: move i2c voltage config to own variableAaron Durbin
In preparation of merging the lpss i2c config structures on apollolake and skylake move the i2c voltage variable to its own field. It makes refactoring things easier, and then there's no reason for a separate SoC specific i2c config structure. BUG=chrome-os-partner:58889 Change-Id: Ibcc3cba9bac3b5779351b673bc0cc7671d127f24 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/17347 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-10-27skylake: Use COMMON_FADTDuncan Laurie
Remove the FADT from the individual mainboards and select and use COMMON_FADT in the SOC instead. Set the ACPI revision to 5. Change-Id: Ieb87c467c71bc125f80c7d941486c2fbc9cd4020 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/17138 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-09-26mainboards,ec: provide common declaration for mainboard_ec_init()Aaron Durbin
Add a header file to provide common declarations that the mainboards can use regarding EC init. BUG=chrome-os-partner:56677 Change-Id: Iaa0b37eff4de644e969a18364713b90b7f27fa1c Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/16734 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins)
2016-08-25vboot: consolidate google_chromeec_early_init() callsAaron Durbin
On x86 platforms, google_chromeec_early_init() is used to put the EC into RO mode when there's a recovery request. This is to avoid training memory multiple times when the recovery request is through an EC host event while the EC is running RW code. Under that condition the EC will be reset (along with the rest of the system) when the kernel verification happens. This leads to an execessively long recovery path because of the double reboot performing full memory training each time. By putting this logic into the verstage program this reduces the bootblock size on the skylake boards. Additionally, this provides the the correct logic for all future boards since it's not tied to FSP nor the mainboard itself. Lastly, this double memory training protection works only for platforms which verify starting from bootblock. The platforms which don't start verifying until after romstage need to have their own calls (such as haswell and baytrail). Change-Id: Ia8385dfc136b09fb20bd3519f3cc621e540b11a5 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/16318 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-08-18Kconfig: rename BOOT_MEDIA_SPI_BUS to BOOT_DEVICE_SPI_FLASH_BUSAaron Durbin
Provide a default value of 0 in drivers/spi as there weren't default values aside from specific mainboards and arch/x86. Remove any default 0 values while noting to keep the option's default to 0. BUG=chrome-os-partner:56151 Change-Id: If9ef585e011a46b5cd152a03e41d545b36355a61 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/16192 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Martin Roth <martinroth@google.com>
2016-08-17mainboard: Clean up boot_option/reboot_bits in cmos.layoutNico Huber
Since commit 3bfd7cc (drivers/pc80: Rework normal / fallback selector code) the reboot counter stored in `reboot_bits` isn't reset on a reboot with `boot_option = 1` any more. Hence, with SKIP_MAX_REBOOT_CNT_CLEAR enabled, later stages (e.g. payload, OS) have to clear the counter too, when they want to switch to normal boot. So change the bits to (h)ex instead of (r)eserved. To clarify their meaning, rename `reboot_bits` to `reboot_counter`. Also remove all occurences of the obsolete `last_boot` bit that have sneaked in again since 24391321 (mainboard: Remove last_boot NVRAM option). Change-Id: Ib3fc38115ce951b75374e0d1347798b23db7243c Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/16157 Tested-by: build bot (Jenkins) Reviewed-by: Timothy Pearson <tpearson@raptorengineering.com> Reviewed-by: York Yang <york.yang@intel.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-08-14src/mainboard: Capitalize ROM, RAM, CPU and APICElyes HAOUAS
Change-Id: Ia1f24d328a065a54975adde067df36c5751bff2d Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/15987 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-08-08skylake/devicetree: Add PIRQ Routing programmingBarnali Sarkar
Program PIRQ Routing with correct values, as done by FSP, and also in 'soc/intel/skylake/romstage/pch.c' file. If not done, these values get overridden by "0" during PxRC -> PIRQ programming in ramstage, in 'soc/intel/skylake/lpc.c' file pch_pirq_init()function. BUG=none BRANCH=none TEST=Build and boot kunimitsu Change-Id: Ibeb9a64824a71c253e45d6a1c6088abd737cf046 Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Reviewed-on: https://review.coreboot.org/16044 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2016-07-31Remove extra newlines from the end of all coreboot files.Martin Roth
This removes the newlines from all files found by the new int-015-final-newlines script. Change-Id: I65b6d5b403fe3fa30b7ac11958cc0f9880704ed7 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/15975 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-07-31intel/wifi: Include conditionally in the buildKyösti Mälkki
Keep this enabled by default as most x86 platforms could have PCI-e slots equipped with one of these Intel WiFi adapters. The Kconfig entries under google boards had no function previously, the variable was never referenced. Change-Id: I728ce3fd83d51d4e5e32b848a2079c5fcee29349 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/15931 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-07-30chromeos mainboards: remove chromeos.aslAaron Durbin
Use the ACPI generator for creating the Chrome OS gpio package. Each mainboard has its own list of Chrome OS gpios that are fed into a helper to generate the ACPI external OIPG package. Additionally, the common chromeos.asl is now conditionally included based on CONFIG_CHROMEOS. Change-Id: I1d3d951964374a9d43521879d4c265fa513920d2 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15909 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-07-28skylake/devicetree: Add LPC EC decode rangeSubrata Banik
Define LPC decode ranges for EC communication. BUG=chrome-os-partner:55357 BRANCH=none TEST=Built and boot kunimitsu to ensure no EC timeout error Change-Id: Idefdd79e67e89a794195c6821fee16550d1eda53 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/15898 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-28skylake/mainboard: Define mainboard hook in bootblockSubrata Banik
Move mainboard post console init functionality (google_chrome_ec_init & early_gpio programming) from verstage to bootblock. Add chromeos-ec support in bootblock BUG=chrome-os-partner:55357 BRANCH=none TEST=Built and boot kunimitsu till POST code 0x34 Change-Id: I1b912985a0234d103dcf025b1a88094e639d197d Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/15786 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-25skylake: Move CHROMEOS config to SoCFurquan Shaikh
All the mainboards share the same config options for CHROMEOS. Instead of duplicating those in every mainboard, move the CHROMEOS config to SoC and make it dependent on MAINBOARD_HAS_CHROMEOS. BUG=chrome-os-partner:55431 Change-Id: Iafabb6373dfe16aaf0fe2cbc4e978952adeb403e Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/15822 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-07-15mainboards/skylake: use common Chrome EC SMI helpersAaron Durbin
Reduce duplicate code by using the Chrome EC SMI helper functions. BUG=chrome-os-partner:54977 Change-Id: Ie83e93db514aa0e12e71d371d7afab34a70797fd Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15689 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-07-15mainboards: align on using ACPI_Sx definitionsAaron Durbin
The mainboard_smi_sleep() function takes ACPI sleep values of the form S3=3, S4=4, S5=5, etc. All the chipsets ensure that whatever hardware PM1 control register values are used the interface to the mainboard is the same. Move all the SMI handlers in the mainboard directory to not open code the literal values 3 and 5 for ACPI_S3 and ACPI_S5. There were a few notable exceptions where the code was attempting to use the hardware values and not the common translated values. The few users of SLEEP_STATE_X were updated to align with ACPI_SX as those defines are already equal. The removal of SLEEP_STATE_X defines is forthcoming in a subsequent patch. BUG=chrome-os-partner:54977 Change-Id: I76592c9107778cce5995e5af764760453f54dc50 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15664 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-06-24google/glados: Move devices from mainboard.asl to devicetreeDuncan Laurie
Declare the mainboard attached devices in the devicetree and enable the provided device drivers by default to generate the ACPI objects for these devices. Then remove the static ACPI objects from the DSDT in mainboard.asl. This was verified on a glados board by verifying the SSDT contents against what used to be in the DSDT. Change-Id: I710cbb8462d0fe695297102a64bec8e4212acc65 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/15315 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-06-09skylake: Move I2C bus configuration to separate structureDuncan Laurie
Move the existing I2C voltage configuration variable into a new structure that is equivalent, similar to how USB ports are configured. This is to make room for additional I2C configuration options like bus speed and whether to enable the bus in early boot which are coming in a subsequent commit. The affected mainboards are updated in this commit so it will build. Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Change-Id: Id2dea3df93e49000d60ddc66eb35d06cca6dd47e Reviewed-on: https://review.coreboot.org/15104 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-06-09skylake: gpio: Add support for setting 1.8V tolerantDuncan Laurie
Add the voltage tolerance GPIO attribute for configuring I2C/I2S buses that are at 1.8V. This is currently done by passing in a value to FSP but it is needed earlier than FSP if the I2C bus is used in verstage. This does not remove the need for the FSP input parameter, that is still required so FSP doesn't disable what has been set in coreboot. The mainboards that are affected are updated in this commit. This was tested by exercising I2C transactions to the 1.8V codec while in verstage on the google/chell mainboard. Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Change-Id: I93d22c2e3bc0617c87f03c37a8746e22a112cc9c Reviewed-on: https://review.coreboot.org/15103 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-05-18ec/google/chromeec/acpi: Add MKBP supportGwendal Grignou
Allow EC to send an interrupt using ACPI SMI when a MKBP event is available. This will be used by the sensor stack. Update all ACPI branch except those without sensors with: for i in $(find . -name ec.h -exec grep -l MAINBOARD_EC_SCI_EVENTS {} \+ | cut -d '/' -f 2 | grep -v -e cyan -e lars); do echo $i cd $i git diff ../lars/ec.h | patch -p 5 cd - done BUG=b:27849483 BRANCH=none TEST=Compile on Samus. Tested in Cyan branch. Change-Id: I4766d1d56c3b075bb2990b6d6f59b28c91415776 Signed-off-by: Martin Roth <martinroth@google.com> Original-Commit-Id: d3b9f76a26397ff619f630c5e3d043a7be1a5890 Original-Change-Id: I56c46ee17baee109b9b778982ab35542084cbd69 Original-Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/342364 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/14854 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@google.com>
2016-04-05chromeos.fmd: Mark RW_LEGACY as CBFSPatrick Georgi
Change the existing chromeos.fmd files and the dts-to-fmd script to mark RW_LEGACY as CBFS, so it's properly "formatted". BUG=chromium:595715 BRANCH=none TEST=none Change-Id: I76de26032ea8da0c7755a76a01e7bea9cfaebe23 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 717a00c459906fa87f61314ea4541c31b50539f4 Original-Change-Id: I4b037b60d10be3da824c6baecabfd244eec2cdac Original-Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/336403 Original-Commit-Ready: Patrick Georgi <pgeorgi@chromium.org> Original-Tested-by: Patrick Georgi <pgeorgi@chromium.org> Original-Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/14240 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-04-05chromeos: Simplify fill_lb_gpios even furtherJulius Werner
A long time ago many Chrome OS boards had pages full of duplicated boilerplate code for the fill_lb_gpios() function, and we spent a lot of time bikeshedding a proper solution that passes a table of lb_gpio structs which can be concisely written with a static struct initializer in http://crosreview.com/234648. Unfortunately we never really finished that patch and in the mean time a different solution using the fill_lb_gpio() helper got standardized onto most boards. Still, that solution is not quite as clean and concise as the one we had already designed, and it also wasn't applied consistently to all recent boards (causing more boards with bad code to get added afterwards). This patch switches all boards newer than Link to the better solution and also adds some nicer debug output for the GPIOs while I'm there. If more boards need to be converted from fill_lb_gpio() to this model later (e.g. from a branch), it's quite easy to do with: s/fill_lb_gpio(gpio++,\n\?\s*\([^,]*\),\n\?\s*\([^,]*\),\n\?\s*\([^,]*\),\n\?\s*\([^,]*\));/\t{\1, \2, \4, \3},/ Based on a patch by Furquan Shaikh <furquan@google.com>. BUG=None BRANCH=None TEST=Booted on Oak. Ran abuild -x. Change-Id: I449974d1c75c8ed187f5e10935495b2f03725811 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/14226 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2016-03-25google/intel mainboards: Add missing board_info.txt filesMartin Roth
The lint script didn't catch that these mainboard directories didn't have board_info files. Add all missing board_info.txt files Change-Id: Ib1d61a3c04e91b22480527885faf60c22093d98a Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/14117 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins)
2016-03-12glados/chell: send an extra VR mailbox commandRizwan Qureshi
MPS IMVP8 VR is not entering PS4 in S0ix on Glados/Chell. The pcode has been updated since v76, and it requires an an extra VR mailbox command should be sent from coreboot to pcode. BUG=chrome-os-partner:48511 BRANCH=None TEST=Verified on glados, clean S0ix entry and exit. IMVP8 power is also pretty low CQ-DEPEND=CL:329393 Change-Id: Ia3ef4031269ac2d4557bba65de34c41a8d73f89a Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 3e66903c9017f9d3f45c97b68284f4e1058c03e2 Original-Change-Id: Ie9e370556bb35d02f6bfcfe5cb81dd977fceace1 Original-Signed-off-by: Robbie Zhang <robbie.zhang@intel.com> Original-Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/329480 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/13983 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-08mainboard/skylake: Include WRDD method in WIFI ACPI deviceDuncan Laurie
Include the code to add the WRDD method to the existing WiFi Device in the mainboard ACPI code. BUG=chrome-os-partner:50516 BRANCH=glados TEST=boot on chell with 'region'='us' in VPD and see that it is properly read out by calling WRDD method on the WiFi device. Compile for the other platforms that are modified. Change-Id: Ibcff7585744071ba9018d0ba50e274e63365b150 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Commit-Id: b74bb553415f7ce224ddcb0c2c5ae509b8fed516 Original-Change-Id: Ieb24e0e64974ee3686d14a234e148f5d07fc8b12 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/329296 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/13840 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-01Skylake boards: Enabling HWP (hardware P state control)Subrata Banik
This patch provides config options to enable/disable Intel SST (Speed Shift Technology). BUG=chrome-os-partner:47517 BRANCH=None TEST=Booted kunimitsu/lars, verified HWP driver load successfully. CQ-DEPEND=CL:313107 Change-Id: I9419a754384f96d308a5ac2ad90bbb519edc296e Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Commit-Id: 5efb7978e9d3ca9a709a4793ad213423a1c3c45d Original-Change-Id: I328b074b4f56ebe3caa8952ce3df7f834c1cf40f Original-Signed-off-by: Robbie Zhang <robbie.zhang@intel.com> Original-Signed-off-by: Subrata Banik <subrata.banik@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/326650 Original-Tested-by: Wenkai Du <wenkai.du@intel.com> Original-Reviewed-by: Benson Leung <bleung@chromium.org> Reviewed-on: https://review.coreboot.org/13843 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-02-12chromebooks: Define GBB hardware IDsPatrick Georgi
This makes the test IDs the default, taken from depthcharge master (board/*/fmap.dts, hwid property). Change-Id: I25793962ac16f451f204dbba6ede6a64c847cfd5 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/13634 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins)
2016-02-09chromebooks: Configure Chrome EC board namesPatrick Georgi
For devices with Chrome EC, state the "board" name(s), so they're built as part of the image. A number of EC boards aren't supported in the Chrome EC master branch, they're brought along but commented out, waiting for a port to master in the Chrome EC code base. Change-Id: Ic6ab821de55cf9b4e8b48fe5ebc603adeb8bb28b Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/13548 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-02-09skylake mainboards: Enable backing up VBNV from CMOS to flashDuncan Laurie
Enable the option to back up Vboot non-volatile data from CMOS to flash as these boards have the necessary nvram fmap region and are using vboot2 which does not backup to the TPM. BUG=chrome-os-partner:47915 BRANCH=glados TEST=manually tested on chell Change-Id: I7bfe88f2cb7826f3315987aaf56f77df708896ce Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 35df03c5ef24406129cba920ee9af6d55458cd45 Original-Change-Id: Ia7c014fe2768c55941a65ec5605ef4fbc986151c Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/324123 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/13601 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-04skylake boards: disable ACPI PM TimerArchana Patni
These devicetree patches set the ACPI PM Disabled variable to 1. This will disable the ACPI PM timer and remove from FADT table. BRANCH=none BUG=chrome-os-partner:48646 TEST=Build for skylake board with the PmTimerDisabled policy in devicetree set to 1. iotools mmio_read32 0xfe0000fc should return 0x2. cat /sys/devices/system/clocksource/clocksource0/available_clocksource should list only "tsc hpet". acpi_pm should be removed from this list. Change-Id: Ia66f37e13f0f2f527651418b8b5c337b56c25c7f Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: db3e8130495038850c7034b89701b4a5fcf88dce Original-Change-Id: Ib1b876cfa361b8cbdde2f9e212e3da4fd724e498 Original-Signed-off-by: Archana Patni <archana.patni@intel.com> Original-Signed-off-by: Subramony Sesha <subramony.sesha@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/319362 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/13589 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-02-04google/glados: perform early init for CAR *stageAaron Durbin
In order to support both separate verstage and a verified boot after romstage one needs to ensure the proper GPIO and EC configuration been complete. Therefore, move that logic to car_mainboard_post_console_init() in car.c file which gets called in the early flow of a CAR stage (either verstage or romstage). BUG=chrome-os-partner:44827 BRANCH=glados TEST=Built glados w/ separate verstage and booted. Change-Id: I626a500c183d21f94d976e24f09af15a242fba9c Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: b564514a8b93f53a919fcdac3589e30dbac82124 Original-Change-Id: Icc989ec5700b3f1a144a6b41198b7dd2c2aac6f7 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/324073 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/13583 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-01-22skylake mainboards: Enable CONFIG_VBOOT_EC_SLOW_UPDATEDuncan Laurie
Updating EC+PD takes long enough to update that it is good to show the "critical update" screen when doing an EC/PD update. BUG=chrome-os-partner:49650 BRANCH=glados TEST=Build and boot on chell in normal mode with an EC update payload and ensure that it reboots to enable graphics, shows the "critical update" screen, and then reboots to disable graphics init again. Change-Id: I436b96b95595b68273e594bdcfe2db0789ee26b2 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 08e45decd066f8f57ad103ff8b76cb7a916afa9e Original-Change-Id: Ie250f4531437e4a0ce14b5aeb0fe564e9461fe4d Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/322783 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/13075 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-22intel/skylake: PL2 override changespchandri
Override the default PL2 values with ones recommended by Intel. BUG=chrome-os-partner:49292 BRANCH=glados TEST=MMIO 0x59A0[14-0] to find PL1 value (0x78) / 8 Watts = 15W MMIO 0x59A0[15] to find PL1 enable/disable = Disable MMIO 0x59A0[46-32] to find PL2 Value (0xC8) / 8 Watts = 25W Here PL2 is set to 25W and PL1 is disabled. CQ-DEPEND=CL:321392 Change-Id: I338b1d4879ae1b5f760e3c1d16e379a2baa1c965 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: fa6a115227385bef44abfacf58af306c16ed478a Original-Change-Id: I3bfc50256c9bdd522c984b11faf2903d7c44c81f Original-Signed-off-by: pchandri <preetham.chandrian@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/322454 Original-Commit-Ready: Venkateswarlu V Vinjamuri <venkateswarlu.v.vinjamuri@intel.com> Original-Tested-by: Venkateswarlu V Vinjamuri <venkateswarlu.v.vinjamuri@intel.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Preetham Chandrian <preetham.chandrian@intel.com> Original-Reviewed-by: Venkateswarlu V Vinjamuri <venkateswarlu.v.vinjamuri@intel.com> Reviewed-on: https://review.coreboot.org/13071 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-21chromeos: import Chrome OS fmapsPatrick Georgi
These are generated from depthcharge's board/*/fmap.dts using the dts-to-fmd.sh script. One special case is google/veyron's chromeos.fmd, which is used for a larger set of boards - no problem since the converted fmd was the same for all of them. Set aside 128K for the bootblock on non-x86 systems (where the COREBOOT region ends up at the beginning of flash). This becomes necessary because we're working without a real cbfs master header (exists for transition only), which carved out the space for the offset. Change-Id: Ieeb33702d3e58e07e958523533f83da97237ecf1 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/12715 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-19google/glados: Set FSP params for min assertion widths and serirqDuncan Laurie
- Enable serial irq configuration in FSP. - Set minimum assertion width values for FSP to configure. - Set I2C4 voltage to 1.8V. - Enable SaGv feature to dynamically train memory frequency. - Disable Deep S3 to match chell so DeepSx story is consistent on skylake-y boards. BUG=chrome-os-partner:47688 BRANCH=none TEST=emerge-glados coreboot (tested on chell board) Change-Id: Ied6bda6a3f2108df7167e0970abe71977d8d2a5c Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: fbf353288edc9629ad03b17d0a582e3042d5a5e1 Original-Change-Id: I1619dd5316060793f38b74f8f0bcaf23d8ab2552 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/321211 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/13008 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-18google/glados: Enable FspSkipMpInit tokenBarnali Sarkar
MP init is already handled in coreboot, but it is also part of FSP. FSP has a implemented a provision to allow FSP to skip MP init and let coreboot handle it. BRANCH=none BUG=chrome-os-partner:44805 TEST=none CQ-DEPEND=CL:319353 Change-Id: I81c54582a3c980ecdcf329347bcd5982802d681c Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: e60ee81acaeb1062a31a3e78ed2ba4ccfe816ec5 Original-Change-Id: I71dd07559dffb7886e489274ffc8e71686ca730f Original-Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/319370 Original-Commit-Ready: Preetham Chandrian <preetham.chandrian@intel.com> Original-Tested-by: Preetham Chandrian <preetham.chandrian@intel.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/12994 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-18google/glados: Add VR config settingsrobbie zhang
Use the Kunimitsu settings as baseline, except Psi4Enable set to 0 due to a known issue (not able to hit S0ix) on glados. The VR settings will then need to be updated per the board VR design. BRANCH=none BUG=chrome-os-partner:48466 TEST=Build and booted glados Change-Id: I42d360657ab7c47d66043f39b79540b69a9072d1 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: d06397c1c32136d1b6a1c1346ed722ad6926ce1a Original-Change-Id: Ib0746cd84c2c8af29f53a65a0a7b85966c918869 Original-Signed-off-by: robbie zhang <robbie.zhang@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/317910 Original-Commit-Ready: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/12984 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-18google/glados: Add pull-ups on LPC address lines and setup PCH_WP earlyDuncan Laurie
Copy changes from chell to add 20K pull-up to LPC address lines and setup the PCH_WP signal early so it is set correctly in VBNV. BUG=chrome-os-partner:40635 BRANCH=none TEST=emerge-glados coreboot Change-Id: I3337cb9e5ee445471c7a0b61ee22869f66189b63 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: c99dae3729636790c2ad457ec3271d2bd99fb1c4 Original-Change-Id: I7627ec263e710ce186cea15c805203395acf3e99 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/317244 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/12982 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-18skylake boards: csme: add p2sb device and hecienabled devicetree variableArchana Patni
The HeciEnabled decides the state of Heci1 at end of boot. Setting to 0 (default) disables Heci1 and hides the device from OS. It internally uses the FSP Psf Unlock policy to disable the Heci1. It also adds the p2sb device in the devicetree which is necessary for hiding and unhiding the device. BRANCH=none BUG=chrome-os-partner:45618 TEST=build for kunimitsu. CQ-DEPEND=CL:*238451 Change-Id: Ieba2ab3b4ac518cce8371069028170ba99aaf079 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: cbefe9d6e9a981594534d346be67a5cd94483d05 Original-Change-Id: I8c95b5b9b28ba8441ca031f4e9ec523d913990d6 Original-Signed-off-by: Archana Patni <archana.patni@intel.com> Original-Signed-off-by: Subramony Sesha <subramony.sesha@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/311913 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/12977 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-16mainboard: Drop abuild.disabled files for Skylake boardsStefan Reinauer
Make sure the latest & greatest Intel targets actually build in our build system. intel/sklrvp is still failing for reasons unrelated to the rest of the skylake boards. Leaving that disabled for now. Change-Id: Ie784628a57257cea30e5e47074648198b884f6db Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12857 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins)
2016-01-15google/glados: add nhlt supportAaron Durbin
Provide an option for including the NHLT blobs within the glados mainboard directory while also adding the ACPI NHLT table generation that the current hardware supports. BUG=chrome-os-partner:44481 BRANCH=None TEST=Built and booted. Headphones, speakers, and mic on camera emits and creates sound albeit not the greatest. Change-Id: I6e36c0a99a73cdcb2bf6ccfbfc886a594f989a39 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 5b0383a93f054011dd7c18519ece4e6f1944366d Original-Change-Id: I6f8bd15c72fa89756382af99bddb6cb6abe89905 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/313794 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/12939 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2015-12-10cbfs/vboot: remove firmware component supportAaron Durbin
The Chrome OS verified boot path supported multiple CBFS instances in the boot media as well as stand-alone assets sitting in each vboot RW slot. Remove the support for the stand-alone assets and always use CBFS accesses as the way to retrieve data. This is implemented by adding a cbfs_locator object which is queried for locating the current CBFS. Additionally, it is also signalled prior to when a program is about to be loaded by coreboot for the subsequent stage/payload. This provides the same opportunity as previous for vboot to hook in and perform its logic. BUG=chromium:445938 BRANCH=None TEST=Built and ran on glados. CQ-DEPEND=CL:307121,CL:31691,CL:31690 Change-Id: I6a3a15feb6edd355d6ec252c36b6f7885b383099 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/12689 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-03google/glados: Disable kepler deviceDuncan Laurie
Disable the kepler device to save power and enable S0ix testing. It has been disabled in the ME image and was not working anyway.. BUG=chrome-os-partner:40635 BRANCH=none TEST=build and boot on glados Change-Id: I6640c7a09d418ba4b4de6f16138c124436dd8758 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 6490769a32539cb6ef429717f021519c152a4a54 Original-Change-Id: If6e384dd2218c6a110747a489329a59fa6433c02 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/313827 Original-Commit-Ready: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/12599 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2015-11-18google/glados: disable power rails in sleep pathAaron Durbin
For the rails controllable by the host processor through gpios turn them off in the sleep paths. The result is that S3 and S5 will turn off those rails. BUG=chrome-os-partner:47228 BRANCH=None TEST=Built and booted glados. Suspended and resumed. Change-Id: I6d45683b64ca5f7c3c47e11f95951bd2d9abf31e Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: ed432e2b5535da6f872a53b76886d983f00b4e8e Original-Change-Id: I94d7e0b00bf7e7da8dc59f299e41b72e8fcb64f4 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/312320 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/12445 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2015-11-11intel/skylake: mainboards: Add MAINBOARD_FAMILY kconfig entryDuncan Laurie
The family variable was not being set yet for skylake, add this to the current boards. BUG=chromium:551715 BRANCH=none TEST=emerge-glados coreboot Change-Id: Icf175e4ce89cb47b9eabce1399eb3ef29e7a607f Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 7e379402f38634eb0204e03b616111fff9515cec Original-Change-Id: Ia31fb04b5c22defc71a0c02d9fa1eff93ccbc49d Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/311213 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/12390 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-05Kconfig: Remove obsolete Kconfig symbols from google/intel boardsMartin Roth
- CACHE_ROM is no longer used in the coreboot code. It was removed in commit 4337020b (Remove CACHE_ROM.) - CAR_MIGRATION is also no longer used in coreboot code - it was removed in commit cbf5bdfe (CBMEM: Always select CAR_MIGRATION) - MARK_GRAPHICS_MEM_WRCOMB was removed in commit 30fe6120 (MTRR: Mark all prefetchable resources as WRCOMB) Change-Id: I8b33a08c256f6b022e57e9af60d0629d9a3ffac8 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: http://review.coreboot.org/12327 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2015-11-05intel/kunimitsu, google/glados: Enable Fan control supportSumeet Pawnikar
This patch enables the Fan thermal participant device in the device tree for thermal active cooling action for DPTF on SKL-U fan based kunimitsu board. This patch defines the _ART table in dptf ASL file. With active cooling policy (_ART), we can control the fan on/off and speed. BRANCH=None BUG=chrome-os-partner:46493 TEST=Built for kunimitsu board. Tested to see that the thermal devices and the participants are enumerated and can be seen in the /sys/bus/platform/devices. Also, checked the FAN type the cooling devices enumerated in the /sys/class/thermal with sysfs interface. Change-Id: I40c540dad32beefe249f025b570c347d3ad08c36 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 82ae11643ca23e65780006f3890f1d173363b8af Original-Change-Id: If44b358052a677d13c74919f09a3eb89611fccad Original-Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/307028 Original-Commit-Ready: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Original-Tested-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Original-Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/12323 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-05mainboard: Remove last_boot NVRAM optionTimothy Pearson
The last_boot NVRAM option was deprecated and removed in commit 3bfd7cc6. Remove the last_boot option from all affected mainboards to eliminate user confusion. Change-Id: I7e201b9cf21dfe5dda156785bad078524098626d Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/12316 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins)
2015-10-31tree: drop last paragraph of GPL copyright headerPatrick Georgi
It encourages users from writing to the FSF without giving an address. Linux also prefers to drop that and their checkpatch.pl (that we imported) looks out for that. This is the result of util/scripts/no-fsf-addresses.sh with no further editing. Change-Id: Ie96faea295fe001911d77dbc51e9a6789558fbd6 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/11888 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-10-28google/glados: Set the type-c flex port to max USB2 settingsDuncan Laurie
Change the tuning setting for the type-c port that is over the flex cable to use the max possible drive strength. Also fix up the comments to indicate what Type-c port goes where instead of just referring to them by number. BUG=chrome-os-partner:45367 BRANCH=none TEST=build and boot on glados Change-Id: Iebcffc9ab95d56289258017248c273090c88bb06 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 824ca87c4bf556d493dc8cdec561f37ab135cd2d Original-Change-Id: I081623bbb1b0f39f1569b9f5cf7933abefe202b3 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/309010 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/12204 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-10-27intel/skylake: Clean up USB configuration in devicetreeDuncan Laurie
Instead of having many different arrays for USB configuration, with each array containing one bit of information, have one array containing all the information for each port. This way we can put the basic tuning parameters into a structure and then define structures for the basic supported configurations. The existing port definitions are taken from the Skylake HSIO tuning guide. BUG=chrome-os-partner:40635 BRANCH=none TEST=build and boot on glados, verify USB functionality in all ports. Change-Id: I5873dee011ae9e250b6654c73a7bd5c17681095b Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 864040412b2d2923d3acbfca8055724887c58506 Original-Change-Id: Id518b1086abbe4a8c25d77fd4efc2d0de856bd5f Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/306734 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/12163 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-10-27google/glados: csme: program sml gpios for csme power gatingArchana Patni
For SMT controllers to power gate, all SMT/SMS clock, data and alert signals should be inactive. The SML0 blocks are not used for any functional purposes and are not configured in the GPIO tables. SMT hardware will not allow the blocks to be power gated in this scenario. The SML* pins are now configured as GPIOs - input and deep. With this change, the SMT blocks are properly power gating. BRANCH=none BUG=chrome-os-partner:45618 TEST=build for Glados. Change-Id: Ie5406f2a1e0c485ac1290e2154755085fa3bb7b9 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 5b3fe3c2ddea4c5daedb04078b24cff14efa49d5 Original-Change-Id: I8dcc0bfc121e612a174e6fe3152650d0fcd68f39 Original-Signed-off-by: Archana Patni <archana.patni@intel.com> Original-Signed-off-by: Subramony Sesha <subramony.sesha@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/306481 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/12160 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-10-27google/glados: Add USB phy settings and update enabled optionsDuncan Laurie
- Add placeholder USB phy settings, needs tuning still - Change UART2 to be skipped during FSP init - Update headphone codec irq to be level triggered as that is how the kernel is configuring it BUG=chrome-os-partner:40635 BRANCH=none TEST=emerge-glados coreboot Change-Id: I9a15a27dab49d4e19f8ef0574ee2e61ae90c99fc Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 6e7a0032ba23d6762342639c2c7cb877c1f90452 Original-Change-Id: Ie1439f21116022b0644d06853df9490e4651a9ae Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/304926 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/12149 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-10-27google/glados: Enable TPM PIRQDuncan Laurie
Enable the config option for TPM to use PIRQ instead of SERIRQ and enable the MAINBOARD_HAS_LPC_TPM option. BUG=chrome-os-partner:40635 BRANCH=none TEST=emerge-glados coreboot Change-Id: I990901117a2c478045c403f1039d6eedfc278255 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 44ecaaae1eb482ef5d4cf1e051de4571cc4441be Original-Change-Id: I115d468c72c3fd015abdddffdd1626368bfedb6e Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/304925 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/12148 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-10-11glados: add chromeos.c to verstageAaron Durbin
In order to build stand alone verstage the chromeos.c file needs to be part of the verstage target. BUG=chrome-os-partner:44827 BRANCH=None TEST=Built and booted glados. Change-Id: Id2b05548e4e10cd12002286913f2228b84802e63 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11828 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-09-28glados: Provide nau8825 platform data via _DSDBen Zhang
BUG=chrome-os-partner:41280 BRANCH=none TEST=Audio jack insert/eject detection and headset buttons work on glados with the nau8825 driver in chromeos-3.18 and the staging kernel skl2. Change-Id: I813a985b4a39249a2cdbe45117acbdb7710bfa29 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 7a5b3dafd407fea2376dff5c3dcde50dff4704fb Original-Change-Id: Ic24a0c444761d0f3a35c268078e70d9aacca4c80 Original-Signed-off-by: Ben Zhang <benzh@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/293610 Original-Reviewed-by: Anatol Pomazau <anatol@google.com> Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/11720 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2015-09-28glados: Fix typo for WLAN ACPI device nameDuncan Laurie
Fix the typo of _DDR to be _DDN. BUG=chrome-os-partner:40635 BRANCH=none TEST=build glados with iasl-20150717 Change-Id: I8d61a6653c3109890d04e54f0d694703b9c9f2bf Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: d4a2b2583bdbf9afd7b306359338d4c49bbb44ad Original-Change-Id: I7b7905a217d34a8a78b8280c898f1074ecbe3cf6 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/302164 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11717 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2015-09-17glados/kunimitsu: remove the implementation of mainboard_add_dimm_inforobbie zhang
This is a follow-up patch to https://chromium-review.googlesource.com/#/c/286877, after fsp support is landed in v1.5. BUG=chrome-os-partner:42975 BRANCH=none TEST=execute "mosys memory spd print all" on glados and kunimitsu Change-Id: I949e287372b190affac36a0efde8a30402eecdc8 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 71a2e1838ff8bbaa358c167dad905b63d23c43fa Original-Change-Id: I64103af4f8456a053a955845a067062122f47af3 Original-Signed-off-by: Robbie Zhang <robbie.zhang@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/298967 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/11657 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-09-17glados: Enable wake-on-wifiDuncan Laurie
- Assign GPE DW0 to GPP_B block - Enable GPP_B16 as ACPI_SCI for wake - Define PCIe WLAN device in ACPI with GPE0_DW0_16 for _PRW Note that current designs cannot wake from Deep S3 via wifi. BUG=chrome-os-partner:40635 BRANCH=none TEST=tested on glados: 1-disable deep s3 in devicetree.cb 2-enable magic packet with "iw phy phy0 wowlan enable magic-packet" 3-powerd_dbus_suspend to go to S3 4-wake system with magic packet Change-Id: I989768615e9da8ecf6354852d2db7aae8069aa82 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 894354c5bfd499b911b7f89310c48b503dbaadc2 Original-Change-Id: I9a7a317fc2eccc70fdb4862843de1a654fbc2eee Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/298231 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11650 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-09-17glados: Remove code to set USB charge behavior on sleepDuncan Laurie
The EC doesn't support these commands so sending them is not working. We have had a default policy of wake on USB for a long time now and this runtime config isn't really needed any longer. BUG=chrome-os-partner:40635 BRANCH=none TEST=emerge-glados coreboot Change-Id: Ib789ae3a7ba56a11dfb5918cb40bfa2f044d1dc3 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 0ed7391942afed94bfc7ad04880d4c2b865e5655 Original-Change-Id: I6fe10952f32673a447001b832ac6c6b04b22aef0 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/298233 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11652 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-09-16glados: Enable ALS connected to ECDuncan Laurie
Glados has an ambient light sensor connected to the EC which is presented to the OS as a standard ACPI0008 device. BUG=chrome-os-partner:43493 BRANCH=none TEST=test ALS functionality on glados P2 board Change-Id: I4a4913a1b407720d85f6e630b674e550bf5e36df Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: aee2b2446ca45039f1b4866feb83754861dba054 Original-Change-Id: I61f3f31ba077f63b36aa0cd9707e128e65c9ea7d Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/298251 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11644 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-09-10glados: Remove functions from acpi_tables.cDuncan Laurie
Remove the acpi_tables.c functions so these functions can move to SOC init code. The file itself is included by x86/arch code and must exist for the build to succeed. BUG=chrome-os-partner:40635 BRANCH=none TEST=emerge-glados coreboot Change-Id: I18e6a0be5eac053598b613b30b622c4963417919 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: af04eb112adf58578c8d2c9d3d182d4c2024abb2 Original-Change-Id: Ibe026d493c25d771357ea39e4b956629fbb799ac Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/297758 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11579 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-09-10glados: Add Board ID supportDuncan Laurie
Add support for reading board id and populating it in the coreboot tables so it is exposed to payloads. BUG=chrome-os-partner:40635 BRANCH=none TEST=boot on glados and look for reported board ID Change-Id: Iba93a913b67e3b3230aded289c2e25585dec1195 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 472cb7bc84136a1a8b284d661868e64eca4ec004 Original-Change-Id: I478dc0b2f96310b7adbd84701e70598a57306628 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/297746 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11570 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-09-10glados: Enable DPTFDuncan Laurie
- Add ACPI code for DPTF support with placeholder thresholds - Do not have custom PDL for mainboard - Do not have enable charger control for DPTF as there is already a complicated charge profile in the EC. We may still want to enable this but it would need to be tuned to work well with the EC profile. BUG=chrome-os-partner:40635 BRANCH=none TEST=emerge-glados coreboot Change-Id: I8cd2e0ea9c322ea92c101995e8e706f063428a45 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 55d3614441d6701a6d6f0f9d1ade94364ef2594a Original-Change-Id: Ie4587572742d3bcdba7c008fc195213ac50c9d9e Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/297745 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11569 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-09-10glados: Misc code cleanupsDuncan Laurie
- romstage.c is using gpio_configure_pads so it should really include soc/gpio.h instead of relying on it to come from "gpio.h" - consistent formatting of array initializers in pei_data.c - remove pei_data->ec_present flag as this is unused in skylake - fix printk level in spd/spd.c to be BIOS_INFO instead of BIOS_ERR - clean up acpi_slp_type usage in ec.c, remove unnecessary post codes, and cleaner console output message. BUG=chrome-os-partner:40635 BRANCH=none TEST=emerge-glados coreboot Change-Id: I0f76a560dc2c4197e66999752c52573ff0278430 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 67c29f900b7709b73bd0d1e0da26f96cca32828b Original-Change-Id: Ia2a320acf879fa85e9f6b06265cfe38e50e51e46 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/297744 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11568 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-09-10glados: Remove thermal.hDuncan Laurie
The constants defined in thermal.h are never used since there is no defined thermal zone. Remove it to result in less code to worry about in board ports. BUG=chrome-os-partner:40635 BRANCH=none TEST=emerge-glados coreboot Change-Id: Idb716b47875b20e2110741ae9c154cc52307fbcf Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 01be180b14b5381a8d339dab6c28428c7ac40c10 Original-Change-Id: Ibb710abc301b18d5632f4e01765ea0374b2fe787 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/297743 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11567 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-09-10glados: Change include headers to relative pathDuncan Laurie
To make it easier to port glados to a new board name change the include headers to use relative path name instead of including the mainboard name. BUG=chrome-os-partner:40635 BRANCH=none TEST=emerge-glados coreboot Change-Id: I6d184adab5b6b2df970ddd3998d3413f1330c12e Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 11dd6b73f298cf4867f4a089478132d5e543ea90 Original-Change-Id: Ia8de127fb176784acbbee975e8b950f8c9824c5c Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/297742 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11566 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-09-09glados: Select EC PD and call early EC initDuncan Laurie
Select the EC PD support in kconfig and call the EC early init code that will reboot into RO for recovery mode. BUG=chrome-os-partner:40635 BRANCH=none TEST=boot on glados in recovery mode Change-Id: Ifa1e2afd91a247c3830d8e705d9d34fb02239fe4 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 135ef6e0e2c4864be1c25a9761e04cfe17aec51e Original-Change-Id: Iac8c092453bfbd94210462be0b377fb77410941d Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/297749 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11573 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-09-08glados: Clean up devicetree.cbDuncan Laurie
Clean up the PCI device list comments to be consistent between the skylake mainboards. BUG=chrome-os-partner:40635 BRANCH=none TEST=emerge-glados coreboot Change-Id: I0080ab21db006365f34995db06480dae68ac547d Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: fa21f77cbaafbc9ca0b98d6951df92c4349fa28d Original-Change-Id: Ie70f94dcc12da141d82b4445643cc0cbe08bb766 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/297338 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11561 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-09-08glados: Fix incorrect comment format in devicetree.cbDuncan Laurie
The devicetree.cb compiler can't handle C style /**/ comments, they need to be shell-style #. Due to a last minute formatting change in my commit to enable USB ports this broke the glados build. BUG=chrome-os-partner:44662 BRANCH=none TEST=emerge-glados coreboot Change-Id: I46ee4e5a94d61eefbd2c9a1ba3cafcb6a9e7d71b Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 8fa92f77b3ef13ede1029292d886351ab5ed87d2 Original-Change-Id: Ibff02a4fd6132def81006a2c6502d34bd4b72823 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/296301 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11553 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-09-08glados: Disable unused USB portsDuncan Laurie
Enable only the USB ports that are connected on-board or to an external port, all others will be disabled. BUG=chrome-os-partner:44662 BRANCH=none TEST=build and boot on glados, ensure expected USB ports still work Change-Id: I8c999e3b17478effc39cf078f8420f63413d091b Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: b86268c70f86991f8c2cdd6763f8efe2ce7f9163 Original-Change-Id: I2fce2c401d07639892c4a0c01527173d3f0b2557 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/296035 Original-Commit-Ready: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11548 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-09-08glados: Update 4GB DIMM SPD for 1866Duncan Laurie
Enable 1866 timings in the 4GB Hynix SPD. BUG=chrome-os-partner:44394 BRANCH=none TEST=emerge-glados coreboot Change-Id: Ibb84f77565d46894afe2153f5951e17a450413fc Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: f64d76a5f0b0095be96317674caf8542c3155423 Original-Change-Id: Ic5312176c21afc4569f723f5b7f00283b09262d7 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/295174 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11528 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-09-01chromeec: Move keyboard backlight code into Chrome EC directoryDuncan Laurie
Since more boards are starting to use the EC provided keyboard backlight interface move the code to a common place and allow it to get included in mainboards. Change-Id: I3f307bbce1a96cdd1c8224b1e89a63d6fedef738 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: http://review.coreboot.org/11478 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-08-29google/glados: Remove unnecessary check for mainboard_ec_init()Martin Roth
mainboard_ec_init() wasn't getting run due to an invalid Kconfig symbol. This check isn't required as the Kconfig option for the EC is forced to be enabled, and the function should always be run. BRANCH=none BUG=none TEST=Rebuilt glados mainboard. Change-Id: I2c4a33d80533a19b02b83b3aaa6a3386e927f1c7 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Original-Commit-Id: edd8c7a0666208b35ee81f57ec2626390958dfb7 Original-Change-Id: I2a92fd28347455c09ecf2119788ca9b6a97a11de Original-Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/295143 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11435 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-08-29google/glados: configure gpio pads prior to SiliconInit()Aaron Durbin
Move the gpio pad configuration prior to SiliconInit() in case there are dependencies of the pads being configured in prior to SiliconInit(). BUG=chrome-os-partner:43522 BUG=chrome-os-partner:43492 BRANCH=None TEST=Built and booted glados. Change-Id: I84f8e965bf205a4945b14a63fa8074953750f785 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Original-Commit-Id: 5cce5347449f69ac6cf7030ea3b91d3f8b4cc7f9 Original-Change-Id: I18cd33a455d5635a866abb76142cab516b04f446 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/294642 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/11420 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-08-29google/glados: fix kepler probingAaron Durbin
On proto2 boards the kepler device has its reset line pulled up to one of its IO rails with a zener in between. This results in the device not being visible at MemoryInit() time because for some reason FSP is doing PCIE configuration/probing in that path. Hack around the broken FSP logic by configuring the pads for kepler's power and clkreq. BUG=chrome-os-partner:44326 BRANCH=None TEST=Built and booted glados. lscpi shows the device on bus 2. Change-Id: I543eb3ccd3ab5ffacd6efc959e6e2f7a88de78b3 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Original-Commit-Id: 67f6b57487e8724b469f74870e0083d4e1dac4d2 Original-Change-Id: I7fe4a707f9321b7bdec4b4be729c5d0dcce65f6e Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/294810 Original-Reviewed-by: Robbie Zhang <robbie.zhang@intel.com> Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/11419 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>