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path: root/src/mainboard/google/glados/spd
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2019-06-19src/mainboard: Remove unused include <arch/byteorder.h>Elyes HAOUAS
Change-Id: I3d638febddbd88cd4870795f96dd1bbf123c7ba3 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33537 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-05-07mb/google/glados: Refactor to get rid of `pei_data`Nico Huber
The SoC specific `struct pei_data` was filled with values that were later only consumed by the mainboard code again. Avoid jumping through this hoop and fill FSP UPDs directly. Change-Id: I040f4a55b4f4bad3f6072920e5e2eceded4cb9bb Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32594 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-07-24google/cave: Add as a variant of gladosMatt DeVillier
Add google/cave (Asus Chromebook Flip C302SA) as a variant of glados Skylake reference board: - add cave-specific DPTF, EC config, GPIO config, Kconfig, NHLT config, PEI data, VBT, SPD data, and devicetree Adapted from Chromium branch firmware-glados-7820.B, commit b0c3efe54d877246d07f2467b2dff51cc30348fa [soc/intel/skylake: Enable VMX] Test: build/boot google/cave, verify correct functionality Change-Id: I5c5181ce68f7a24ccd49f53ecd9d48c081fd085a Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/27420 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-07-24google/caroline: Add as a variant of gladosMatt DeVillier
Add google/caroline (Samsung Chromebook Pro) as a variant of glados Skylake reference board: - add caroline-specific DPTF, EC config, GPIO config, Kconfig, NHLT config, PEI data, VBT, SPD data, and devicetree - add caroline-specific memory-init param to romstage - adjust mainboard EC SCI events for boards with tablet function Adapted from Chromium branch firmware-glados-7820.B, commit b0c3efe54d877246d07f2467b2dff51cc30348fa [soc/intel/skylake: Enable VMX] Test: build/boot google/caroline, verify correct functionality Change-Id: I611a4e76581ba2e5b42e1bc48b0a5b8c70f3598e Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/27419 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-07-24google/sentry: Add as a variant of gladosMatt DeVillier
Add google/sentry (Lenovo Thinkpad 13 Chromebook) as a variant of glados Skylake reference board: - add sentry-specific DPTF, EC config, GPIO config, Kconfig, NHLT config, PEI data, VBT, SPD data, and devicetree - add sentry-specific GPIO determination of which audio codec is present Adapted from Chromium branch firmware-glados-7820.B, commit b0c3efe54d877246d07f2467b2dff51cc30348fa [soc/intel/skylake: Enable VMX] Test: build/boot google/sentry, verify correct functionality Change-Id: I783422aedac8b7fc52098eebd05b2061a1011b60 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/27418 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Youness Alaoui <snifikino@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-21google/lars: Convert to a variant of gladosMatt DeVillier
Convert lars to a variant of glados Skylake reference board: - add lars-specific DPTF, EC config, GPIO config, Kconfig, NHLT config, PEI data, VBT, SPD data, and devicetree - add conditional generation of NHLT ACPI data for Maxim codec, including override of OEM ID and OEM table ID - remove existing lars board/directory Test: build/boot google/lars, verify functionality unchanged from pre-variant configuration Change-Id: Iab37f1b92b0f3a5d99796f916a6fdcc14ce4eef4 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/27413 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Youness Alaoui <snifikino@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-21google/chell: Convert to a variant of gladosMatt DeVillier
Convert chell to a variant of glados Skylake reference board: - add chell-specific DPTF, EC config, USB port defs, GPIO config, NHLT config, PEI data, VBT, SPD data, and devicetree - add romstage handler to turn on keyboard backlight for boards so equipped - remove existing chell board/directory Test: build/boot google/chell, verify functionality unchanged from pre-variant configuration Change-Id: I7dfbafe3afcab7cee7bcb2bf91c6733c07b409c4 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/27412 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-07-21google/glados: Convert to variant setupMatt DeVillier
Convert Skylake reference board glados to variant setup in preparation for merge with existing Skylake boards chell and lars, and upstreaming of new boards asuka, caroline, cave, and sentry. The following changes have been made: - move DPTF to variant subdir - move non-common EC defs to variant subdir - adjust Kconfig for variant setup - move non-common NHLT config to variant Kconfig - make non-common NHLT ACPI code conditional - move devicetree to variant subdir - move board GPIO defs to variant subdir - move board PEI data to variant subdir - move SPD index calculation to romstage so available for dual-channel determination during PEI for boards which need it - move SPD compilation to variant makefile - add weak function for determination of dual-channel RAM - add weak function for mainboard_gpio_smi_sleep() so SKL-Y variants can override and power down rails as needed Test: build google/glados Change-Id: I41615979dc11b5a10e32d6b5f477a256735cde53 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/27411 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2016-08-14src/mainboard: Capitalize ROM, RAM, CPU and APICElyes HAOUAS
Change-Id: Ia1f24d328a065a54975adde067df36c5751bff2d Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/15987 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2015-10-31tree: drop last paragraph of GPL copyright headerPatrick Georgi
It encourages users from writing to the FSF without giving an address. Linux also prefers to drop that and their checkpatch.pl (that we imported) looks out for that. This is the result of util/scripts/no-fsf-addresses.sh with no further editing. Change-Id: Ie96faea295fe001911d77dbc51e9a6789558fbd6 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/11888 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-09-10glados: Misc code cleanupsDuncan Laurie
- romstage.c is using gpio_configure_pads so it should really include soc/gpio.h instead of relying on it to come from "gpio.h" - consistent formatting of array initializers in pei_data.c - remove pei_data->ec_present flag as this is unused in skylake - fix printk level in spd/spd.c to be BIOS_INFO instead of BIOS_ERR - clean up acpi_slp_type usage in ec.c, remove unnecessary post codes, and cleaner console output message. BUG=chrome-os-partner:40635 BRANCH=none TEST=emerge-glados coreboot Change-Id: I0f76a560dc2c4197e66999752c52573ff0278430 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 67c29f900b7709b73bd0d1e0da26f96cca32828b Original-Change-Id: Ia2a320acf879fa85e9f6b06265cfe38e50e51e46 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/297744 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11568 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-09-10glados: Change include headers to relative pathDuncan Laurie
To make it easier to port glados to a new board name change the include headers to use relative path name instead of including the mainboard name. BUG=chrome-os-partner:40635 BRANCH=none TEST=emerge-glados coreboot Change-Id: I6d184adab5b6b2df970ddd3998d3413f1330c12e Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 11dd6b73f298cf4867f4a089478132d5e543ea90 Original-Change-Id: Ia8de127fb176784acbbee975e8b950f8c9824c5c Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/297742 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11566 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-09-08glados: Update 4GB DIMM SPD for 1866Duncan Laurie
Enable 1866 timings in the 4GB Hynix SPD. BUG=chrome-os-partner:44394 BRANCH=none TEST=emerge-glados coreboot Change-Id: Ibb84f77565d46894afe2153f5951e17a450413fc Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: f64d76a5f0b0095be96317674caf8542c3155423 Original-Change-Id: Ic5312176c21afc4569f723f5b7f00283b09262d7 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/295174 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11528 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-08-27glados: Abstract board GPIO configuration in gpio.hDuncan Laurie
Move all the various places that look at board specific GPIOs into the mainboard gpio.h so it can be easily ported to new boards. BUG=chrome-os-partner:40635 BRANCH=none TEST=build and boot on glados p2 Original-Change-Id: I3f1754012158dd5c7d5bbd6e07e40850f21af56d Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/293942 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Change-Id: I93c4dc1795c1107a3d96e686f03df3199f30de8a Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/11282 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2015-08-27glados: Fix SPD part number for Hynix H9CCNNN8JTBLARDuncan Laurie
The part number was the same as the H9CCNNNBLTLAR which means it is not possible to distinguish the two based on part number alone. This breaks mosys and thus the factory tests. BUG=chrome-os-partner:43514 BRANCH=none TEST=boot on glados P2 SKU3 and verify memory reported by mosys Original-Change-Id: I606ef3989bd7273d134a258bc933088ccc865542 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/293513 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Change-Id: I7cea7cc4c61a20fda47673c8e25c431d391aa3bc Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/11279 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-08-14glados: move to native gpio configurationAaron Durbin
Instead of relying on FSP to do gpio configuration in one place use the native support in coreboot. This also removes the open coded configuration of the memory configuration ids. BUG=chrome-os-partner:42982 BRANCH=None TEST=Built and booted glados. Original-Change-Id: I4655221d821d91a2270d774305a02d6bd5c3959c Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/289800 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Change-Id: I2e66242d050c3825f6bc65d3d2c7f51d2cdfbd73 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11175 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-07-24glados: Support reading memory strap GPIOs to select SPDDuncan Laurie
Add some board specific code to enable the memory configuration GPIOs in GPIO input mode and read them to determine which memory type is on the board. Also add the other memory types that are not yet present in the glados mainboard directory. This should be replaced with the real gpio infrastructure once it is ready. BUG=chrome-os-partner:43069 BRANCH=none TEST=build and boot on glados Change-Id: I7a9ce10e92ad6681528572e87b6cfee29880841a Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: d81e969c5950fd89bb745d1403abddb08a942f83 Original-Change-Id: Iffb0bd5c176f2adbdd9302d9bff5b7bde725d671 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/287436 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11046 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-23glados: Add SPD manufacturer and part numberDuncan Laurie
The FSP memory info hob does not return this data so we need to supply it from the SPD included with the mainboard. BUG=chrome-os-partner:42975, chrome-os-partner:42561 BRANCH=none TEST=execute "mosys memory spd print all" on glados Change-Id: Idfb71d36d1f8163d0daceb68675b10194db7cde7 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 7feece45900e5166864927047ad3ab7b997f8258 Original-Change-Id: Id2bc544ac5faf53f0f676fe132fea1db5640a401 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/286877 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11034 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-07-21google/glados: add new boardPatrick Georgi
Change-Id: I0c196ff84484717c59c59d11bb7230b5920e0654 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/10997 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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