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Add eDP panel power-on sequences and initialize the display in the
ramstage.
eDP panel in MT8188 EVB: "IVO R140NWF5 RH".
Panel spec name: R140NWF5 RH Product Specification
Firmware display eDP panel logs:
configure_display: Starting display initialization
SINK DPCD version: 0x11
SINK SUPPORT SSC!
Extracted contents:
header: 00 ff ff ff ff ff ff 00
serial number: 26 cf 7d 05 00 00 00 00 00 1e
version: 01 04
basic params: 95 1f 11 78 0a
chroma info: 76 90 94 55 54 90 27 21 50 54
established: 00 00 00
standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
extensions: 00
checksum: fb
Manufacturer: IVO Model 57d Serial Number 0
Made week 0 of 2020
EDID version: 1.4
BUG=b:244208960
TEST=see firmware display using eDP panel in MT8188 EVB.
Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Change-Id: I67e0699c976c6f85e69d40d77154420c983b715e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68490
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
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Configure ChromeOS specific GPIOs:
- Open-drain pins to high-z mode:
GPIO_EC_AP_INT_ODL, GPIO_GSC_AP_INT_ODL and GPIO_WP_ODL.
- GPO mode:
GPIO_AP_EC_WARM_RST_REQ, GPIO_EN_SPKR and GPIO_XHCI_INIT_DONE.
This patch is based on MT8188G_GPIO_Formal_Application_Spec_V0.3.
TEST=build pass
BUG=b:236331724
Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Change-Id: I84d3f62ec8a3966fe1982d5d4cf6ff270450d4bf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66274
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Initialize I2C bus 1 for TPM control.
TEST=build pass
BUG=b:236331724
Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Change-Id: If5807c9bb39260315ecbc55305def483bd2b8c51
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66273
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Initialize SPI bus 0 for Chrome EC control.
TEST=build pass
BUG=b:236331724
Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Change-Id: I6de5ea8a0273a3b0c725e4cdbcf69f4db74c5db7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66272
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
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