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path: root/src/mainboard/google/geralt/Makefile.inc
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2023-08-11mb/google/geralt: Add reset.c for bootblockYidi Lin
VBOOT_CBFS_INTEGRATION needs board_reset in its logic. Otherwise, it will cause a build failure. BUG=b:294643742 TEST=build coreboot Change-Id: Ia4b81d8add71e62707f6b5a747d270caba502174 Signed-off-by: Yidi Lin <yidilin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77118 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2023-08-11mb/google/geralt: Move I2C and SPI initialization to verstageYidi Lin
After enabling VBOOT_CBFS_INTEGRATION, bootblock exceeds allocated size (60K) by 3.5K. Since TPM and EC won't be accessed in bootblock, we move I2C and SPI initializaion to verstage to reduce bootblock size. The GSC interrupt pin configuration is also moved to verstage to save more spaces for bootblock. The size of bootblock.raw.bin is reduced from 64,040 bytes to 60,808 bytes. BUG=b:294643742 TEST=boot to kernel Change-Id: I5f6855d5a1a0fce6e739d44652c88e406f6f7b89 Signed-off-by: Yidi Lin <yidilin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77107 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2023-08-06mainboard: Add SPDX license headers to MakefilesMartin Roth
To help identify the licenses of the various files contained in the coreboot source, we've added SPDX headers to the top of all of the .c and .h files. This extends that practice to Makefiles. Any file in the coreboot project without a specific license is bound to the license of the overall coreboot project, GPL Version 2. This patch adds the GPL V2 license identifier to the top of all makefiles in the mainboard directory that don't already have an SPDX license line at the top. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: Ic451e68b1ad9ccdf34484dd98bd7fca7e177ef22 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68982 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Tim Crawford <tcrawford@system76.com> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-12-12mb/google/geralt: Put MIPI panel data in panel_geralt.cBo-Chen Chen
There are eDP and MIPI panels supported in geralt. We put the panels' specified functions - `power_on()` and `configure_panel_backlight()` in panel_geralt.c. Also provide the common interface `get_active_panel()` in panel.c to generalize the display initialization. Since each board may support a different set of MIPI panels, we put the MIPI data in a separate file panel_geralt.c. BUG=b:244208960 TEST=emerge-geralt coreboot Change-Id: Ie928759e020a916f29f0364201a3cf202dc512c3 Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70404 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-11-08vboot: Add VBOOT_CBFS_INTEGRATION supportJakub Czapiga
This patch introduces support signing and verification of firmware slots using CBFS metadata hash verification method for faster initial verification. To have complete verification, CBFS_VERIFICATION should also be enabled, as metadata hash covers only files metadata, not their contents. This patch also adapts mainboards and SoCs to new vboot reset requirements. TEST=Google Volteer/Voxel boots with VBOOT_CBFS_INTEGRATION enabled Signed-off-by: Jakub Czapiga <jacz@semihalf.com> Change-Id: I40ae01c477c4e4f7a1c90e4026a8a868ae64b5ca Reviewed-on: https://review.coreboot.org/c/coreboot/+/66909 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-25mb/google/geralt: Configure firmware display for eDP panelBo-Chen Chen
Add eDP panel power-on sequences and initialize the display in the ramstage. eDP panel in MT8188 EVB: "IVO R140NWF5 RH". Panel spec name: R140NWF5 RH Product Specification Firmware display eDP panel logs: configure_display: Starting display initialization SINK DPCD version: 0x11 SINK SUPPORT SSC! Extracted contents: header: 00 ff ff ff ff ff ff 00 serial number: 26 cf 7d 05 00 00 00 00 00 1e version: 01 04 basic params: 95 1f 11 78 0a chroma info: 76 90 94 55 54 90 27 21 50 54 established: 00 00 00 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a extensions: 00 checksum: fb Manufacturer: IVO Model 57d Serial Number 0 Made week 0 of 2020 EDID version: 1.4 BUG=b:244208960 TEST=see firmware display using eDP panel in MT8188 EVB. Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Change-Id: I67e0699c976c6f85e69d40d77154420c983b715e Reviewed-on: https://review.coreboot.org/c/coreboot/+/68490 Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-09-14mb/google/geralt: Raise little core CPU frequency from 500MHz to 2GHzRex-BC Chen
To improve boot time, raise little CPU from 500MHz to 2GHz at romstage (before DRAM calibration). FW logs: Check CPU freq: 1999968 KHz, cci: 1600012 KHz TEST=cpu freq and cci freq run correctly. BUG=b:244251006 Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Change-Id: Ic1bed53669baa15f797c9a952455376a39d29cf3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67544 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-27mb/google/geralt: Fully calibrate DRAMXi Chen
Initialize and calibrate DRAM in romstage. DRAM full calibration logs: dram_init: dram init end (result: 0) DRAM-K: Full calibration passed in 50176 msecs TEST=Full calibration pass. BUG=b:233720142 Signed-off-by: Xi Chen <xixi.chen@mediatek.com> Change-Id: I31f5693ffe4a1e30defbc8a96dc128de03d6b7e7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66278 Reviewed-by: Yidi Lin <yidilin@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-03mb/google/geralt: Implement SKU ID and RAM codeRex-BC Chen
- Retrieve the SKU ID for Geralt via CBI interface. If that failed (or no data found), fall back to ADC channels for SKU ID. - The RAM code is implemented by the resistor straps that we can read and decode from ADC. TEST=build pass BUG=b:236331724 Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Change-Id: I31626e44bd873a3866c9bd1d511b476737f15a20 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66275 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-22mb/google/geralt: Implement regulator interfaceHui Liu
Control regulator more easily with regulator interface. TEST=measure 3.0V in VMCH and VMC. BUG=b:236331724 Signed-off-by: Hui Liu <hui.liu@mediatek.corp-partner.google.com> Change-Id: I9727475774b3b9a8dcd49e5e60e133f9d745b407 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65875 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-04mb/google/geralt: Add MediaTek MT8188 reference boardRex-BC Chen
Add mainboard folder and drivers for new reference board 'Geralt'. TEST=saw the coreboot uart log to bootblock BUG=b:233720142 Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Change-Id: I5e437d46097369bef535ff64e6a693b7cf67f2f1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65586 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yidi Lin <yidilin@chromium.org>
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