| Age | Commit message (Expand) | Author |
|---|---|---|
| 2017-09-02 | mainboard/google/fizz: Enable support for DPTF | Tsai, Gaggery |
| 2017-08-25 | soc/intel/skylake: Add LPC and SPI lock down config option | Subrata Banik |
| 2017-07-14 | google/fizz: Override PL2 and SysPL2 values | Shelley Chen |
| 2017-06-28 | mainboard/google/fizz: Add audio devices | Kevin Cheng |
| 2017-06-20 | google/fizz: Enable cr50 over SPI | Shelley Chen |
| 2017-06-20 | google/fizz: Enable cr50 over i2c | Shelley Chen |
| 2017-05-05 | google/fizz: Enable devices under pci 1c.0 | Shelley Chen |
| 2017-04-27 | google/fizz: Enable SATA on port 1 | Shelley Chen |
| 2017-04-24 | mb/google/fizz: Configure PCI root port | Naresh G Solanki |
| 2017-04-13 | soc/intel/skylake: Split AC/DC settings for Deep Sx config | Duncan Laurie |
| 2017-03-23 | google/fizz: Update device tree from schematic | Shelley Chen |
| 2017-03-23 | google/fizz: Add new board | Shelley Chen |
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index : coreboot.git | |
| my copy of coreboot | gitea |
| aboutsummaryrefslogtreecommitdiff |