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path: root/src/mainboard/google/fizz/devicetree.cb
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2017-07-14google/fizz: Override PL2 and SysPL2 valuesShelley Chen
Set PL2 and SysPL2 for Fizz based on cpu id. BUG=b:7473486, b:35775024 BRANCH=None TEST=On bootup make sure PL2 and PsysPL2 values set properly (through debug output) Change-Id: I5c46667fdae9d8eed5346a481753bb69f98a071b Signed-off-by: Shelley Chen <shchen@chromium.org> Reviewed-on: https://review.coreboot.org/20420 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-06-28mainboard/google/fizz: Add audio devicesKevin Cheng
- Describe RT5663 headphone codec in ACPI so it can be enumerated by the OS. - Supply NHLT binaries for RT5663 BUG=b:62872377 TEST=Apply full patch set and UCM, verify basic audio works. Signed-off-by: Kevin Cheng <kevin.cheng@intel.com> Change-Id: I5bbd58b0e660cdf5089e6a6dd35a757ecf8ec076 Reviewed-on: https://review.coreboot.org/20305 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-06-20google/fizz: Enable cr50 over SPIShelley Chen
By default disabled. Will need to add FIZZ_USE_SPI_TPM config to enable. BUG=b:62456589, b:35775024 BRANCH=None TEST=Reboot and ensure that TPM works in verstage CQ-DEPEND=CL:530184 Change-Id: I14ce73a1c3745c996b79c4d4758ca744e63a46b4 Signed-off-by: Shelley Chen <shchen@chromium.org> Reviewed-on: https://review.coreboot.org/20134 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-06-20google/fizz: Enable cr50 over i2cShelley Chen
BUG=b:62456589, b:35775024 BRANCH=None TEST=Reboot and ensure verstage doesn't have any TPM errors CQ-DEPEND=CL:530185 Change-Id: Icfde0f62bd058d960fcb0c6fc67f9d8f6b9462f5 Signed-off-by: Shelley Chen <shchen@chromium.org> Reviewed-on: https://review.coreboot.org/20133 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-05-05google/fizz: Enable devices under pci 1c.0Shelley Chen
Turn on device 1c.0 in order to enable devices under it. BUG=b:37486021, b:35775024 BRANCH=None TEST=Boot from NVMe Change-Id: Ide66823283c58d2bea0c9886f762f0581741affe Signed-off-by: Shelley Chen <shchen@chromium.org> Reviewed-on: https://review.coreboot.org/19533 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-04-27google/fizz: Enable SATA on port 1Shelley Chen
BUG=b:37486021 BRANCH=None TEST=compile coreboot and make sure sda and sdb show up in /sys/class/block. Change-Id: I11344a4a5fc7e5b5d907d25439f92744a5fb70da Signed-off-by: Shelley Chen <shchen@chromium.org> Reviewed-on: https://review.coreboot.org/19450 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-04-24mb/google/fizz: Configure PCI root portNaresh G Solanki
Configure PCI root port as per schematic. Change-Id: I10ef682e8c54e22f328db5105d4da39c72ac2bed Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com> Reviewed-on: https://review.coreboot.org/19390 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-04-13soc/intel/skylake: Split AC/DC settings for Deep Sx configDuncan Laurie
Currently when enabling Deep S3 or Deep S5 it unconditionally gets enabled in both DC and AC states. However since using Deep S3 disables some expected features like wake-on-USB it is not always desired to enable the same state in both modes. To address this split the setting and add a separate config for Deep Sx in AC and DC states. All motherboards that set this config were updated, but there is no actual change in behavior in this commit. BUG=b:36723679 BRANCH=none TEST=This commit has no runtime visible changes, I verified on Eve that the Deep SX config registers are unchanged, and it compiles for all affected boards. Change-Id: I590f145847785b5a7687f235304e988888fcea8a Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/19239 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-03-23google/fizz: Update device tree from schematicShelley Chen
BUG=b:35775024 BRANCH=None TEST=Compiles successfully Change-Id: I92cf9baa4c3aefc6983511543d875e74a6b0bf94 Signed-off-by: Shelley Chen <shchen@chromium.org> Reviewed-on: https://review.coreboot.org/18944 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-03-23google/fizz: Add new boardShelley Chen
Creating google/fizz directory based on poppy (using kabylake and FSP 2.0). Only making name changes and Copyright year changes. Many poppy-specific configs left in and will be updated in follup CLs. BUG=b:35775024 BRANCH=None TEST=Compile fizz board Change-Id: Icab3639a53fef65e904e797028916fda879fff7c Signed-off-by: Shelley Chen <shchen@chromium.org> Reviewed-on: https://review.coreboot.org/18796 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-10-21 01:25:14 +0000